JPS61240682A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device with a miniature element and to improve the integrity of the element, by providing an insulation film around a gate electrode in a self-aligning manner and forming a channel with the use of the insulation film as a mask. CONSTITUTION:A thermal oxidation film 3 is formed on a region 2 in a substrate 1 where an impurity is diffused. Ions are implanted in a second diffusion region 5. Subsequently, an insulation layer 6 is applied thereon. A film 7 having good draping properties is further applied thereon. When the film 7 and the insulation layer 6 are etched until a gate electrode 4 is exposed, a part of the insulation layer 6 remains unetched. When the gate electrode 4 is etched with a mask of the insulation film 6, the insulation film 6 defines projections on the side wall thereof. When an insulation film 8 is deposited, it has a larger thickness around the gate electrode and a smaller thickness in the central region. The insulation film 8 is etched until the central region of the gate electrode 4 is exposed, and ions are implanted with a mask of the insulation film 8 so as to cancel the concentration of the impurity in the diffusion region 2 and to form a channel 9.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which a thick insulating film is formed on the peripheral portion of a gate electrode in a self-aligned manner, and a channel is formed in a self-aligned manner. .

[Technical background of the invention and its problems]

As shown in Fig. 2(a), in the conventional technology, due to the limitations of beam lithography, it is only possible to form a channel with a length approximately equal to that of the gate electrode, and it is also possible to shorten the channel by diffusing the source or drain laterally using thermal diffusion. In this case, the source or drain simultaneously diffuses in the depth direction as shown in (b), which tends to cause punch-through and short channel effects.

Therefore, in order to reduce the size of the device and increase the yield, it is important to form the channel length short and to form the channels above and below the gate in a self-aligned manner.

[Purpose of the invention]

This invention improves the drawbacks of the prior art described above.
An object of the present invention is to provide a method for manufacturing a semiconductor device in which a thick insulating film is formed on the peripheral portion of a gate electrode in a self-aligned manner, the insulating film is used as a mask, and a channel is formed by ion implantation technology.

[Summary of the invention]

Normally, when a thin film is deposited on a substrate with a step, the film thickness becomes thinner in the following order: the side of the step, the bottom of the step, and the top of the step. Therefore, an element region is created on the semiconductor substrate, and the source and
After a drain region is formed and a relatively thick gate electrode is formed, an insulator is deposited by processing, and the film with good coverage and the insulator are etched over the entire surface until the upper part of the gate electrode is exposed. The insulating layer remains in the peripheral area of the electrode and in the area where there is no gate electrode. When the gate electrode is etched to a desired thickness using the insulating film layer as a mask, a new step is formed in the insulating film on the side of the gate electrode. Here, after further depositing the second insulating film,
By etching the entire surface again until the upper part of the gate electrode is exposed, a thick insulating film layer can be formed in a self-aligned manner around the upper part of the gate electrode and on the sides of the gate electrode.

Here, an element is formed by forming a channel by ion implantation using the insulating film layer as a mask.

〔Effect of the invention〕

The device manufactured by the above steps has a structure as shown in FIG. 1(i), and the channel can be formed to be thinner than the limit of phosphorography and in a self-aligning manner.

Therefore, since it becomes possible to create a device that is smaller than the conventional device, the degree of integration of the device can be dramatically improved.

[Embodiments of the invention]

Embodiments of the present invention will be described with reference to FIGS. 1(a) to (i). FIG. 1(a) shows a region 2 on a P-type substrate 1 in which a Kn-type impurity, for example, phosphorus, is diffused to a concentration of 1×106 rIL.
After forming a thermal oxide film 3 of, for example, 200X, a gate electrode '4, such as polysilicon, is formed at a thickness of 6000X.

After A was deposited, a thin electrode 4 was formed by an etching process for about seven etchings.

FIG. 1(b) shows that the second diffusion region 5 is made of, for example, As.
．． Ion implantation was performed at 0x10 cm at 6.0 KeV.

After this, the first insulating film/ii 6 (ON'D SiO
t) t" For example, FIG. 1(C) shows a step view when 8,000 to 10,000 A is deposited or coated.Furthermore, FIG. 3 is a diagram in which a film 7 (photoresist) with good coverage and an etching rate of .

In this state, the film 7 has good coverage until the gate electrode is exposed.
, and the first insulating film layer 6 are etched by RIE using OtP*+CHF5 gas, the insulating film 6 will remain on the sides of the gate electrode 4 and in areas where there is no gate electrode. This situation is shown in FIG. 1(e).

Here, the gate electrode 4 is uniformly etched using the insulating film 6 as a mask. In order for the insulating film 6 to serve as a mask at this time, it is desirable that the etching resistance is 95 times or more superior to that of the gate electrode 4, although it depends on the amount of etching. Then, when the etching of the gate electrode 4 is finished leaving a desired film thickness, for example, 3000 to 4000×, the first
It is figure (f).

Here, the side wall of the insulating film 6 shown in FIG. 1(e) has a protruding shape. Next, insulating film 8 (CVD5iOt)
When deposited, a thick insulator is formed inside the protrusion, that is, at the periphery of the gate electrode 4, and a thin insulator is formed at the center of the gate electrode 4. (Fig. 1 Og).

Thereafter, the second insulating film layer 8 is etched until the center of the gate electrode 4 is exposed, as shown in FIG. 1(h). When boron ions are implanted as a channel portion using the second insulating film layer 8 as a mask, the phosphorus impurity concentration in the diffusion region 2 is canceled and a P-type channel 9 is formed.

(b) Cross-sectional view of FIG. 2 is a cross-sectional view showing the final shape of the element in a conventional example.

In the figure, 1.11... semiconductor substrate, 2... first diffusion region, 3
゜13... Oxide film, 4.14... Gate electrode, 5.
15... Second diffusion region, 6.16... First insulating film,
7... Film with good coverage, 8... Second insulating film, 9.1
9...Channel area.

Representative Patent Attorney Kensuke Chika (and 1 other person) No. 1
Figure 2 wa 7^

Claims (1)

[Claims] A step of processing a diffusion region and a gate electrode on a semiconductor substrate, covering the entire surface of this semiconductor substrate with a first insulating film, and depositing a film with good covering properties on top of which the etching rate is approximately equal to that of the first insulating film. etching the film with good coverage and the first insulating film over the entire surface until the upper layer of the gate electrode is exposed; etching the gate electrode with respect to the first insulating film; a step of forming a second insulating film over the entire surface, etching the entire surface, and etching the thin film portion of the concave portion of the second insulating film until the upper layer of the gate electrode is exposed; and second
1. A method of manufacturing a semiconductor device, comprising the step of forming a channel by ion implantation using an insulating film as a mask.