JPS61234555A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61234555A JPS61234555A JP60077370A JP7737085A JPS61234555A JP S61234555 A JPS61234555 A JP S61234555A JP 60077370 A JP60077370 A JP 60077370A JP 7737085 A JP7737085 A JP 7737085A JP S61234555 A JPS61234555 A JP S61234555A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- pad
- pad hole
- hole
- ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置に係り、特に、半導体チップにお
けるボンディングパッドの構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to the structure of a bonding pad in a semiconductor chip.
（従来の技術）
従来、半導体装置は半導体中央部にホトリソ拡散などに
より成形された半導体素子を、１などの金属材料で接続
して電子回路を形成し、これを外部接読用ボンディング
パッドを介して外部に接続するようになっており、外部
接続は内部配線に使用した金属材料と接合性の良いＡｌ
やＡｕなどのφ２０〜４０μｍの細線を用いて熱圧着方
式や超音波によって実施するようにしている。そして、
内部の配線に使用される金属の機械的ダメージや水分の
侵入による腐食を防止するために、ＣＶＤ（Ｃｈｅｍｉ
ｅａｌ Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔｉｏｎ）などに
より絶縁性保護膜が半導体チップ全面に形成されるが、
上記の外部接続用ボンディングパッドだけはエツチング
により穴あけを行う。これがＣＶＤパッド穴である。こ
のＣＶＤパッド穴をあける理由はＣＶＤ等の保護膜の上
からではボンディング用細線の接続ができないためであ
る。(Prior Art) Conventionally, in semiconductor devices, an electronic circuit is formed by connecting a semiconductor element formed by photolithographic diffusion or the like in the center of the semiconductor using a metal material such as 1, and this is connected via a bonding pad for external reading. The external connection is made of aluminum, which has good bonding properties with the metal material used for internal wiring.
This is carried out using a thermocompression bonding method or ultrasonic waves using a thin wire of φ20 to 40 μm such as or Au. and,
In order to prevent mechanical damage to metals used for internal wiring and corrosion due to moisture intrusion, CVD
An insulating protective film is formed over the entire surface of a semiconductor chip using a method such as real vapor deposition.
Only the above-mentioned external connection bonding pads are made by etching. This is the CVD pad hole. The reason why this CVD pad hole is formed is that it is impossible to connect a thin wire for bonding from above a protective film such as CVD.
第３図は係る半導体チップに使用されている外部接続用
ボンディングパッドの平面図であり、第４図は第３図の
ＴＶ−ＩＶ’平面図である。これらの図において、ｌは
外部接続用ボンディングパッドであり、Ａｌ配線によっ
て形成される。２は・絶縁膜、例えばＣＶＤ膜、３はＣ
ＶＤ膜２がエツチングされて開けられたパッド穴である
。このパッド穴３の寸法は約１００μｍ程度であり、外
部接続のためのボンディング時は約４０倍に拡大した光
学アイを使用してボンディングの位置のセットを行って
いる。ＣＶＤ膜厚２は１〜２μｍであり、薄くて透明な
ため４０倍程度の光学アイ（ＴＶカメラ）ではパッド穴
３の境界をセンシングできない。なお、光学アイにより
ボンディング領域を認識してボールボンドを行うことは
一般的に行われており、例えば特公昭５６−５０６２号
公報が挙げられる。そのため、ＣＶＤ膜２の下部にある
ボンディングパッドｌを形成するＡ１配線パターンの外
形よりパッド穴３の位置を推定してボンディングを行っ
ている。FIG. 3 is a plan view of a bonding pad for external connection used in such a semiconductor chip, and FIG. 4 is a plan view of TV-IV' in FIG. 3. In these figures, l represents a bonding pad for external connection, which is formed by Al wiring. 2 is an insulating film, for example a CVD film, and 3 is a C
This is a pad hole made by etching the VD film 2. The size of this pad hole 3 is approximately 100 μm, and when bonding for external connection, an optical eye magnified approximately 40 times is used to set the bonding position. The CVD film thickness 2 is 1 to 2 μm, and because it is thin and transparent, the boundaries of the pad holes 3 cannot be sensed with an optical eye (TV camera) of about 40 times. Note that it is common practice to perform ball bonding by recognizing the bonding area using an optical eye, for example, as disclosed in Japanese Patent Publication No. 56-5062. Therefore, bonding is performed by estimating the position of the pad hole 3 from the outline of the A1 wiring pattern forming the bonding pad 1 under the CVD film 2.
（発明が解決しようとする問題点）
ところでボンディングパッド１を形成するＡｌ配線パタ
ーンには多種多様のものがある。例えば、第５図（ａ）
に示されるようにＡｌ配線によって形成されるボンディ
ングパッド１の領域が横に長くなっているような場合や
、第５図（ｂ）に示されるようにＡｌ配線のボンディン
グパッド１の領域が縦に長くなっているような場合があ
る。このような場合には図に示されるようにボンディン
グのためのパッド穴３が設けられ、第５図（ｃ）及び（
ｄ）に示されるように、例えばＡｕボール４によるボー
ルボンドが行われると問題はないのであるが、前記した
ようにＣＶＤ膜２の膜厚は１〜２μｍであり、薄くて透
明なため光学アイではパッド穴３の境界をセンシングで
きないために、第５図（Ｐ３）及び第５図（ｆ）に示さ
れるようにバンド穴の位置を誤って所定のパッド穴３よ
りずれた位置にあるものとして推定してボールボンドを
行うといった問題があった。このようにＡｕボール４の
ボンディング時のセツティングミスが発生すると、Ａｕ
ボール４の接着面積が不足してはがれる可能性がある。(Problems to be Solved by the Invention) By the way, there are a wide variety of Al wiring patterns forming the bonding pad 1. For example, Fig. 5(a)
As shown in FIG. 5(b), the area of the bonding pad 1 formed by the Al wiring is long horizontally, or as shown in FIG. 5(b), the area of the bonding pad 1 formed by the Al wiring is vertical Sometimes it seems like it's getting longer. In such a case, a pad hole 3 for bonding is provided as shown in the figure, and as shown in FIGS.
As shown in d), there is no problem if ball bonding is performed using, for example, Au balls 4, but as mentioned above, the thickness of the CVD film 2 is 1 to 2 μm, and it is thin and transparent, so it cannot be seen by optical eyes. In this case, since the boundary of the pad hole 3 cannot be sensed, the band hole is incorrectly located at a position shifted from the predetermined pad hole 3 as shown in FIG. 5 (P3) and FIG. 5 (f). There was a problem that ball bonding was performed based on estimation. If a setting error occurs during bonding of the Au ball 4 in this way, the Au
There is a possibility that the adhesive area of the ball 4 is insufficient and the ball 4 comes off.
例えば、ＭＩＬ規格ではＡｕボール全体の面積の７５％
以上がボンディングパッド内になくてはならないと定め
られているが、上記ボールボンディングによれば、この
規格に適合せず、不良品となってしまうことになる。For example, according to the MIL standard, 75% of the total area of the Au ball
Although it is stipulated that the above must be present in the bonding pad, the above-mentioned ball bonding does not comply with this standard, resulting in a defective product.
また、ボンディングは自動化されている。っまり、まず
、目視により人為的に各パッド穴の位置をワイヤボンダ
のメモリに入力し、以降はメモリされた座標に基づいて
自動ボンディングが行われるようになっている。そこで
、上記したように穴の位置が誤って推定されるとメモリ
に人力する際に誤座標を入力してしまい、誤った位置に
自動的にボンディングされることになり、不良品を多量
に製造するといった問題があった。Additionally, bonding is automated. In other words, first, the position of each pad hole is manually entered into the wire bonder's memory by visual inspection, and then automatic bonding is performed based on the memorized coordinates. Therefore, as mentioned above, if the position of the hole is incorrectly estimated, the wrong coordinates will be entered when manually inputting it into the memory, and the bond will be automatically bonded at the wrong position, resulting in the production of a large number of defective products. There was a problem with doing so.
更に、チップ外観検査時には基準となるパッド穴３の位
置が確定できないためにＡｕボールのずれが判定できな
いことになり、不良品を良品としてしまうといった問題
があった。Furthermore, since the position of the pad hole 3, which serves as a reference, cannot be determined during chip appearance inspection, the displacement of the Au ball cannot be determined, and there is a problem in that a defective product is judged as a non-defective product.
本発明は、上記の問題点を除去し、外部接続のための配
線を迅速かつ的確に行うことができ、しかもチップ外観
検査を効率よ〈実施できる半導体装置を提供することを
目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device that eliminates the above-mentioned problems, allows quick and accurate wiring for external connections, and allows efficient chip appearance inspection.
（問題点を解決するための手段）
本発明は上記問題点を解決するために、半導体チップの
外部接続用ボンディングパッドと、該ボンディングパッ
ドを覆う絶縁膜と、該絶縁膜が除去されるパッド穴とを
有し、前記ボンディングパッドには前記パッド穴の位置
を識別するマークを付すように構成する。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a bonding pad for external connection of a semiconductor chip, an insulating film covering the bonding pad, and a pad hole from which the insulating film is removed. and a mark for identifying the position of the pad hole is attached to the bonding pad.
（作用）
本発明によれば、上記したように、半導体チップのボン
ディングパッドには、パッド穴の位置を識別するための
識別マークが設けられるために、作業者はパッド穴の位
置を迅速かつ的確に識別し、正確なボンディング位置を
確定して信頼性の高い外部接続を行い得る。(Function) According to the present invention, as described above, since the bonding pad of the semiconductor chip is provided with an identification mark for identifying the position of the pad hole, the operator can quickly and accurately identify the position of the pad hole. can be identified and the exact bonding location can be determined to make reliable external connections.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明に係るボンディングパッドの平面図、第
２図は本発明に係るボンディングパッドの断面図である
。図中、１は外部接続用ボンディングパッドであり、例
えばＡ１配線によって形成される。２は絶縁膜、例えば
ＣＶＤ膜、３は絶縁膜２が除去されて開けられたパッド
穴、５はパッド穴３を識別するためのマークである。FIG. 1 is a plan view of a bonding pad according to the present invention, and FIG. 2 is a cross-sectional view of the bonding pad according to the present invention. In the figure, 1 is a bonding pad for external connection, which is formed by, for example, an A1 wiring. 2 is an insulating film, for example, a CVD film; 3 is a pad hole formed by removing the insulating film 2; and 5 is a mark for identifying the pad hole 3.
これらの図に示されるように、識別マーク５としてはボ
ンディングパッド１のパッド穴３の終点には約１０μｍ
平方の四角形の切り込みを２箇所設ける。これによって
パッド穴３の境界を識別し、Ａｕボールを圧着するボン
ディング領域を明示することができる。As shown in these figures, the identification mark 5 is approximately 10 μm at the end point of the pad hole 3 of the bonding pad 1.
Make two square rectangular cuts. This makes it possible to identify the boundary of the pad hole 3 and clearly indicate the bonding area where the Au ball is to be pressed.
第６図（ａ）及び（ｂ）は本発明に係るボンディングを
行った半導体装置の平面図であり、この図に示されるよ
うに、パッド穴３の位置は識別マーク５に基づいて正確
に識別され、Ａｕボール４は所定の位置にボンディング
される。6(a) and 6(b) are plan views of a semiconductor device bonded according to the present invention, and as shown in these figures, the position of the pad hole 3 can be accurately identified based on the identification mark 5. Then, the Au ball 4 is bonded to a predetermined position.
第７図は第２の実施例を示す半導体装置の平面図であり
、識別マーク６としてパッド穴３の終点に三角形の突起
を２箇所に設けるようにしたものである。FIG. 7 is a plan view of a semiconductor device showing a second embodiment, in which two triangular protrusions are provided as identification marks 6 at the end points of pad holes 3.
第８図は第３の実施例を示す半導体装置の平面図であり
、識別マーク７としてパッド穴３の終点に三角形の切り
込みを２箇所設けるようにしたものである。FIG. 8 is a plan view of a semiconductor device showing a third embodiment, in which two triangular notches are provided as identification marks 7 at the end points of pad holes 3.
第９図は第４の実施例を示す半導体装置の平面図であり
、識別マーク８として四角形の突起を１箇所に設けるよ
うにしたものである。FIG. 9 is a plan view of a semiconductor device showing a fourth embodiment, in which a rectangular projection is provided as an identification mark 8 at one location.
第１０図は第５の実施例を示す半導体装置の平面図であ
り、識別マーク９として三角形の切り込みを１箇所設け
るようにしたものである。FIG. 10 is a plan view of a semiconductor device showing a fifth embodiment, in which a triangular notch is provided as an identification mark 9 at one location.
このようにボンディング用のパッド穴の終点部にはボン
ディング用のパッド穴の位置を識別するための各種のマ
ークを付設するようにする。従って、作業者はボンディ
ング位置を迅速かつ的確に識別することができ、正確な
位置にボンディングを行うことができる。In this way, various marks for identifying the position of the bonding pad hole are attached to the end point of the bonding pad hole. Therefore, the operator can quickly and accurately identify the bonding position and perform bonding at the correct position.
また、Ａｕボール配線後に行うチップの外観検査時には
、上記識別マークに基づいてＡｕボールのずれは容易に
発見できることになる。Furthermore, when inspecting the appearance of the chip after wiring the Au balls, any misalignment of the Au balls can be easily found based on the identification mark.
更に、上記したパッド穴の識別マークの位置は半導体チ
ップに設けられる複数のボンディングパッドの全てに対
して行う。従って、上記識別マークを付設することによ
り、多量処理における自動ボンディングのために各ボン
ディング位置座標をメモリに入力する際に、その入力は
迅速かつ的確に行われ、誤座標を入力することがない。Furthermore, the positions of the pad hole identification marks described above are determined for all of the plurality of bonding pads provided on the semiconductor chip. Therefore, by attaching the identification mark, when inputting the coordinates of each bonding position into the memory for automatic bonding in large-volume processing, the input is performed quickly and accurately, and there is no possibility of inputting erroneous coordinates.
また、本発明は上記の実施例に限定されるものではなく
、本発明の趣旨に基づいて種々の変形が可能であり、こ
れらを本発明の範囲から排除するものではない。Further, the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、半導体
チップの外部接続用ボンディングパッドと、該ボンディ
ングパッドを覆う絶縁膜と、該絶縁膜が除去されるパッ
ド穴とを有し、前記ボンディングパッドには前記バンド
穴の位置を識別するマークを付すようにしたので、
（１）ボンディングを行うべきバンド穴の位置を迅速か
つ、的確に識別することができ、信頼性の高い外部接続
を実施することができる。(Effects of the Invention) As described above in detail, according to the present invention, a bonding pad for external connection of a semiconductor chip, an insulating film covering the bonding pad, and a pad hole from which the insulating film is removed are provided. Since the bonding pad is provided with a mark to identify the position of the band hole, (1) the position of the band hole where bonding is to be performed can be quickly and accurately identified, and reliability is improved. High external connectivity can be implemented.
（２）パッド穴の位置を正確にメモリに目視入力できる
ので自動ボンディングを正確な位置に実施することがで
きる。(2) Since the position of the pad hole can be accurately visually input into the memory, automatic bonding can be performed at the correct position.
（３）チップ外観検査時に基準となるパッド穴のイ１１
＜朧５！Ｉ＋ ７’去スの１−ゼールゼンＶ小Ｊ台署ず
ｈの判定を確実に行うことができる。(3) Pad hole I11, which serves as a reference during chip appearance inspection
<Oboro 5! It is possible to reliably judge the 1-Seelzen V small J table of I + 7' left.
このように本発明によれば、簡単な構成にもかかわらず
、信頬性の高い半導体装置を得ることができる。As described above, according to the present invention, a highly reliable semiconductor device can be obtained despite its simple configuration.
第１図は本発明に係るボンディングパッドの平面図、第
２図は同ボンディングパッドの断面図、第３図は従来の
ボンディングパッドの平面図、第４図は従来のボンディ
ングパッドの断面図、第５図は従来のボンディングにお
ける問題点説明図、第６図は本発明に係るボンディング
を行ったの半導体装置の平面図、第７図乃至第１０図は
本発明の他の実施例をそれぞれ示す半導体装置の平面図
である。
１・・・ボンディングパッド、２・・・絶縁膜、３・・
・パッド穴、４ ・・−Ａ ｕボール、５．６．７．８
．９・・・バンド穴の識別マーク。1 is a plan view of a bonding pad according to the present invention, FIG. 2 is a sectional view of the same bonding pad, FIG. 3 is a plan view of a conventional bonding pad, and FIG. 4 is a sectional view of a conventional bonding pad. 5 is a diagram explaining problems in conventional bonding, FIG. 6 is a plan view of a semiconductor device subjected to bonding according to the present invention, and FIGS. 7 to 10 are diagrams showing other embodiments of the present invention. FIG. 2 is a plan view of the device. 1... Bonding pad, 2... Insulating film, 3...
・Pad hole, 4...-A u ball, 5.6.7.8
．． 9... Band hole identification mark.
Claims (1)
ンディングパッドを覆う絶縁膜と、該絶縁膜が除去され
るパッド穴とを有し、前記ボンディングパッドには前記
パッド穴の位置を識別するマークを付すようにしたこと
を特徴とする半導体装置。The semiconductor chip has a bonding pad for external connection of a semiconductor chip, an insulating film covering the bonding pad, and a pad hole from which the insulating film is removed, and the bonding pad is provided with a mark for identifying the position of the pad hole. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60077370A JPS61234555A (en) | 1985-04-11 | 1985-04-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60077370A JPS61234555A (en) | 1985-04-11 | 1985-04-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61234555A true JPS61234555A (en) | 1986-10-18 |
| JPH0464464B2 JPH0464464B2 (en) | 1992-10-15 |
Family
ID=13632008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60077370A Granted JPS61234555A (en) | 1985-04-11 | 1985-04-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61234555A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02163948A (en) * | 1988-12-17 | 1990-06-25 | Nec Corp | Semiconductor integrated circuit device |
| JPH0689676A (en) * | 1992-01-08 | 1994-03-29 | Nec Corp | Driving semiconductor element-incorporated fluorescent character display panel |
| JPH0851113A (en) * | 1994-08-05 | 1996-02-20 | Sony Corp | Semiconductor integrated circuit and manufacture thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49131381A (en) * | 1973-04-18 | 1974-12-17 |
-
1985
- 1985-04-11 JP JP60077370A patent/JPS61234555A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49131381A (en) * | 1973-04-18 | 1974-12-17 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02163948A (en) * | 1988-12-17 | 1990-06-25 | Nec Corp | Semiconductor integrated circuit device |
| JPH0689676A (en) * | 1992-01-08 | 1994-03-29 | Nec Corp | Driving semiconductor element-incorporated fluorescent character display panel |
| JPH0851113A (en) * | 1994-08-05 | 1996-02-20 | Sony Corp | Semiconductor integrated circuit and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0464464B2 (en) | 1992-10-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |