JPS61234541A - Inspecting method for transistor array - Google Patents

Abstract

PURPOSE:To implement high speed inspection, by inspecting the performance of each transistor through a capacitor, which is constituted by both electrodes and one main electrode of each transistor. CONSTITUTION:A gate electrode 2 is formed on a substrate 1 comprising glass and the like. A semiconductor layer 4 is formed through an insulating layer 3. On the semiconductor layer 4, doping layers 5 and 5' for ohmic contact are formed. Two main electrodes are evaporated in contact with the doping layers. A drain electrode 7 is connected to a picture element electrode 8, which is formed on the substrate 1. The picture element electrode 8 is in an electrically opened state. On the picture element electrode 8, a surface electrode 10 is formed so as to hold the insulating layer 3 and an insulating layer 9 for protecting the semiconductor layer 4. A TFT is constituted by the gate electrode 2, the insulating layer 3 as the gate insulating film, the semiconductor layer 4, a source electrode 6 and the drain electrode 7. A capacitor is constituted by the picture element electrode 8, the surface electrode 10 and the insulating layers 3 and 9. The performance of each transistor is inspected through said capacitor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for testing a transistor array, and particularly to a method for easily and quickly testing a transistor array in which a plurality of transistors are arranged on the same substrate. .

The transistor array testing method according to the present invention is applied to, for example, performance testing of thin film transistor (hereinafter referred to as FT) arrays used in liquid crystal display elements, liquid crystal shutter arrays, line sensors, thermal heads, and the like.

[Prior Art] Conventionally, the following three testing methods have been mainly used to test TFT arrays.

(a) Device using TFT array as driving means (
For example, in the case of a liquid crystal display device, etc., after the device itself is completed, the performance of the TFT array is tested by connecting it to the TFT array and operating it.

(b) In the process of manufacturing a TFT array, before forming a protective insulating layer, the operation of each TPT is directly checked using a probe or the like.

(c) On the same substrate as the TFT array actually used,
The performance of the actual TFT array is estimated by providing a test TFT or TFT AS-I or in the vicinity thereof and checking the operation of the test ↑FT.

[Problems to be Solved by the Invention] However, the above-mentioned conventional inspection method had the following problems.

In the method shown in (a), for example, a liquid crystal display device is
Since the TFT array is inspected by driving it with a T array, it is not possible to determine whether a defect in a certain part of the liquid crystal display is caused by the TFT or the liquid crystal cell. , since the TFT array cannot be inspected until the TFT array and liquid crystal cell formation processes are completed, if the yield of liquid crystal cells formed after the TFT array formation process is poor, the TFT array As a result, the yield of liquid crystal display devices is significantly reduced compared to a method in which inspection is performed at the stage where the liquid crystal display device is formed.

In the method shown in (b), T
Since the FT array is being tested, there is a possibility of degrading the TPT. Furthermore, test probes are attached to each T.
Since each PT or multiple TPTs must be sequentially connected and tested, the time required for testing increases as the number of TPTs increases.

In the method shown in (C), the performance of the TFT array is estimated from the performance of a small number of test TPTs, and therefore, reliable testing cannot be performed.

[Summary of the Invention] The present invention aims to solve the above problems, and a method for testing a transistor array according to the present invention includes: a method for testing a transistor array in which a plurality of transistors are arranged on the same substrate; A surface electrode is formed on or below the transistor array via an insulating layer, and the performance of each transistor is checked via a capacitor constituted by the surface electrode and one main electrode of each transistor. shall be.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of a TPT of an active liquid crystal display element to which an embodiment of the inspection method according to the present invention is applied. However, here, the stage in which the formation of TPT has been completed in the manufacturing process of the liquid crystal display element is shown.

In the figure, a substrate made of a material such as glass or plastic! A gate electrode 2 is formed thereon, and a semiconductor layer 4 is further formed with an insulating layer 3 interposed therebetween. The semiconductor layer 4 has a doping layer 5 for making ohmic contact.
and 5' are formed, and two main electrodes (here a source electrode 6 and a drain electrode 7) are deposited in contact with each doping layer.

Drain electrode 7 is a substrate! An insulating layer 8 for protecting the insulating layer 3 and the semiconductor layer 4 is sandwiched over the 0 pixel electrode 8 which is connected to the pixel electrode 8 formed above and the pixel electrode 8 is kept in an electrically open state. The materials of the zero-plane electrode 10 on which the plane electrode 10 is formed include AI, Cr, and N.
It is a metal such as O, W, Ta, NiCr, Au, or Pt, or a conductive oxide film such as ITO or 5n02.

A TPT is constituted by the gate electrode 2, the insulating layer 3 as a gate insulating film, the semiconductor layer 4, the source electrode 8, and the drain electrode 7, and the pixel electrode 8, the surface electrode 10, and the insulating layer 3.
and 8 constitute a capacitor.

FIG. 2 is a perspective view of a pixel electrode portion of a liquid crystal display element in which TPTs shown in FIG. 1 are arranged in a matrix. As described later, the gate electrode 2 of each ↑FT is connected to the line L for each row.
a, Lb, . . . , and the source electrodes 6 are commonly connected to lines Va, Vb, . . . for each column.

FIGS. 3A to 3D are basic test circuit diagrams for measuring the charging and discharging current of a capacitor flowing through a TFT, respectively. However, in each figure, element S is TPT
and a capacitor C, and the capacitor C is composed of the pixel electrode 8 and the surface electrode 10 connected to one main electrode of the TPT as described above.

In FIG. 3(A), the surface electrode 10 is grounded via a capacitor C1, and the capacitors C and C1 are charged and discharged by the on/off operation of the TPT.

, by detecting the resulting potential difference across the capacitor C1 with the voltage follower operational amplifier 11,
The current flowing through the TFT can be measured, and it is possible to determine whether the TFT is good or bad.

Similarly, in FIG. 3(B), the surface electrode lO has a resistance R,
By detecting the potential difference across the resistor R1, the current flowing through the TFT can be measured.

In FIG. 3(C), the surface electrode 10 is connected to the operational amplifier 11.
and a capacitor C2, and the amount of charge charged in the capacitor C is obtained as an output of the integrating circuit.

In FIG. 3(D), the surface electrode lO is connected to the operational amplifier 11.
and a resistor R2, and the charging/discharging current flowing through the capacitor C is measured.

By using the circuit as described above and measuring the charging and discharging current of the capacitor C, the performance of the TPT can be easily checked.

FIG. 4 is an equivalent circuit diagram of the pixel electrode section including the surface electrode shown in FIG. 2. Here, the elements Saa to Sdc are arranged in a 3×4 matrix as an example, and the front suffix indicates the rows (a, b, c, d), and the rear suffix indicates the column (a
, b, and c) are shown, respectively.

In addition, the elements 5aa-Sdc are the elements S shown in FIG.
is the same as

In FIG. 4, the gate electrode 2 of the TPT of each element is commonly connected to the line La-Ld for each row, and the TPT of each element is
The source electrodes 6 of each column are commonly connected to lines Va-Vc. Further, the surface electrode 10 is connected to a current detector 12 as shown in FIG.

Using such a circuit configuration, the TPT is tested as follows.

FIG. 5 is a timing waveform diagram showing one embodiment of the present invention.

In the figure, first, a positive potential is applied to line Va, and during that time gate pulses are sequentially applied to lines La-wLd. As a result, the TPTs of the elements Saa to Sda in the first column are sequentially turned on, the capacitor C is sequentially charged with positive charge, and the current at that time is detected by the current detector 12. Thereafter, in the same manner, the charging currents of the capacitors C of the elements in the second column and the third column are sequentially detected.

Here, the charging currents of the capacitors C of all the elements S aax S da are measured within the period Tl.

Subsequently, each capacitor C is charged with a negative charge in the same order within one period T2, and the charging current is measured.

In the above test sequence, for example, if the sixth output of the current detector 12 in each period is abnormal,
It can be determined that the TPT of element sbb is defective.

Although this embodiment shows the case where the inspection is performed by scanning column by column, it is of course not limited to this. As shown in FIG. 6, TPT is turned on for each row and the period T
1, a positive voltage and a period T2, a negative voltage are sequentially applied to the line V.
The charging current may be measured by applying it to a-Vc, however, in this case, for example, the TP of element sbb
If T is defective, the fifth output of the current detector 12 will be abnormal.

Furthermore, if the surface electrode 10 is unnecessary after the above-described inspection is completed, it is sufficient to remove the surface electrode 10 by etching, leaving only the light-shielding layer 13 of the TFT, as shown in FIG.

FIG. 8 shows a cross section of a device in which a surface electrode 10 is formed under the transistor array with an insulating layer 9 interposed therebetween. The testing method for this device is the same as the testing method for the device shown in Fig. 1. After the testing is completed, the surface electrode 10 forms an additional capacitance as a counter electrode to the pixel electrode 8, and is used as a component constituting a circuit. can do.

Furthermore, the inspection method according to the present invention is not only applicable to liquid crystal display devices, but also applies to devices that have transistors (not limited to TPT) arranged in an array and are capable of forming surface electrodes. Any device can be applied as long as it exists at least during the manufacturing process.

[Effects of the Invention] As explained in detail above, the transistor array testing method according to the present invention enables high-speed performance testing of all transistors by simply forming a plane electrode on or below the transistor array via an insulating layer. It can be done easily and easily.

Further, since inspection can be easily performed during the manufacturing process of a device including a transistor array, the yield of the device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view of a TPT of an active liquid crystal display element to which an embodiment of the inspection method according to the present invention is applied, and FIG. 2 is a liquid crystal display in which the TPTs shown in FIG. 1 are arranged in a matrix. A perspective view of the pixel electrode part of the display element, FIG. 3(A)
~(D) are basic test circuit diagrams for measuring the charging and discharging current of a capacitor flowing through a TPT, respectively. 4 is an equivalent circuit diagram of the pixel electrode section including the surface electrode shown in FIG. 2, FIG. 5 is a timing waveform diagram showing one embodiment of the present invention, and FIG. FIG. 7 is a timing waveform diagram showing an embodiment; FIG. 7 is a schematic cross-sectional view of a display element in which the surface electrode is removed by etching and made into a light shielding layer after testing the active liquid crystal display element in FIG. 1; FIG. FIG. 3 is a schematic cross-sectional view of a TPT of another active liquid crystal display element. 2...Front gate electrode 3,8...Insulating layer 8.7...
Fist/main electrode 8... Pixel electrode lO... Surface electrode Agent Patent attorney Seki Yamashita Taira va vb vc Figure 3 (A) (B) (C)
(D) Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] (1) In a method of inspecting a transistor array in which a plurality of transistors are arranged on the same substrate, a plane electrode is formed on or below the transistor array via an insulating layer, and one of the plane electrode and each of the transistors is formed. A method for testing a transistor array, comprising checking the performance of each of the transistors through a capacitor formed by a main electrode of the transistor.