JPS61232721A - Amplitude converting circuit for logical signal - Google Patents

Abstract

PURPOSE:To execute the expected action even when the temperature of the semiconductor logic circuit rises by connecting serially the first channel type electric field effect transistor, a diode circuit, and the second channel type electric field effect transistor between the first and second electric power source terminals. CONSTITUTION:When a small amplitude logic signal SB is obtained by a high electric potential VBH from an output terminal 4, the resistance of a diode 21 is decreased as the temperature rises, and therefore, the drop voltage of a diode circuit D1 is decreased as the temperature rises, and the value of the high electric potential given to the gate of the electric field effect transistor Q3 is increased as the temperature rises. Consequently, the voltage between the gate of Q3 and the source connected to an electric power source terminal E1 is decreased, the temperature dependency of the shifting degree of the carrier (electron) is a little only influenced by the temperature dependency of the drain electric current, and the value of the high electric potential VBH is increased as the temperature rises. Thus, the high electric potential VBH is obtained by having the value of the allowable scope of the high electric potential VCH of a small amplitude logic signal SC handled at a semiconductor logic circuit C, and even when the temperature rises, the expected action is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for converting large-amplitude logic signals such as those handled by semiconductor logic circuits constructed using field effect transistors into semiconductor logic circuits constructed using bipolar transistors. The present invention relates to an improvement in a logic signal amplitude conversion circuit that converts the signal into a small amplitude logic signal that can be handled in a logic circuit.

2. Description of the Related Art As such a logic signal amplitude conversion circuit, one having the configuration described below with reference to FIG. 2 has heretofore been proposed.

That is, it is indicated by the symbol B in FIG. 2, and for example, Ov
For example, -2, O
A field effect transistor 1 having a P-channel enhancement type and a resistor 2 are connected in series in that order between a power supply terminal E3 and a power supply terminal E3 at which a potential of V3 is obtained;
The input terminal 3 is led out from the gate of the field effect transistor 1, and the output terminal 4 is led out from the midpoint of the connection between the field effect transistor 1 and the resistor 2.

Conventional logic signal amplitude conversion circuit B having such a configuration
According to , a semiconductor logic circuit A (the details thereof are not shown) operated by a power source is provided between the above-mentioned power source terminal 1 and a power source terminal E2 from which a potential v2 of, for example, -5,2■ is obtained. The semiconductor logic circuit A outputs from its output terminal 5 a high potential VAl+, which is close to the potential V between the potential ■ of the power supply terminal E1 and the potential v2 of the power supply terminal E2, as "1" in binary representation, and the potential v
1 and v2, lower than the high potential VA11, e.g. -5
, 2V low potential VA, is configured to output a large-amplitude logic signal SA that indicates "0" in binary display, and that large-amplitude logic signal SA indicates "O" in binary display.
'', that is, a low potential vA, is applied to the input terminal 3 of the logic signal amplitude conversion circuit B. Since it is applied to the gate of the field effect transistor, the field effect transistor is turned on, and therefore the output terminal 4, a high potential ■8N is obtained which is lower than the potential V1 of the power supply terminal E1 by the voltage drop valve at the field effect transistor.

Further, from the output terminal 5 of the semiconductor logic circuit A, the above-mentioned large-amplitude logic signal SA is given to the input terminal 3 of the logic signal amplitude conversion circuit B, with a binary value of "1", that is, a high potential ■AFI. If it is, even if it is applied to the gate of the field effect transistor, the field effect transistor 1 will not turn on in this case, and therefore the output terminal 4 will receive a low potential approximately equal to the potential V3 of the power supply terminal E3. is obtained.

Therefore, now, for example, the same OV as obtained from the power supply terminal E1
A semiconductor logic circuit C that operates on a power source between a power supply terminal 1' where a potential v1' of the potential V1' is obtained and a power supply terminal E2 where a potential V1' of -5.2 V, which is the same as that obtained at the power supply terminal E2, is obtained. The semiconductor logic circuit C has a high potential V, for example -0.8V, at its input terminal 6, between the potential V1' of the power supply terminal E1' and the potential V2' of the power supply terminal E2'. )l
``1'' on the binary display, the potential between V1' and 2'
. A low potential ■ lower than □, for example -1°6V. , is "0" in binary display, and the amplitude +VCIl-VC,I between "1" in binary display and rOJ is "1" of large amplitude logic signal SA obtained at output terminal 5 of semiconductor logic circuit A. ” and r
The logic signal amplitude conversion circuit is configured to operate by being supplied with a small amplitude logic signal SC that is smaller than the amplitude IVAN 'ALI between OJ, and is connected to the input terminal 6 of such a semiconductor logic circuit C. When the output from the output terminal 4 is supplied, the potential v3 of the power supply terminal E3 is set to the potential v3 of the power supply terminal E2 to E2'.
', and approximately equal to the low potential C6 of the binary representation of "0" of the small amplitude logic signal SC, the large amplitude logic signal is applied from the output terminal 4 to the input terminal 3. It is possible to output a small amplitude logic signal SB having a smaller amplitude than SA.

Therefore, according to the conventional logic signal amplitude conversion circuit B shown in FIG. It has a function of converting it into a logic signal SB.

However, in the case of the conventional logic signal amplitude conversion circuit B shown in FIG. Since a large voltage is applied between the gate of the field effect transistor 1 and the source connected to the power supply terminal E1, the temperature dependence of the drain current of the field effect transistor 1 is It is only slightly affected by the temperature dependence of the threshold voltage, and therefore, the temperature dependence of the mobility of carriers (holes in this case) in the field effect transistor 1 is greatly influenced by the temperature dependence of the drain current of the field effect transistor 1. Therefore, the value of high potential ■BFI decreases with increasing temperature.

On the other hand, since the semiconductor logic circuit C is configured using bipolar transistors, the high potential (2) of the small amplitude logic signal SC handled by the semiconductor logic circuit C. The value of □ increases as the temperature increases.

Therefore, in the case of the conventional logic signal amplitude conversion circuit B shown in FIG. 2, when the temperature rises, the high potential V8 representing r7J in the binary representation of the small amplitude logic signal SB obtained from the output terminal 4
- a high potential V whose value represents "1" in the binary representation of the small amplitude logic signal SC to be supplied to the input terminal 6 of the semiconductor logic circuit C;
. , is obtained outside the allowable range, and there is a risk that the semiconductor logic circuit C will not operate as expected.

In the case of the conventional logic signal amplitude conversion circuit B shown in FIG. 2, the small amplitude logic signal SB obtained at the output terminal 4 is
The low potential ■BL that shows "0" on the value display is the power terminal E3.
Since the potential V3 of the power supply terminal E3 is almost equal to the potential ■3 determined by the potential V3 of the power supply terminal E3,
A low potential V representing "0" in binary representation of the small amplitude logic signal SC to be supplied to the input terminal 6 of the semiconductor logic circuit C. , it had to be a value within the possible range of .

By means of this method, the present invention seeks to propose a new logic signal amplitude conversion circuit, which does not have the above-mentioned drawbacks.

The logic signal amplitude conversion circuit according to the present invention has the following configuration.

That is, between the first N source terminal and the second power terminal,
a first field effect transistor having a first channel type; a first diode circuit consisting of one diode or a plurality of diodes connected in series;
a second field effect transistor having a second channel type opposite to that of the first diode circuit in their order and with respect to a power supply available between the first and second power supply terminals; Connected in series with forward polarity.

Further, a first field effect transistor is connected in parallel with the second field effect transistor.
resistor is connected.

Furthermore, a third field effect transistor having a second channel type and a second resistor are connected in series in that order between the first power supply terminal and the third power supply terminal. .

Further, in parallel with the third field effect transistor, a second diode circuit including one diode or a plurality of diodes connected in series connects the power source obtained between the first and third power terminals. It is connected with a polarity that is forward polarity.

Furthermore, the gate of the third field effect transistor is
It is connected to a connection midpoint between the first diode circuit and the second field effect transistor.

Furthermore, a common input terminal is led out from the gates of the first and second field effect transistors.

Furthermore, an output terminal is led out from a connection midpoint between the third field effect transistor and the second resistor.

The above is the configuration of the logic signal amplitude varying circuit according to the present invention.

Function: According to the logic signal amplitude conversion circuit according to the present invention having such a configuration, a large voltage similar to that applied to the input terminal 3 of the conventional logic signal amplitude conversion circuit B described above in FIG. 2 is applied to the input terminal. If the amplitude logic signal SA is given as "0" in binary representation, that is, at a low potential, the first and second field effect transistors are turned on and off, respectively, and the gate of the third field effect transistor is A high potential lower than the potential of the first power supply terminal by the sum of the voltage drop in the first field effect transistor and the voltage drop in the first diode circuit is applied, and the third field effect transistor is It remains on. Therefore, a high potential lower than the potential of the first power supply terminal by the voltage drop across the third field effect transistor can be obtained from the output terminal.

Moreover, the above-mentioned large amplitude logic signal SA is input to the input terminal.
If the value is "1", that is, a high potential is applied, the first and second field effect transistors are turned off and on, respectively, and the gate of the third field effect transistor is
A low potential approximately equal to the potential of the second power supply terminal is applied,
The third field effect transistor is turned off. For this reason,
A low potential that is lower than the potential of the first power supply terminal by the voltage drop in the second diode circuit is obtained from the output terminal.

Therefore, by appropriately selecting the potentials of the first, second, and third power supply terminals, the number of diodes in the first and second diode circuits, etc., a large amplitude can be applied from the output terminal to the input terminal. A small amplitude logic signal having a smaller amplitude than the logic signal can be output.

Therefore, also in the case of the logic signal amplitude conversion circuit according to the present invention,
Similar to the conventional logic signal amplitude conversion circuit described above in FIG. 2, it has a function as a logic signal amplitude conversion circuit.

However, in the case of the logic signal amplitude conversion circuit according to the present invention, a small amplitude logic signal is obtained from the output terminal at a high potential that is lower than the potential of the first power supply terminal by the voltage drop at the third field effect transistor. At this time, the voltage drop of the first diode circuit becomes lower as the temperature rises, and therefore, at this time, the potential of the first diode circuit becomes lower than the potential of the first power supply terminal applied to the gate of the third field effect transistor. The value of the high potential, which is lower by the sum of the voltage drop across the field effect transistor and the voltage drop across the first diode circuit, increases as the temperature rises. Therefore, the voltage between the gate of the third field effect transistor and the source connected to the first power supply terminal becomes low, and the temperature dependence of the drain current of the third field effect transistor changes depending on the third electric field. It is only slightly influenced by the temperature dependence of the threshold voltage of the effect transistor, so that the temperature dependence of the carrier mobility in the third field effect transistor is influenced by the temperature dependence of the drain current of the third field effect transistor. It is only slightly affected that the high potential value of the small amplitude logic signal available at the output terminal increases with increasing temperature.

Further, when a small amplitude logic signal is obtained from the output terminal at a potential lower than the potential of the first power supply terminal by the voltage drop in the second diode circuit, the value of the low potential is the voltage at the second diode circuit. The voltage drop is determined by the number of diodes making up the second diode circuit.

Effects Therefore, according to the logic signal amplitude conversion circuit according to the present invention,
Even if the small amplitude logic signal obtained from the output terminal is supplied to a semiconductor logic circuit configured using a bipolar transistor that handles the same small amplitude logic signal as described above in FIG. Since the high potential of the small amplitude logic signal handled by the semiconductor logic circuit constructed using bipolar transistors is within the permissible range of the high potential of the small amplitude logic signal handled by the semiconductor logic circuit constructed using bipolar transistors, There is no fear that the semiconductor logic circuit that has been manufactured will not operate as expected even if the temperature rises.

Furthermore, since the low potential value of the small amplitude logic signal obtained from the output terminal is determined by the number of diodes constituting the second diode circuit, the potential of the third power supply terminal is determined by the above-mentioned bipolar transistor. There is no restriction that the low potential of the small amplitude logic signal to be supplied to the input terminal of the semiconductor logic circuit configured using the semiconductor logic signal must be within the range of possible values.

Embodiment Next, an embodiment of the logic signal amplitude conversion circuit according to the present invention will be described with reference to FIG.

In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The logic signal amplitude conversion circuit B according to the present invention shown in FIG.
It has the following configuration.

In other words, the power supply terminal E1 where the potential ■1 is obtained, and the potential ■
2, a field effect transistor Q1 having a P-channel enhancement type, a diode circuit D1 consisting of, for example, one diode 21, and a field effect transistor having an N-channel enhancement type, connected between two obtained power supply terminals E2. Q2 are connected in series in their order and with polarity such that the diode circuit D1 has forward polarity with respect to the power source obtained between the power source terminals 1 and 7.

Further, a resistor R1 is connected in parallel with the field effect transistor Q2.

Furthermore, a field effect transistor Q3 having an N-channel depression type and a resistor R2 are connected in series in that order between the power supply terminal E1 and the power supply terminal E3 from which the potential v3 is obtained.

Further, a diode circuit D2 in which, for example, two diodes 22 are connected in series in parallel with the field effect transistor Q3 is connected with a polarity that is forward polarity with respect to the power source obtained between the power source terminals E1 and E3. There is.

Further, the gate of the field effect transistor Q3 is connected to the connection midpoint between the diode circuit D1 and the field effect transistor Q2.

Further, a common input terminal 3 is led out from the gates of the field effect transistors Q1 and Q2, and an output terminal 4 is led out from the midpoint of connection between the field effect transistor Q3 and the resistor R2.

The above is the configuration of the embodiment of the logic signal amplitude conversion circuit B according to the present invention.

According to the logic signal amplitude conversion circuit B according to the present invention having such a configuration, the large amplitude logic signal outputted from the output terminal 5 of the semiconductor logic circuit A is input to the input terminal 3 in the same way as described above in FIG. The signal SA is 2 as described above in FIG.
At the same low potential VA1 as "O" on the value display,
If given, it is the field effect transistors Q1 and Q
2, the field effect transistor Q
1 and Q2 are turned on and off, respectively, and a voltage at the gate of the field effect transistor Q3 is lower than the potential V1 of the power supply terminal E1 by the sum of the voltage drop across the field effect transistor Q1 and the voltage drop across the diode circuit D1. A high potential is applied to keep the field effect transistor Q3 on. Therefore, a high potential V811 is obtained from the output terminal 4, which is lower than the potential 1 of the power supply terminal E1 by the voltage drop of the field effect transistor Q3.

In addition, the above-mentioned large amplitude logic signal SA is input to the input terminal 3.
If a high potential VAH representing "1" is given in the same binary display as described above in FIG. Then, a low potential approximately equal to the potential V2 of the power supply terminal E2 is applied to the gate of the field effect transistor Q3, and the field effect transistor Q3 is turned off.

Therefore, a low potential VBL is obtained from the output terminal 4, which is lower than the potential 1 of the power supply terminal E1 by the voltage drop across the diode circuit D2.

Therefore, we now have a semiconductor logic circuit C configured using bipolar transistors similar to those described above in FIG.
In the case where the output from the diode circuit D2 is supplied, the potential 3 of the power supply terminal E3 is set to a value similar to that described above in FIG. 2, and the number of diodes 22 constituting the diode circuit D2 is If, for example, r2J is set in advance as described above, the output terminal 4 will have a smaller amplitude than the large amplitude logic signal SA applied to the input terminal 3 (its value is lV8H).
-V8. l ) can be outputted with a small amplitude logic signal SB. Therefore, in the case of the logic signal amplitude conversion circuit B according to the present invention shown in FIG. 1, as well as in the case of the conventional logic signal amplitude conversion circuit described above in FIG. It has a function of converting SA into a small amplitude logic signal SB similar to the small amplitude logic signal SC handled by the semiconductor logic circuit C.

However, in the case of the logic signal amplitude conversion circuit B according to the present invention shown in FIG.
When B is obtained at high potential VBH, diode circuit D1
Since the resistance of the diode 21 constituting the circuit decreases as the temperature increases, the voltage drop across the diode circuit D1 decreases as the temperature increases, and therefore, the voltage applied to the gate of the field effect transistor Q3 at this time. The potential of the power supply terminal E1 is higher than the field effect transistor Q1.
The value of the high potential, which is lower by the voltage valve equal to the sum of the voltage drop in the diode circuit D1 and the voltage drop in the diode circuit D1, becomes higher as the temperature rises.

Therefore, the voltage between the gate 1- of the field effect transistor Q3 and the source connected to the power supply terminal E1 becomes low, and the temperature dependence of the drain current of the field effect transistor Q3 becomes smaller than the threshold voltage of the field effect transistor Q3. Therefore, the temperature dependence of carrier (electron) mobility in the field effect transistor Q3 only slightly affects the temperature dependence of the drain current of the field effect transistor Q3. Therefore, the value of the high potential v8□ of the small amplitude logic signal SB obtained from the output terminal 4 increases as the temperature rises.

Therefore, the high potential V8Il of the small amplitude logic signal SB obtained from the output terminal 4 is the high potential V8Il of the small amplitude logic signal SC handled by the semiconductor logic circuit C. Since the value of H is within the permissible range, the semiconductor logic circuit C operates as expected even if the temperature rises.

Furthermore, when the small amplitude logic signal 8B is obtained from the output terminal 4 at the low potential mentioned above, the value of the low potential is determined by the number of diodes 22 constituting the diode circuit D2. It has an excellent feature that the potential 3 does not have to be a value within the range that the low potential VCL of the small amplitude logic signal SC to be supplied to the input terminal 6 of the semiconductor logic circuit C can take.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing an embodiment of a logic signal amplitude conversion circuit according to the present invention. FIG. 2 is a connection diagram showing a conventional logic signal amplitude conversion circuit. El, E1', E2, E2', E3 ...... Power terminals A, C...
...... Semiconductor logic circuit B...
・・・・・・・・・・・・・・・Logic signal amplitude conversion circuit 1, Ql, Q2, Q3 ・・・・・・・・・・・・・・・Field effect transistor 2, R1, R2

Claims (1)

[Claims] A first field effect transistor having a first channel type and one diode or a plurality of diodes are connected in series between a first power supply terminal and a second power supply terminal. and a second field effect transistor having a second channel type opposite to the first channel type; A first resistor is connected in series with a polarity that is forward polarity with respect to the power source obtained between the second power supply terminals, and a first resistor is connected in parallel with the second field effect transistor, and the first resistor is connected in parallel with the second field effect transistor. and a third field effect transistor having a second channel type between the and the third power supply terminal;
a second resistor connected in series in that order, and a second diode circuit consisting of one diode or a plurality of diodes connected in series in parallel with the third field effect transistor; With a polarity that is forward polarity with respect to the power obtained between the first and third power supply terminals,
connected, and the gate of the third field effect transistor is connected to the midpoint of the connection between the second diode circuit and the second field effect transistor, and the gate of the third field effect transistor is connected to the gate of the first and second field effect transistors. , an input terminal common to them is derived, and an output terminal is derived from a connection midpoint between the third field effect transistor and the second resistor.