JPS61232678A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Eleventh Industrial Field] The present invention relates to a semiconductor integrated circuit device having a MOS type structure, and particularly to a method for manufacturing a semiconductor integrated circuit device with improved radiation resistance.

[Conventional technology]

In recent highly integrated MOS type semiconductor integrated circuit devices, the entire source/drain region is formed in a region defined by a thick oxide film as an element isolation region by a self-line method that fully utilizes the gate electrode. Therefore, as shown in FIG. 2, the source/drain regions 22 formed in the semiconductor substrate 21 are not only in contact with the gate electrode 23 but also in the element isolation region 22.
4 has a structure in contact with both.

By the way, in a MOS type transistor having such a structure, especially a H-channel MOS type transistor, when exposed to radiation, a parasitic MOS type isolation MOS transistor (the entire gate insulating film is used in the element isolation region, and this is a MOS type transistor) and other MOS type transistors. A sudden increase in the subthreshold I-node current n'fl of a M(J)8 transistor whose source and drain regions are the source and drain of a MOS transistor.
: occurs, so it is not suitable for applications that require radiation resistance.

According to the inventor's study, the cause of the increase in the leakage current described above is the positive charge accumulated in the oxide film during radiation exposure and the increase in the interface state at the oxide film-silicon boundary. The thicker the oxide film is, the more the amount increases.

Therefore, in order to obtain radiation resistance, in the case of a MOS transistor, it is effective to separate the source/drain region from the thick oxide film region for isolation of all elements in order to prevent the influence of parasitic leakage.

For these reasons, the structure shown in FIG. 3 has been proposed. The figure shows an example of an N-channel MOS transistor, in which a gate electrode 23 and an N-type source/drain region 22, which together constitute the entire VCM08 transistor, are located inside an element isolation region 24 made of a thick oxide film.
P-type anti-inversion layer 2 with a high degree of #017 to 10"an"
5. It has a fully formed configuration.

In this structure, when forming the source/drain regions 22, it is not necessary to fully utilize the self-line method as described above.
), (B) is adopted 3, that is, (A
), after an element isolation region 24 is formed on a silicon substrate 21 by a conventional selective oxidation method, a P-type anti-inversion layer 25 is formed by a selective ion implantation method using a full mask (not shown). Then, the gate oxide film 26 and the gate electrode 2
After all three layers are formed, 27 mask material layers such as a silicon nitride film are formed on the entire surface, and a photoresist layer path is formed thereon, and the entire layer is patterned. Then, using this photoresist layer 28 as a mask, the mask removal layer 27 is etched as shown in the figure, and then the entire seventh photoresist layer 28 is removed as shown in FIG. 3).

All ions of hemi-type impurities are implanted to form source/drain regions 22.
is formed.

The reason why the mask material layer 27 is used is because of problems such as peelability and outgassing when ion implantation is performed at a high dose.
This occurs because the photoresist cannot be used as it is as a mask. [Problem to be solved by the invention] In the conventional manufacturing method described above, the source/drain region 2
The dimensional accuracy of No. 2 is determined by the etching accuracy of the mask material layer 27, but since wet etching is used for etching the mask material layer 27, it may be affected by variations in the thickness of the mask material layer and variations in etching. It is quite difficult to suppress the pattern dimensional accuracy of the mask material layer 27 to 2 to 3 μm or less.

For this reason, in the conventional method, the overlapping precision of the source/drain regions 22 (A in FIG. 4(B)) and the size of the source/drain regions 22 are adjusted by taking into account variations in dimensional accuracy in advance. ) must be quite large, which is an impediment to higher integration of semiconductor integrated circuit devices.

[Means to solve all problems]

The method for manufacturing a semiconductor integrated circuit device of the present invention includes the steps of forming the entire inversion prevention layer along the inside of the device isolation region by selective ion implantation using a mask after forming the device isolation region; An anisotropic method in which the entire gate electrode is formed in the defined device region, and a mask is provided on the nitride film that covers the anti-inversion layer while opening other device regions. The structure includes a step of forming a notch by a chemical etching method, and a step of performing ion implantation using a self-line using this nitride film and the gate electrode as a mask to form the entire source/drain region.

〔Example〕

Next, the present invention will be explained with reference to all the drawings.

Figure 1 (5) ~ @) shows the present invention being applied to N on a P-type silicon substrate.
FIG. 3 is a diagram illustrating in order of steps an embodiment applied to forming a channel MOS type transistor.

First, as shown in FIG. 1(A), a field oxide film 2 is formed on a P-type silicon substrate 1 using a selective oxidation method (LOCO8 method).
A gate oxide film 3 having a thickness of approximately 40.0 mm is formed in the element region defined by this field oxide film 2. E, 2, photoresist layer 4 formed on the entire surface
'fr, patterning is performed by photolithography technique to form a mask with a fully open portion along the inner edge of the field oxide film 2.

Then, a P-type impurity such as boron is introduced into the all-silicon substrate 1 to form an anti-inversion layer 5 along the inner edge of the field oxide film 2. Note that this inversion prevention layer 5 is fully ion-implanted so that the surface concentration is approximately 17 to 10180113 f).

Next, after removing the photoresist film 4, a gate electrode material such as polycrystalline silicon is formed on the entire surface to a thickness of about 500 OA, and etching is performed using photolithography technology to form the required gate electrode material as shown in (2) in the same figure. A patterned gate electrode 6 is formed.

Next, as shown in the same figure <C), a thermal oxide film 7 of about 500A is formed.
After the entire surface is formed, a silicon nitride film 8 of approximately t 000 A is formed on the entire surface, and furthermore, seven metresist layers 9 are formed again. Then, the photoresist layer 9 is formed using a photolithography technique using a pattern-shaped photomask (not shown) along the inner edge of the opening of the photoresist layer 9, that is, the inner edge of the anti-inversion layer 5 in the step (i) described above.
Butter the whole thing. Thereafter, the silicon nitride film 8 is patterned by anisotropic etching using the entire photoresist layer 9 as a mask. At this time, anisotropic etching is used and the thickness of the silicon nitride film 8 is 100 mm.
Due to two reasons: OA level and thinness, the pattern shape of the silicon nitride film 8 almost matches the pattern shape of the photoresist layer 9, and extremely high dimensional accuracy can be obtained.

Next, as shown in FIG. 7Qkev,
It is implanted at a dose of about 10 an2 to form a square source/drain region 11 by a self-aligning method using a gate electrode 6 and a silicon nitride film 8.

Thereafter, by removing the silicon nitride film 8 and forming an interlayer insulating film 12, a source/drain electrode 13, and a protective film 14, a highly radiation-resistant H channel M is formed as shown in FIG.
CI type transistor can be completed.

Therefore, the problem with this method is that the silicon nitride film 8 used as a mask when forming the source/drain regions 11 is patterned by anisotropic etching using the photoresist layer 9 as a mask. It can be formed with dimensional accuracy. Therefore, Fig. 1 0
It is possible to reduce the overlay accuracy Al of the source/drain regions 11 and the size Btk of the source/drain regions 11 shown in FIG.
High integration of semiconductor integrated circuit devices can be achieved by miniaturizing the cables.

It goes without saying that the anti-inversion layer 5 can improve the radiation resistance of the MOS transistor.

The above description has been made only regarding the step of forming a hemi-channel MOS transistor, and the process may be combined with other steps as desired. For example, when manufacturing a complementary radiation-resistant MOS type semiconductor integrated circuit device, it is not necessary to use the above-mentioned method to form the source/drain regions of a P-channel MOS type transistor, but the conventional method using a normal mask material. It can be done with

Further, in the embodiment described above, the silicon oxide film 7 is once removed and then reoxidized completely, but this step may be omitted.

〔Effect of the invention〕

As explained above, in the present invention, after forming the entire anti-inversion layer along the inside of the cable isolation region, the nitride film is used to cross over the anti-inversion layer to open the thin element plate. Since the pattern is formed by an anisotropic etching method using a mask provided directly above the nitride film, the dimension N degree of this nitride film can be improved and the sound precision of the source/drain regions formed using this nitride film as a mask can be improved. Therefore, highly integrated semiconductor integrated circuit devices with excellent radiation resistance can be formed.

[Brief explanation of drawings]

Figures 1 (5) to (c) are process cross-sectional views for fully explaining an embodiment of the method of the present invention, Figure 2 is a cross-sectional view of a conventional MOS transistor, and Figure 3 is a cross-sectional view of a conventional improved MOS transistor. A cross-sectional view of a MOS transistor, FIG. 4(5), σ3) is a process cross-sectional view for explaining the entire conventional manufacturing method. 1...Silicon substrate, 2...Field oxide film (element isolation region), 3...Gate oxide film, 4...Photoresist film, 5...Inversion prevention layer, 6...Goo)! very,
8... Silicon nitride film (mask material), 9... Photoresist layer, 11... Source/drain region, 12...
...Interlayer insulating film, 13...Source/drain electrode, 1
4... Retention membrane. zl --- 1, 11・se↓≦ Zter --- Nri J no ink not enough sauce traces and whispers to mogo y extreme build acid i mentions and turns 1 large - positive eyebrow 7 suge 廿

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device having an N-channel MOS type transistor as an element, including the steps of forming an inversion prevention layer along the inside of an element isolation region that defines an element region, and forming a gate electrode in the element region. a step of patterning a nitride film that covers the anti-inversion layer while opening the remaining device region by an anisotropic etching method using a mask provided directly above the nitride film; A method of manufacturing a semiconductor integrated circuit device, comprising the step of performing ion implantation by self-alignment using the gate electrode as a mask to form source/drain regions.