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JPS61228544A - Write protection system - Google Patents

Write protection system

Info

Publication number
JPS61228544A
JPS61228544A JP6951585A JP6951585A JPS61228544A JP S61228544 A JPS61228544 A JP S61228544A JP 6951585 A JP6951585 A JP 6951585A JP 6951585 A JP6951585 A JP 6951585A JP S61228544 A JPS61228544 A JP S61228544A
Authority
JP
Japan
Prior art keywords
write
circuit
read
circuits
lower limit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6951585A
Other languages
Japanese (ja)
Inventor
Tomio Komatsu
小松 富夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6951585A priority Critical patent/JPS61228544A/en
Publication of JPS61228544A publication Critical patent/JPS61228544A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Storage Device Security (AREA)

Abstract

PURPOSE:To detect a write state to a test area and to protect completely the write state by adding a means to a magnetic disk device to inhibit the writing carried out from a host device as necessary. CONSTITUTION:Both upper and lower limit inhibiting areas are stored in the upper and lower limit address memory circuits 11 and 12 of a write protection system respectively. Then the read or write address designated by a host device is stored in a read/write address memory circuit 20. An upper limit comparator 31 compares the contents of both circuits 11 and 20 with each other, while a lower limit comparator 32 compares the contents of both circuits 12 and 20 with each other. An AND circuit 40 secures an AND between outputs of both comparators 31 and 32, and a read/write indicating circuit 50 indicates the distinction between the read and write states. An AND circuit 60 secures an AND between the outputs of both circuits 40 and 50, and a valid/invalid indicating circuit 70 indicates the valid or invalid of each action. Then an AND circuit 80 secures an AND between both circuits 50 and 60. The circuits 40, 60 and 80 detect the write state to a test area for complete protection of the write state.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は磁気ディスク装置に関し、特にその書込保護方
式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic disk device, and particularly to a write protection method thereof.

〔従来の技術〕[Conventional technology]

一般に磁気ディスク装置を試験する場合、記録媒体をも
含む形で行なわれることが多い。この為貴重なデータを
破壊してしまう可能性を持っている。このようなデータ
破壊を未然に防止するために種々の対策が講じられて来
た。従来のこの種のデータ破壊防止手段としては、試験
用の領域を予めリザーブしておき書込はこの領域にしか
行なわない方法が知られている。この方法ではリザーブ
された領域の位置を試験プログラムで意識する必要がち
シ、又試験用領域の位置が異なる装置が追加されると試
験プログラムもこれに追随して修正しなければならず、
この修正を間違えると試験用領域以外の領域を破壊して
しまうという欠点があった。
Generally, when testing a magnetic disk device, the test often includes the recording medium as well. Therefore, there is a possibility that valuable data may be destroyed. Various measures have been taken to prevent such data destruction. As a conventional means for preventing data destruction of this type, a method is known in which a test area is reserved in advance and writing is performed only in this area. With this method, it is necessary to be aware of the location of the reserved area in the test program, and if a device with a different location of the test area is added, the test program must be modified accordingly.
There was a drawback that if this correction was made incorrectly, areas other than the test area would be destroyed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は、磁気ディスク装置自体に試験用領域を
記憶する機能および該領域以外に対して書込が行なわれ
ようとすることを検出し、書込は行なわず報告を行なう
機能を持たせることによりて、よシ確実な書込保護が可
能な磁気ディスク装置の書込保護方式を提供することK
ある。
An object of the present invention is to provide the magnetic disk device itself with a function of storing a test area and a function of detecting an attempt to write to an area other than the area and reporting without writing. To provide a write protection method for a magnetic disk device that is capable of more reliable write protection.
be.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明によれば書込禁止領域を記憶する書込禁止領域記
憶手段と、読出書込アドレスを記述する読出書込アドレ
ス記憶手段と、読出/書込の区別を指示する読出書込指
示手段と、前記書込禁止領域記憶手段の内容と前記読出
書込アドレス記憶手段の内容とを比較する比較手段と、
該比較手段の出力と前記読出書込指示手段の出力とから
不正書込を検出する不正書込検出手段とを有し、磁気デ
ィスク装置に対する不正書込を検出することができる書
込保護方式が得られる。
According to the present invention, a write-protected area storage means for storing a write-protected area, a read/write address storage means for writing a read/write address, and a read/write instruction means for instructing a read/write distinction. , comparison means for comparing the contents of the write-protected area storage means and the contents of the read/write address storage means;
There is provided a write protection method capable of detecting unauthorized writing to a magnetic disk device, comprising an unauthorized writing detection means for detecting unauthorized writing from the output of the comparison means and the output of the read/write instruction means. can get.

〔実施例〕〔Example〕

次に本発明の一実施例を示す図面を参照して詳細に説明
する。
Next, an embodiment of the present invention will be described in detail with reference to the drawings.

本発明の一実施例の書込保護方式は、書込禁止領域の上
限を記憶する上限アドレス記憶回路11と、書込禁止領
域の下限を記憶する下限アドレス記憶回路12と、上位
装置から指定される読出又は書込アドレスを記憶する読
出書込アドレス記憶回路20と、上限アドレス記憶回路
11の内容と読出書込アドレス記憶回路20の内容とを
比較する上限比較回路31と、下限アドレス記憶回路1
2の内容と続出書込アドレス記憶回路20の内容とを比
較する下限比較回路32と、上限比較回路31および下
限比較回路32の出力の論理積をとるAND回路40と
、読出/書込の区別を指示する続出曹込指示回に!r5
0と、ANI)回路40の出力と読出書込指示回路50
の出力との論理積をとるAND回路60と、以上述べて
来た動作の有効/無効を指示する有効無効指示回路70
と、AND回路60の出力と有効無効指示回路70の出
力との論理積をとるAND回路80とを有する。
A write protection system according to an embodiment of the present invention includes an upper limit address storage circuit 11 that stores the upper limit of the write-protected area, a lower limit address storage circuit 12 that stores the lower limit of the write-protected area, and a write protection system that stores the upper limit of the write-protected area. a read/write address storage circuit 20 that stores the read or write address to be read, an upper limit comparison circuit 31 that compares the contents of the upper limit address storage circuit 11 and the contents of the read/write address storage circuit 20, and a lower limit address storage circuit 1.
2 and the content of the subsequent write address storage circuit 20, an AND circuit 40 that takes the logical product of the outputs of the upper limit comparison circuit 31 and the lower limit comparison circuit 32, and the read/write distinction. Instructing Sogome instructions one after another! r5
0, ANI) output of the circuit 40 and the read/write instruction circuit 50
an AND circuit 60 that performs logical product with the output of
and an AND circuit 80 which takes the logical product of the output of the AND circuit 60 and the output of the validity/invalidity indicating circuit 70.

続出書込指示回路50は、書込の場合“1″続出の場合
“0”を出力するものとし、又有効無効指示回路70は
、有効の場合“1”無効の場合“0”を出力するものと
する。更に上限アドレス記憶回路11および下限アドレ
ス記憶−wr12の内容は、本例では夫々予め定められ
た値に固定されているものとするが、上限アドレス記憶
回路11の内容及び下限アドレス記憶回路12の内容は
上位装置から与えることも考えられる。
The successive write instruction circuit 50 outputs "1" for writing and "0" for successive writing, and the validity/invalidity instruction circuit 70 outputs "1" for valid and "0" for invalid. shall be taken as a thing. Furthermore, the contents of the upper limit address storage circuit 11 and the lower limit address storage -wr12 are respectively fixed to predetermined values in this example, but the contents of the upper limit address storage circuit 11 and the contents of the lower limit address storage circuit 12 are It is also possible to give it from a higher-level device.

次にこのような構成の書込保護方式の動作について説明
する。
Next, the operation of the write protection system having such a configuration will be explained.

磁気ディスク装置のある領域(本例では固定域)を書込
禁止にする必要が生じた場合、上位装置からの指示によ
シ、有効無効指示回路70の出力を“1”に設定する。
When it becomes necessary to write to a certain area (fixed area in this example) of the magnetic disk device, the output of the valid/invalid instruction circuit 70 is set to "1" in accordance with an instruction from the host device.

このような状況の下に上位装置から読出又は書込の要求
があると読出又は書込の対象となるディスク装置上のア
ドレスが読出1込アドレス記憶回路20に、又読出書込
の区別を指示するデータが読出書込指示回路50に夫々
設定される。読出書込アドレス記憶回路20に設定され
たアドレスデータは上限比較回路31及び下限比較回路
32に供給される。ここで上限比較回路31は供給され
たアドレスデータと上限アドレス記憶回路11の内容を
比較し、前者が後者より小さいか又は等しい時に“1”
を出力し、これ以外の時には“0”を出力する。父、下
限比較回路32は供給されたアドレスデータと下限アド
レス記憶回路12の内容を比較し、前者が後者より大き
いか又は等しい時に“1”を出力し、これ以外の時には
“0”を出力する。
Under such circumstances, when there is a read or write request from the host device, the address on the disk device to be read or written is sent to the read 1 address storage circuit 20, and the distinction between read and write is indicated. The data to be read and written are respectively set in the read/write instruction circuit 50. Address data set in the read/write address storage circuit 20 is supplied to an upper limit comparison circuit 31 and a lower limit comparison circuit 32. Here, the upper limit comparison circuit 31 compares the supplied address data with the contents of the upper limit address storage circuit 11, and when the former is smaller than or equal to the latter, it becomes "1".
is output, and “0” is output otherwise. The lower limit comparison circuit 32 compares the supplied address data with the contents of the lower limit address storage circuit 12, and outputs "1" when the former is greater than or equal to the latter, and outputs "0" otherwise. .

さて、供給されたアドレスデータが上限アドレス記憶回
路11の内容よシ小さいか又は等しく且つ下限アドレス
記憶回路12の内容よシ大きいか又は等しい場合には上
限比較回路31および下限比較回路32の出力は共に“
1”となる為、AND回路40の出力は“1′′となり
、これ以外の場合は“O”となる。続出書込指示回路5
0の出力が“1″で、即ち書込の場合で、且つAND回
路40の出力が“1″の場合にはAND回路60の出力
は“1″となシ、これ以外の場合は“0”となる。AN
I)回路60の出力が“1″の場合、即ち上位装置から
与えられたアドレスデータが書込禁止領域の上限と下限
の範囲内にあり且つ上位装置から要求された動作が書込
の場合に限シ、AND回路80の出力は“1″となシ、
この出力信号は書込の抑止および上位装置に対する不正
書込報告信号として便用される。
Now, when the supplied address data is smaller than or equal to the contents of the upper limit address storage circuit 11 and larger than or equal to the contents of the lower limit address storage circuit 12, the outputs of the upper limit comparison circuit 31 and the lower limit comparison circuit 32 are both"
1", the output of the AND circuit 40 becomes "1"; otherwise, it becomes "O". Successive write instruction circuit 5
If the output of 0 is "1", that is, in the case of writing, and the output of the AND circuit 40 is "1", the output of the AND circuit 60 is "1"; otherwise, it is "0". ” becomes. AN
I) When the output of the circuit 60 is "1", that is, when the address data given from the host device is within the upper and lower limits of the write-protected area and the operation requested by the host device is writing. In this case, the output of the AND circuit 80 is “1”.
This output signal is useful for inhibiting writing and as an unauthorized writing report signal to the host device.

磁気ディスク装置に対して書込禁止を行なう必要のない
場合は、上位装置からの指示によプ有効無効指示回路7
0の出力を“O”に設定する。この場合AND回路60
の出力の如何に関らずAND回路80の出力は常に0”
となる為、書込の抑止および上位装置に対する不正書込
報告は行なわれない。
If it is not necessary to write to the magnetic disk device, the write enable/disable instruction circuit 7
Set the output of 0 to “O”. In this case, the AND circuit 60
The output of the AND circuit 80 is always 0 regardless of the output of
Therefore, writing is not inhibited and unauthorized writing is not reported to the higher-level device.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、磁気ディスク装置に、
必要に応じて上位装置から書込を禁止する手段を追加す
ることによシ、上位装置で実行される磁気ディスク装置
の試験プログラム等のバグその他によるデータ破壌を未
然に防止できるという効果がある。
As explained above, the present invention provides a magnetic disk device with
By adding a means to prohibit writing from the host device as necessary, it is possible to prevent data corruption due to bugs or other causes in the magnetic disk drive test program executed on the host device. .

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の一実施例を示すブロック図である。 11・・・・・・上限アドレス記憶回路、12・・・・
・・下限アドレス記憶回路、20・・・・・・読出書込
アドレス記憶回路、31・・・・・・上限比較回路、3
2・・・・・・下限比較回路、40・・・・・・AND
回路、50・・・・・・読出書込指示回路、60・・・
・・・AND回路、70・・・・・・有効無効指示回路
、80・・・・・・AND回路。 代理人 弁理士  内 原   n 白
The drawing is a block diagram showing one embodiment of the present invention. 11... Upper limit address storage circuit, 12...
...Lower limit address storage circuit, 20...Read/write address storage circuit, 31...Upper limit comparison circuit, 3
2...lower limit comparison circuit, 40...AND
Circuit, 50... Read/write instruction circuit, 60...
. . . AND circuit, 70 . . . Validity/invalidity instruction circuit, 80 . . . AND circuit. Agent Patent Attorney Uchihara n Shiro

Claims (1)

【特許請求の範囲】[Claims] 書込禁止領域を記憶する書込禁止領域記憶手段と、読出
書込アドレスを記憶する読出書込アドレス記憶手段と、
読出/書込の区別を指示する読出書込指示手段と、前記
書込禁止領域記憶手段の内容と前記読出書込アドレス記
憶手段の内容とを比較する比較手段と、前記比較手段の
出力と前記読出書込指示手段の出力とから不正書込を検
出する不正書込検出手段とを具備することを特徴とする
磁気ディスク装置の書込保護方式。
a write-protected area storage means for storing a write-protected area; a read/write address storage means for storing a read/write address;
read/write instruction means for instructing read/write distinction; comparison means for comparing the contents of the write-protected area storage means with the contents of the read/write address storage means; 1. A write protection system for a magnetic disk device, comprising unauthorized write detection means for detecting unauthorized writing from an output of a read/write instruction means.
JP6951585A 1985-04-01 1985-04-01 Write protection system Pending JPS61228544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6951585A JPS61228544A (en) 1985-04-01 1985-04-01 Write protection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6951585A JPS61228544A (en) 1985-04-01 1985-04-01 Write protection system

Publications (1)

Publication Number Publication Date
JPS61228544A true JPS61228544A (en) 1986-10-11

Family

ID=13404942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6951585A Pending JPS61228544A (en) 1985-04-01 1985-04-01 Write protection system

Country Status (1)

Country Link
JP (1) JPS61228544A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02201562A (en) * 1989-01-30 1990-08-09 Nec Corp Magnetic disk controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02201562A (en) * 1989-01-30 1990-08-09 Nec Corp Magnetic disk controller

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