JPS6122669A - Thin film transistor and its manufacturing method - Google Patents
Thin film transistor and its manufacturing methodInfo
- Publication number
- JPS6122669A JPS6122669A JP59143622A JP14362284A JPS6122669A JP S6122669 A JPS6122669 A JP S6122669A JP 59143622 A JP59143622 A JP 59143622A JP 14362284 A JP14362284 A JP 14362284A JP S6122669 A JPS6122669 A JP S6122669A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon film
- film
- gate electrode
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6731—Top-gate only TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6745—Polycrystalline or microcrystalline silicon
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は２例えば絶縁性基板上に多結晶シリコン膜を
半導体膜として形成する薄膜トランジスタ及びその製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thin film transistor in which a polycrystalline silicon film is formed as a semiconductor film on, for example, an insulating substrate, and a manufacturing method thereof.
従来、この種の装置として第１図に示すものがあったっ
図において、（１）は絶縁性基板あるいは表面が絶縁膜
で１例えばガラス基板、（２）は半導体膜となる多結晶
シリコン膜、（３）は多結晶シリコン嘆（２）上に形成
されたゲート絶縁膜で１例えば酸化シリコン膜、（４）
はゲート絶縁膜（３）上に形成されたゲート電極で１例
えば金属、（５）は多結晶シリコン喚（２）に、又は多
結晶シリコン膜（２）に接続して形成されたソースある
いはドレイン、（６）はそれぞれの層間を絶縁する層間
絶縁膜、（７）は各電極のそれぞれに接続されたアルミ
ニウムあるいはアルミニウム合金配線である。また、第
２図は層間絶縁膜（６）を形成する工程よシ以前の薄膜
トランジスタの断面を示すものである。Conventionally, there has been a device of this type as shown in FIG. 1. In the figure, (1) is an insulating substrate or a glass substrate whose surface is an insulating film, (2) is a polycrystalline silicon film that is a semiconductor film, (3) is a gate insulating film formed on polycrystalline silicon (2), for example, a silicon oxide film, (4)
1 is a gate electrode formed on a gate insulating film (3), for example, a metal, and (5) is a source or drain formed on a polycrystalline silicon film (2) or connected to a polycrystalline silicon film (2). , (6) is an interlayer insulating film that insulates the respective layers, and (7) is an aluminum or aluminum alloy wiring connected to each electrode. Further, FIG. 2 shows a cross section of the thin film transistor before the step of forming the interlayer insulating film (6).
このような従来の多結晶シリコン膜（２）を半導体膜と
して形成した薄膜トランジスタは、多結晶シリコン膜（
２）のゲート電極（４）に対向する対向部１例えばチャ
ネル部に、結晶粒界や結晶欠陥などのトラップ準位゛が
存在するため、キャリアがチャネル領域を伝導しに＜＜
、シきい値電圧（ＶＴＨ）がきわめて高かった。このチ
ャネル部にドープする不純物をパラメータとしてしきい
値電圧（Ｖ−）を制御すると、ドープ量が少ない場合、
トランジスタのＯＮ電流値が小さくなり、このＯＮ電流
値と、ゲート・ソース間電圧（Ｖｏ８）：ＯＶ での
ドレイン・ソース間電流（工。Ｓ）であるＯＦＦ時のリ
ーク電流値との比、つまりＱ Ｎ１０ Ｆ Ｆ抵抗比が
小さくなる。A thin film transistor formed using such a conventional polycrystalline silicon film (2) as a semiconductor film is
Since trap levels such as crystal grain boundaries and crystal defects exist in the opposing part 1 facing the gate electrode (4) of 2), for example in the channel part, carriers cannot be conducted through the channel region.
, the threshold voltage (VTH) was extremely high. If the threshold voltage (V-) is controlled using the impurity doped into the channel as a parameter, if the amount of doping is small,
The ON current value of the transistor becomes smaller, and the ratio of this ON current value to the leakage current value when OFF, which is the drain-source current (S) at the gate-source voltage (Vo8): OV, is Q N10 FF F resistance ratio becomes small.
また、ドープ量が多い場合、ＯＮ電流値の上昇に比べて
、 ＯＦＦ時のリーク電流値の上昇が著しいため。Also, when the amount of doping is large, the increase in leakage current value when OFF is more significant than the increase in ON current value.
やけｊＱ ０Ｎ１０ＦＦ抵抗比は小さく、かつｆｌＦＦ
時のリーク電流値が高くなるので問題であった。また。YakejQ 0N10FF resistance ratio is small and flFF
This was a problem because the leakage current value would be high when Also.
パラメータと１．て、トランジスタのゲート電極（４）
の瞭厚及びゲート長を加えてしきい値電圧（ｖＴＨ）を
制御するようにしても、上記と同様にしきい値電圧（ｖ
ＴＨ）がきわめて高いだめ、その制御には限界があった
。例えば、ゲート長が１６メｍの場合。Parameters and 1. The gate electrode of the transistor (4)
Even if the threshold voltage (vTH) is controlled by adding the thickness and gate length of the gate, the threshold voltage (vTH)
Since the TH) was extremely high, there were limits to its control. For example, if the gate length is 16 mem.
しきい値電圧（ｖＴＨ）をＩＯＶ程度まで下げるのが限
界であった。The limit was to lower the threshold voltage (vTH) to around IOV.
従来の薄膜トランジスタは以上のように構成されている
ので、多結晶シリコン膜のゲート電極対向部に存在する
トラップ準位のため、しきい値電圧（ＶＴＨ）がきわめ
て高く、シかも０７７時のリーク電流が大きいため、
０Ｎ１０ＦＦ抵抗比が小さく。Since conventional thin film transistors are configured as described above, the threshold voltage (VTH) is extremely high due to the trap level existing in the portion of the polycrystalline silicon film opposite to the gate electrode, and the leakage current at 077 is extremely high. is large, so
0N10FF resistance ratio is small.
しきい値電圧（ｖＴＨ）を低く制御するのは困難であっ
た。It has been difficult to control the threshold voltage (vTH) low.
本発明は上記のような従来のものの欠点を除去するため
になされたもので、絶縁性基板上あるいは絶縁膜上に形
成された多結晶シリコン膜、この多結晶シリコン膜上に
形成されたゲート絶縁膜及びゲート電極、及び多結晶シ
リコン膜に、又は多結晶シリコン膜に接続して形成され
たソースとドレインを有する薄膜トランジスタにおいて
、多結晶シリコン膜のゲート電極対向部に水素イオンを
含有させることによシ、シきい値電圧（ｖＴＨ）が低く
、かつ高いＯＮ電流を得て、０Ｎ１０′Ｐ１ｔ′抵抗比
の大きな薄膜トランジスタを提供することを目的として
いる。The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above. In a thin film transistor having a film, a gate electrode, and a source and drain formed in or connected to a polycrystalline silicon film, hydrogen ions can be contained in the portion of the polycrystalline silicon film facing the gate electrode. Another object of the present invention is to provide a thin film transistor with a low threshold voltage (vTH), a high ON current, and a high resistance ratio of 0N10'P1t'.
また１本発明の別の発明は、絶縁性基板上あるいは絶縁
膜上に多結晶シリコン膜を形成する工程。Another aspect of the present invention is a step of forming a polycrystalline silicon film on an insulating substrate or an insulating film.
多結晶シリコン膜上にゲート絶縁膜とゲート電極を形成
する工程、多結晶シリコン膜に、又は多結晶シリコン膜
に接続してソースとドレインを形成する工程、及び多結
晶シリコン膜のゲート電極対向部に水素イオンを注入又
は拡散する工程を施すことにより、しきい値電圧（ＶＴ
Ｈ）が低く、かつ高いＯＮ電流を得て、 ０Ｎ１０ＦＦ
抵抗比の大きな薄膜トランジスタの製造方法を提供する
ことを目的としている。A step of forming a gate insulating film and a gate electrode on a polycrystalline silicon film, a step of forming a source and a drain on or connected to the polycrystalline silicon film, and a portion of the polycrystalline silicon film facing the gate electrode. The threshold voltage (VT
H) is low and high ON current is obtained, 0N10FF
It is an object of the present invention to provide a method for manufacturing a thin film transistor with a large resistance ratio.
以下、この発明の一実施例を図について説明する。第３
図において、−″（８１はゲート電極（４）対向部にお
いて水素イオンを含有する多結晶シリコン膜であり１例
えば一価に荷電した水素イオンを１×１０ ／ａｍ
からｌＸｌ０／ａｍ の範囲で含有されている。この
一実施例による薄膜トランジスタは。An embodiment of the present invention will be described below with reference to the drawings. Third
In the figure, -'' (81 is a polycrystalline silicon film containing hydrogen ions in the portion facing the gate electrode (4).
The content ranges from 1X10/am2 to 1X10/am2. The thin film transistor according to this embodiment is as follows.
第４図にその製造工程途中の断面を示すように。Figure 4 shows a cross section during the manufacturing process.
絶縁性基板（１）上に多結晶シリコン膜（２）を形成し
、多結晶シリコン蓉（２）上にゲート絶縁膜（３）とゲ
ート′ｒＴｉｆｆｉ （４）を形成し１次に多結晶シリ
コン膜（２）に又はこれに接続するようにソースとドレ
イン（５）を形成し、さらにそれぞれの電極上に絶縁膜
（６）を形成する。A polycrystalline silicon film (2) is formed on an insulating substrate (1), a gate insulating film (3) and a gate (4) are formed on the polycrystalline silicon film (2), and then the polycrystalline silicon film (4) is formed on the polycrystalline silicon film (2). A source and a drain (5) are formed on or connected to the film (2), and an insulating film (6) is further formed on each electrode.
この後１図に示すように多結晶シリコンＩｌｌ！！ （
２）のゲー、ｈ 電極（４）対向部にイオンが到達する
ように所定のエネルギ例えば１８０ｋｅＶで１例えば一
価に荷電した水素イオンをイオン注入によって、多結晶
シリコン膜（２）に含有させる。After this, as shown in Figure 1, polycrystalline silicon Ill! ! (
2) Ga, h Hydrogen ions charged to a single charge, for example, at a predetermined energy of 180 keV are ion-implanted into the polycrystalline silicon film (2) so that the ions reach the portion facing the electrode (4).
水素イオンを含有する多結晶シリコン膜（８）では。In the polycrystalline silicon film (8) containing hydrogen ions.
ゲー）ｔｆｌｉ（４）対向部に存在するトラップ準位が
ターミネイトされ、しきい値電圧（Ｖ、、、）が著しく
低下する。このため、薄膜トランジスタのＯＮ電流が上
昇する。一方、イオン注入によりダングリングボンドが
減少するので、 ＯＦＦ時のリーク電流も減少する。従
って、この発明の一実施例における薄膜トランジスタの
０Ｎ１０ＦＦ抵抗比は向上する。tfli(4) The trap level existing in the opposing portion is terminated, and the threshold voltage (V, , ) is significantly lowered. Therefore, the ON current of the thin film transistor increases. On the other hand, since dangling bonds are reduced by ion implantation, leakage current during OFF state is also reduced. Therefore, the 0N10FF resistance ratio of the thin film transistor in one embodiment of the present invention is improved.
このため、液晶のスイッチング素子などに十分灯芯でき
る特性の薄膜トランジスタを形成することができる。Therefore, it is possible to form a thin film transistor having characteristics sufficient to be used as a wick for liquid crystal switching elements and the like.
ここで、水素イオンの含有量は、多結晶シリコン膜（８
）のゲート電極（４）対向部において、ｌＸｌ０”／ａ
ｍ からｌ Ｘ １０ ７ｃｍの範囲とし、ｌＸｌ０
／Ｃ［ｎ 以下だと、効果が少なく、ｌ Ｘ １０
／ａｍよシも多いと、効果が飽和すると共に不純物によ
る悪影響が出るので好ましくない。Here, the hydrogen ion content is the polycrystalline silicon film (8
) in the opposite part of the gate electrode (4), lXl0”/a
The range is from m to l x 10 7cm, and lXl0
/C[n, the effect is small, l x 10
If /am is too large, the effect will be saturated and impurities will have an adverse effect, which is not preferable.
なお、上記実施例では水素イオン注入によって水素イオ
ンを多結晶シリコン暎（２）のゲート電＠（４）対向部
に注入しているが、水素プラズマ処理でＨ９Ｈ２を注入
してもよく、又Ｈ，Ｈ２の雰囲気中で熱処理して、Ｈ，
Ｈ２を拡散させてもよい。In the above embodiment, hydrogen ions are implanted into the portion of the polycrystalline silicon layer (2) facing the gate electrode (4), but H9H2 may also be implanted by hydrogen plasma treatment. , H2, and heat-treated in an atmosphere of H,
H2 may be diffused.
また、この水素イオンを注入する工程は、注入イオンの
離脱を避けるため後工程に約４５０℃以上の高温熱処理
を含まない工程で行なえばよく、ゲート絶縁膜（３）及
びゲート電極（４）を形成する工程より後の工程におい
て、４５０℃以上の高温熱処理を含まなければ、絶縁性
基板Ｑ）上に多結晶シリコン膜（２）を形成しｆｃ後、
水素イオンを注入してもよい。In addition, this step of implanting hydrogen ions may be performed in a post-process that does not include high-temperature heat treatment of approximately 450°C or higher to avoid detachment of the implanted ions, and the gate insulating film (3) and gate electrode (4) are If the process after the forming process does not include high-temperature heat treatment at 450°C or higher, the polycrystalline silicon film (2) is formed on the insulating substrate Q), and after fc,
Hydrogen ions may also be implanted.
以上のように９本発明によれば、絶縁性基板上あるいは
絶縁膜上に形成された多結晶シリコン膜。As described above, according to the present invention, a polycrystalline silicon film is formed on an insulating substrate or an insulating film.
この多結晶シリコン膜上に形成されたゲート絶縁膜及び
ゲート電極、及び多結晶シリコン模に、又は多結晶シリ
コン嘆に接続して形成されたソースとドレインを有する
薄膜トランジスタにおいて。In a thin film transistor having a gate insulating film and a gate electrode formed on the polycrystalline silicon film, and a source and a drain formed on the polycrystalline silicon pattern or connected to the polycrystalline silicon layer.
多結晶シリコン膜のゲート電極対向部に水素イオンを含
有させることにより、水素イオンによって多結晶シリコ
ン嘆のゲート電極対向部に存在するトラップ準位をター
ミネイトして、しきい値電圧（Ｖ、Ｈ）を下げ、 ０Ｎ
１０ＦＦ抵抗比を向上できる薄膜トランジスタが得られ
る効果がある。By containing hydrogen ions in the polycrystalline silicon film in the area facing the gate electrode, the hydrogen ions terminate the trap level existing in the polycrystalline silicon film in the area facing the gate electrode, increasing the threshold voltage (V, H). lower, 0N
This has the effect of providing a thin film transistor that can improve the 10FF resistance ratio.
また、本発明の別の発明によれば、絶縁性基板上あるい
は絶縁膜上に多結晶シリコン膜を形成する工程、多結晶
シリコン膜上にゲート絶縁膜とゲート電極を形成する工
程、多結晶シリコン膜に。According to another invention of the present invention, a step of forming a polycrystalline silicon film on an insulating substrate or an insulating film, a step of forming a gate insulating film and a gate electrode on the polycrystalline silicon film, a step of forming a gate insulating film and a gate electrode on the polycrystalline silicon film, to the membrane.
又は多結晶シリコン膜に接続してソースとドレインを形
成する工程、及び多結晶シリコン嘆のゲート電極対向部
に水素イオンを注入又は拡散する工程を施すことによシ
、水素イオンによって多結晶シリコン嘆のゲート電極対
向部に存在するトラップ準位をターミネイトして、しき
い値電圧（■ＴＨ）を下げ、 ０Ｎ１０ＦＦ抵抗比を向
上できる薄膜トランジスタの製造方法を提供できる効果
がある。Alternatively, by performing a step of connecting to a polycrystalline silicon film to form a source and a drain, and a step of implanting or diffusing hydrogen ions into the portion of the polycrystalline silicon film opposite to the gate electrode, the polycrystalline silicon film is bonded to the polycrystalline silicon film by hydrogen ions. This has the effect of providing a method for manufacturing a thin film transistor that can lower the threshold voltage (■TH) and improve the 0N10FF resistance ratio by terminating the trap level existing in the portion facing the gate electrode.
第１図は従来の薄膜トランジスタを示す断面図、第２図
は、従来の薄膜トランジスタを製造する際■ソース及び
ドレイン形成後における薄膜トランジスタを示す断面図
、第３図はこの発明の一実施例による薄膜トランジスタ
を示す断面図、第４図はこの発明の一実施例による水素
イオンを注入する工程における薄膜トランジスタを示す
断面図である。
（１）・・・絶縁性基板あるいは絶縁膜、（２）・・・
多結晶シリコン膜、（３）・・・ゲート絶縁膜、（４）
・・・ゲート電極。
（５）・・・ソースあるいはドレイン、（８）・・・水
素イオンを含有する多結晶シリコン換。
なお１図中同一行号は同一、又は相当部分を示す。FIG. 1 is a cross-sectional view showing a conventional thin film transistor, FIG. 2 is a cross-sectional view showing a thin film transistor after forming a source and drain when manufacturing a conventional thin film transistor, and FIG. 3 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a thin film transistor in a step of implanting hydrogen ions according to an embodiment of the present invention. (1)...Insulating substrate or insulating film, (2)...
Polycrystalline silicon film, (3)...gate insulating film, (4)
...Gate electrode. (5)...source or drain, (8)...polycrystalline silicon containing hydrogen ions. Note that the same line numbers in Figure 1 indicate the same or equivalent parts.
Claims (4)
晶シリコン膜、この多結晶シリコン膜上に形成されたゲ
ート絶縁膜及びゲート電極、及び上記多結晶シリコン膜
に、又は上記多結晶シリコン膜に接続して形成されたソ
ースとドレインを有する薄膜トランジスタにおいて、上
記多結晶シリコン膜の上記ゲート電極対向部に水素イオ
ンを含有させたことを特徴とする薄膜トランジスタ。(1) A polycrystalline silicon film formed on an insulating substrate or an insulating film, a gate insulating film and a gate electrode formed on the polycrystalline silicon film, and a polycrystalline silicon film formed on the polycrystalline silicon film or the polycrystalline silicon film. 1. A thin film transistor having a source and a drain formed in connection with a film, characterized in that a portion of the polycrystalline silicon film facing the gate electrode contains hydrogen ions.
１＾４／ｃｍ＾２から１×１０＾１＾５／ｃｍ＾２の範
囲であることを特徴とする特許請求の範囲第１項記載の
薄膜トランジスタ。(2) The content is 1 x 10^ of monovalently charged hydrogen ions.
2. The thin film transistor according to claim 1, wherein the thickness is in the range of 1^4/cm^2 to 1x10^1^5/cm^2.
膜を形成する工程、上記多結晶シリコン膜上にゲート絶
縁膜とゲート電極を形成する工程、上記多結晶シリコン
膜に又は上記多結晶シリコン膜に接続してソースとドレ
インを形成する工程、及び上記多結晶シリコン膜の上記
ゲート電極対向部に水素イオンを注入又は拡散する工程
を施す薄膜トランジスタの製造方法。(3) A step of forming a polycrystalline silicon film on an insulating substrate or an insulating film, a step of forming a gate insulating film and a gate electrode on the polycrystalline silicon film, and a step of forming a gate insulating film and a gate electrode on the polycrystalline silicon film or the polycrystalline silicon film. A method for manufacturing a thin film transistor, comprising: forming a source and drain by connecting the polycrystalline silicon film to the polycrystalline silicon film; and implanting or diffusing hydrogen ions into a portion of the polycrystalline silicon film facing the gate electrode.
の注入量を多結晶シリコン膜のゲート電極対向部で１×
１０＾１＾４／ｃｍ＾２から１×１０＾１＾５／ｃｍ＾
２の範囲とする特許請求の範囲第３項記載の薄膜トラン
ジスタの製造方法。(4) In the implantation of hydrogen ions, the amount of monovalently charged hydrogen ions is 1×
10^1^4/cm^2 to 1x10^1^5/cm^
2. A method for manufacturing a thin film transistor according to claim 3, which is defined in claim 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59143622A JPS6122669A (en) | 1984-07-09 | 1984-07-09 | Thin film transistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59143622A JPS6122669A (en) | 1984-07-09 | 1984-07-09 | Thin film transistor and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6122669A true JPS6122669A (en) | 1986-01-31 |
Family
ID=15343030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59143622A Pending JPS6122669A (en) | 1984-07-09 | 1984-07-09 | Thin film transistor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6122669A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253972A (en) * | 1988-04-01 | 1989-10-11 | Matsushita Electric Ind Co Ltd | Heterojunction device and its manufacturing method |
| JPH0728092A (en) * | 1993-07-08 | 1995-01-31 | Nec Corp | Method for manufacturing liquid crystal display device with built-in drive circuit |
| US5504020A (en) * | 1993-09-22 | 1996-04-02 | Sharp Kabushiki Kaisha | Method for fabricating thin film transistor |
| US5508555A (en) * | 1989-07-12 | 1996-04-16 | U.S. Philips Corporation | Thin film field effect transistor having a doped sub-channel region |
-
1984
- 1984-07-09 JP JP59143622A patent/JPS6122669A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253972A (en) * | 1988-04-01 | 1989-10-11 | Matsushita Electric Ind Co Ltd | Heterojunction device and its manufacturing method |
| US5508555A (en) * | 1989-07-12 | 1996-04-16 | U.S. Philips Corporation | Thin film field effect transistor having a doped sub-channel region |
| JPH0728092A (en) * | 1993-07-08 | 1995-01-31 | Nec Corp | Method for manufacturing liquid crystal display device with built-in drive circuit |
| US5504020A (en) * | 1993-09-22 | 1996-04-02 | Sharp Kabushiki Kaisha | Method for fabricating thin film transistor |
| EP0645803A3 (en) * | 1993-09-22 | 1997-03-05 | Sharp Kk | Method of manufacturing a thin film transistor. |
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