JPS61220419A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61220419A JPS61220419A JP6084785A JP6084785A JPS61220419A JP S61220419 A JPS61220419 A JP S61220419A JP 6084785 A JP6084785 A JP 6084785A JP 6084785 A JP6084785 A JP 6084785A JP S61220419 A JPS61220419 A JP S61220419A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- polycrystalline silicon
- layer
- epitaxial
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概 要〕
シリコン基板及び二酸化シリコン膜上にそれぞれエピタ
キシャルシリコン及び多結晶シリコンを同時に成長させ
るため、予め二酸化シリコン膜上にシリコンイオン注入
した後に行なう。[Detailed Description of the Invention] [Summary] In order to simultaneously grow epitaxial silicon and polycrystalline silicon on a silicon substrate and a silicon dioxide film, respectively, silicon ions are implanted into the silicon dioxide film in advance.
本発明は半導体装置の製造方法に係り、特にバイポーラ
トランジスタの引出電極のベース領域の寄生容量を小に
するために用いるエピタキシャルシリコン−多結晶シリ
コンの同時成長法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for simultaneously growing epitaxial silicon and polycrystalline silicon used to reduce parasitic capacitance in a base region of a lead electrode of a bipolar transistor.
従来、高耐圧な相補型ＩＧを製造するためのエピタキシ
ャルシリコン−多結晶シリコンを同時に形成する方法が
用いられている。すなわちシリコン基板上に二酸化シリ
コン等をパターニング形成し、これをエピタキシャル成
長装置内に入れ、ＳｉＨ４、ＳｉＨ２Ｃ１２等のガスを
８００〜１０００℃程度の雰囲気温度で流し、シリコン
基板上にエピタキシャルシリコンそして二酸化シリコン
上に多結晶シリコンを同時に成長させる。Conventionally, a method of simultaneously forming epitaxial silicon and polycrystalline silicon has been used to manufacture a complementary IG with high breakdown voltage. That is, silicon dioxide or the like is patterned on a silicon substrate, placed in an epitaxial growth apparatus, gas such as SiH4, SiH2C12, etc. is flowed at an ambient temperature of about 800 to 1000°C, and epitaxial silicon is formed on the silicon substrate and then silicon dioxide is formed on the silicon substrate. Simultaneously grow polycrystalline silicon.
上記エピタキシャルシリコン−多結晶シリコンの同時成
長では多結晶シリコンの表面の凹凸状態及びエピタキシ
ャルシリコンの結晶性が重要である。In the simultaneous growth of epitaxial silicon and polycrystalline silicon, the unevenness of the surface of polycrystalline silicon and the crystallinity of epitaxial silicon are important.
しかしながら例えば１０００℃程度の温度でエピタキシ
ャルシリコン−多結晶シリコンの同時成長を行なうと、
エピタキシャルシリコンの結晶性は良好であるが多結晶
シリコンの表面はダレインが太き（なるため約５０００
人の凹凸が生じ、その後の工程に悪影響を及ぼす、また
例えば８００℃程度の温度で上記同時成長を行なうと多
結晶シリコンの表面は約１０００Å以下の凹凸と良好で
あるがエピタキシャルシリコンの結晶性が不良となり電
気的特性を低下させる。However, if epitaxial silicon and polycrystalline silicon are grown simultaneously at a temperature of about 1000°C, for example,
Epitaxial silicon has good crystallinity, but the surface of polycrystalline silicon has thick daleins (approximately 5,000
This causes unevenness, which has a negative effect on subsequent processes.For example, if the above simultaneous growth is performed at a temperature of about 800°C, the surface of the polycrystalline silicon is good, with unevenness of about 1000 Å or less, but the crystallinity of epitaxial silicon deteriorates. It becomes defective and deteriorates electrical characteristics.
Ｃ問題点を解決するための手段〕
上記問題点は本発明によれば、シリコン基板上にパター
ニングされた絶縁層を形成し、該絶縁層にシリコンイオ
ンを注入し、次に該全表面にシリコンを成長させること
によって該絶縁層上に多結晶シリコンそして該シリコン
基板上にエピタキシャルシリコンを同時に成長させる工
程を含むことを特徴とする半導体装置の製造方法によっ
て解決される。Means for Solving Problem C] According to the present invention, the above problem can be solved by forming a patterned insulating layer on a silicon substrate, implanting silicon ions into the insulating layer, and then implanting silicon onto the entire surface. The present invention is solved by a method for manufacturing a semiconductor device, which includes a step of simultaneously growing polycrystalline silicon on the insulating layer and epitaxial silicon on the silicon substrate by growing a polycrystalline silicon layer.
すなわち本発明によれば絶縁層にシリコンがイオン注入
されるので、該絶縁層にシリコンの種が形成され、その
種を元にして表面状態が良好な多結晶シリコンが成長す
る。That is, according to the present invention, silicon ions are implanted into the insulating layer, so silicon seeds are formed in the insulating layer, and polycrystalline silicon with a good surface condition grows from the seeds.
以下本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１Ａ図及び第１Ｂ図は本発明の一実施例を説明するた
めの工程断面図である。FIGS. 1A and 1B are process sectional views for explaining one embodiment of the present invention.
第１Ａ図に示すように、シリコン基板１上に約３０００
人の厚さを有する５ｔｏ２層２を形成しパターニングし
、一部のシリコン基板１の表面１ａを露出させる。次に
５Ｌ０２層２上方から注入条件５、 ＯｘｌＯ／ｄ、
３５ ＫｅＶでシリコンイオン３を５ｔｏ２層に注入し
た。このようにして得られた基板を周知のエピタキシャ
ル成長装置のベルジャ内に載置し、該ベルジャ内圧力を
約１トールの減圧下にする０次に約１０００℃に基板を
加熱しながら水素、シランガスをベルジャ内に供給し、
第１Ｂ図に示すように約５０００人の多結晶シリコンを
５ｉｏｚ層２上及びシリコン基板表面ｌａ上に形成する
。As shown in FIG. 1A, about 300
A 5to2 layer 2 having a thickness of about 100 mm is formed and patterned to expose a part of the surface 1a of the silicon substrate 1. Next, implantation conditions 5 from above the 5L02 layer 2, OxlO/d,
Silicon ions 3 were implanted into the 5to2 layer at 35 KeV. The substrate thus obtained is placed in a bell jar of a well-known epitaxial growth apparatus, and the pressure inside the bell jar is reduced to about 1 Torr. Next, hydrogen and silane gas are introduced while heating the substrate to about 1000°C. Supplied into the bell jar,
As shown in FIG. 1B, about 5,000 layers of polycrystalline silicon are formed on the 5ioz layer 2 and on the silicon substrate surface la.
この際シリコン基板表面ｌａ上ではシリコン基板を種結
晶として多結晶シリコンが単結晶のエピタキシャルシリ
コンとして成長する。At this time, polycrystalline silicon grows as single-crystal epitaxial silicon on the silicon substrate surface la using the silicon substrate as a seed crystal.
５ｔｏｚ層２上に形成された多結晶シリコンは５ｉ０２
層に注入されたシリコンを種として表面の凹凸の少ない
状態で形成せしめられる。The polycrystalline silicon formed on the 5toz layer 2 is 5i02
The silicon implanted into the layer is used as a seed to form the layer with less irregularities on the surface.
以上説明したように本発明によれば、基板上の絶縁層に
シリコンをイオン注入しているのでそのシリコンを種と
して平坦な多結晶シリコン層が形成され、しかも１００
０℃で形成されているのでエピタキシャルシリコン層も
結晶性の良いものを得ることができる。従ってこの方法
を利用すればパイボーラトラランジスタ等の電極引出し
部のベース領域をわずかなスペースで製造できる。As explained above, according to the present invention, since silicon ions are implanted into the insulating layer on the substrate, a flat polycrystalline silicon layer is formed using the silicon as a seed.
Since it is formed at 0° C., an epitaxial silicon layer with good crystallinity can be obtained. Therefore, by using this method, the base region of the electrode lead-out portion of a piboratransistor or the like can be manufactured in a small space.
第１Ａ図及び第１Ｂ図は本発明の一実施例を説明するた
めの工程断面図である。
１・・・シリコン基板、 ２・・・５ｉ０２層、３・
・・Ｓｉイオン、 ４・・・多結晶シリコン、
５・・・多結晶シリコン表面、
６・・・エピタキシャルシリコン。FIGS. 1A and 1B are process sectional views for explaining one embodiment of the present invention. 1... Silicon substrate, 2... 5i02 layer, 3...
...Si ion, 4...polycrystalline silicon,
5... Polycrystalline silicon surface, 6... Epitaxial silicon.
Claims (1)
し、該絶縁層にシリコンイオンを注入し、次に該全表面
にシリコンを成長させることによって該絶縁層上に多結
晶シリコンそして該シリコン基板上にエピタキシャルシ
リコンを同時に成長させる工程を含むことを特徴とする
半導体装置の製造方法。1. Form a patterned insulating layer on a silicon substrate, implant silicon ions into the insulating layer, and then grow silicon on the entire surface to form polycrystalline silicon on the insulating layer and on the silicon substrate. 1. A method of manufacturing a semiconductor device, comprising the step of simultaneously growing epitaxial silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6084785A JPS61220419A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6084785A JPS61220419A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61220419A true JPS61220419A (en) | 1986-09-30 |
Family
ID=13154170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6084785A Pending JPS61220419A (en) | 1985-03-27 | 1985-03-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61220419A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5213991A (en) * | 1986-02-07 | 1993-05-25 | Nippon Telegraph And Telephone Corporation | Method of manufacturing semiconductor device |
| US5250454A (en) * | 1992-12-10 | 1993-10-05 | Allied Signal Inc. | Method for forming thickened source/drain contact regions for field effect transistors |
-
1985
- 1985-03-27 JP JP6084785A patent/JPS61220419A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5213991A (en) * | 1986-02-07 | 1993-05-25 | Nippon Telegraph And Telephone Corporation | Method of manufacturing semiconductor device |
| US5250454A (en) * | 1992-12-10 | 1993-10-05 | Allied Signal Inc. | Method for forming thickened source/drain contact regions for field effect transistors |
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