JPS61219239A - Clock selection controlling device for network terminating device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] - Overview - Field of industrial application - Prior art - Problems to be solved by the invention - Means for solving the problems - Actions - Examples of devices Operation of component devices/effects of the invention [Summary] Regarding a clock selection control device for a network termination device, the present invention identifies the connection form between the network termination device and the terminal device, selects an appropriate retiming clock accordingly, and When an identification error is likely to occur, the previous identification result is retained to improve the reliability of the selection.

[Industrial application field]

The present invention relates to a clock selection control device for a network termination device.
The clock selection control device of the present invention is used, for example, in Integrated Service Digital W4 (ISDN), and is configured using a digital phase locked loop (DPLL) or the like depending on the connection form between the subscriber premises network termination device and the subscriber terminal. A recovered clock and a fixed phase clock are automatically selected as retiming clocks at network terminations.

[Prior Art] In integrated service digital networks, the connection forms between the subscriber premises network terminal (NT) and the subscriber terminals include single bus, extemporized bus, and point bus.
There are three forms of two points.

FIG. 2 shows a single bus configuration, FIG. 3 shows an expanded bus configuration, and FIG. 4 shows a point-to-point configuration.

According to the CCITT proposal, the network terminal equipment NT and each terminal NE
(1) ~ N E (The maximum distance with 11 is 100 to 150 m or less in the single bus configuration shown in Figure 2, 500+ m or less in the expanded bus configuration, and point-to-point.
It is below lk+w in point form. The round trip delay from sending out a transmission frame to receiving a reception frame at a network termination device is 10 to 14 μs in a single bus configuration. On the other hand, in the expanded bus mode and point-to-point mode, it is 10 to 32μ.
However, the delay difference between terminals is limited to 1.4 μs.

Communication is carried out between the network termination equipment and the terminal via the T line and the R line, and the channel structure on the T line and Rkjl is, for example, 64 KB/s information channel B (11, B (2) and 1
It is time-division multiplexed with a 6 KB/s signal channel D, and a frame synchronization signal F is added to determine transmission and reception timing. 10 as a transmission code
0% AMI is used. 1” is 0 for 100% AMI
The level "0" uses positive and negative pulses alternately. As the frame synchronization signal, a violation is used in which "θ" and "0" successively rise to the positive or negative side.

In single-bus configurations, it is preferable to use a fixed-phase clock as the retiming clock at the network termination, since in this configuration there is no limit to the distance between the terminals. data has a closed eye pattern, so even if you try to recover the clock from the received signal using DPPL etc., the amount of clock jitter is large and it is not suitable as a retiming clock, whereas round trip delay is This is because the delay amount is as small as 10 μs to 14 μs, so data from each terminal can be read even with a fixed phase clock.

On the other hand, in the case of expanded bus configurations and point-to-point configurations, the round trip delay is as wide as 10 to 32 μs, so with a fixed phase clock, signals from each terminal are read by the network termination equipment. However, since the time difference between each terminal is limited to 1.4 μs, the amount of jitter is small even with a reproduced clock using a DPLL or the like, so it is appropriate to use this reproduced clock as a retiming clock.

In this way, the retiming clock in the network termination equipment can be either a fixed phase clock or a D
It is preferable to select and use a clock reproduced by a PLL or the like. As a method for automatically carrying out this selection, a patent application filed by the present applicant: Japanese Patent Application No. 149235/1983 entitled "Clock Selection Control System" is proposed.

This clock selection control system automatically switches read clocks by replacing each connection type with the distance from the network termination equipment to the shortest terminal, and a block diagram of the main part thereof is shown in FIG. The device shown in FIG. 5 is installed in the network termination device, and 1 is a receiver, 2' is a shortest terminal distance identification circuit, 3 is a digital phase synchronization circuit, 4 is a retiming circuit, 5 is a selector, and 6 is a transmitter. It is a control circuit.

The shortest terminal distance identification circuit 2' extracts the received frame timing bit from the output signal from the receiver 1 based on the transmitted frame timing bit from the transmission control circuit 6, and measures the amount of delay time thereof. The connection form is determined and detected, and the detection signal is sent to the selector 5.

The selector 5 selects either the reproduced clock from the digital phase synchronization circuit 3 or the fixed phase clock from the transmission control circuit 6 as a retiming clock in accordance with the detection signal, and supplies the retiming clock to the retiming circuit 4.

A block diagram of the conventional shortest terminal distance identification circuit 2' in the apparatus shown in FIG. 5 is shown in FIG. In Figure 6, 21
' is a frame detection circuit, 22 is a monostable multivibrator, 23 is an AND circuit, 24 is an RS flip-flop,
25 is a D flip-flop. FIG. 7 shows signal waveforms at various parts of the circuit of FIG. 6. In Figure 7, the English letter (a
), (b), (C).

The waveforms shown in (d) and (e) are signal waveforms at locations indicated by the same reference numerals in FIG. 6, respectively. Here, the signals (C) I and (Q) I are the signals when the connection is a single bus, and the signals (C) t and (t') t are the signals when the connection is an expanded bus or point-to-point. This is an example.

When the transmission frame timing signal (a) is supplied as an input to the monostable multivibrator 22, the monostable multivibrator 22 outputs an "H" level signal for a fixed period of time every time the signal (a) is input.

This certain period of time is selected to be a value within which a single bus connection mode is determined. On the other hand, frame detection circuit 2
1' receives the received signal from the terminal, and the received frame timing signal (
C) is extracted and output.

The received frame timing signal (C) and the output signal from the monostable multi-bi break 22) are connected to the AND circuit 23.
The comparison result is the RS flip-flop 24
The D flip-flop 25 outputs it as an "H" or "L" level detection signal depending on the connection type.

That is, the received frame is detected from the frame detection circuit 21'.
When the timing signal (C) is output, go to N
This signal (C)1 via the D circuit 23 sets the RS flip-flop 24 and outputs the output signal (dl), so that the output of the D flip-flop 25 is always "
The detection signal (e)1 is high, and it can be determined that the connection type is a single bus.

On the other hand, when the output signal from the frame detection circuit 21' is the received frame timing signal (c)t, this signal (C)2 is cut off by the NO circuit 23, so the RS flip-flop 24 is set. is absent, so its output is always L'', and the D flip-flop 2
5 outputs the "L level detection signal (e) 2", and it can be determined that the connection type is an expanded bus or point-to-point.In this way, the transmission frame timing and reception frame timing can be determined. Automatically learns the connection type by measuring the time difference between
A preferred retiming clock can be selected.

A conventional block diagram of the receiver 1 and frame detection circuit 21' is shown in FIG. 8, and signal waveforms of various parts in FIG. 8 are shown in FIG. S (1) to 5Q4) in Figure 9
The waveforms shown in FIG. 8 are signal waveforms at locations indicated by the same reference numerals in FIG. In FIG. 8, receiver 1 is a comparator CM
Consists of PI and CMP2. The frame detection circuit 21' is
A rising edge detection circuit 211 that detects the rising edge of the received signal S (1) toward the positive side, a rising edge detection circuit 212 that detects the rising edge of the received signal 5 (1) toward the negative side, and a pulse of "00" that continues on the positive side. a detection circuit 213 that detects , a detection circuit 214 that detects continuous "OO" pulses on the negative side,
The circuit includes a detection circuit 215 for detecting a pie oscillon with 1 in between, such as 010, and a NAND circuit 216.

To explain the operation of the circuit in Figure 8, the received signal S from the terminal
(1) is for receiver 1 and Nte comparator CMP1. C
MP2 separates them into "0" signals on the positive and negative sides, respectively. These signals S (2), S (3)
The rise detection circuits 211 and 212 perform rise differentiation to detect rises to the positive and negative sides, respectively, and the detection signals 5 (4) are output from the rise detection circuits 211 and 212.

5 (7) are output respectively.

If the "H" bit H0 in front of the pyreshiron and the violation (v)1 are separated by an interval, such as violation (V) in FIG. 9, this violation is It is detected by the detection circuit 215. That is, the RS flip-flop FF5 is set and reset by the signals obtained by delaying the detection signals S (4) and 5 (7) by one clock, and the output signal SQI and the inverted output signal 5aiJ of the RS flip-flop FP5 are used to set and reset the OR circuits G5 and G4. is controlled to open and close. In FIG. 9, the detection signal 5 corresponds to the “H” pit H0.
(4) sets the RS flip-flop PF5, its inverted output signal Sαυ opens the OR circuit G4, and then the detection signal 5(4) corresponding to the violation (V) passes through the OR circuit G5. The signal S becomes the signal 5 (121), and this signal S (transition) is further outputted as the detection signal S G4 via the NANO circuit G7.

Next, when violation (v) 2 and the previous "H" bit occur consecutively, as in violation (v) 2 in FIG.
detected by. That is, the detection signal 5(7) corresponding to the "H" bit H2 is delayed by one signal by the shift register SR2 and is input as the signal 5(8) to the OR circuit G6. It is controlled so that it is opened when it is at "H" and closed when it is at 'L'. Therefore, in the case of violation (v) 2, the detection signal 5 (7) corresponding to the 'H' bit H2 is sent to the shift register S.
R2, NAN as signal 5 (9) via OR circuit G6
The signal is input to the D circuit G7, and sent out as a violation detection signal 5Q4) via the NAND circuit G7.

[Problem that the invention seeks to solve]

In the current CCITT proposal, the frame format is as shown in FIG. In Fig. 1θ, F is a frame bit, L is a DC balance bit, and Bl is a B
1 channel bit, B2 is B2 channel bit, D
is the D channel bit, E is the D channel echo bit, A
is the starting bit, Fa&! Always 0” auxiliary frame bit, Sl.

B2 is a spare bit, the upper diagram shows a transmission frame from the network termination device to the terminal, and the lower diagram shows a reception frame from the terminal to the network termination device.

As can be seen from FIG. 10, in the CCITT proposal, the received frame bit at the network termination device is always a violation on the positive side, and the bit before it is the balance bit L of the D channel. This balance bit is a bit inserted to adjust the number of "13s and 0s" in the frame.

In this way, the bit immediately before the received frame bit is the balanced bit of the D channel, so for example, if the farthest terminal is communicating via the D channel and the balanced bit L becomes H'', this balanced bit L and the received frame bits are consecutive, making it impossible to differentially detect the rising edge of the received frame bit.Therefore, in the circuit of FIG. ing.

For this reason, originally, the received frame is determined by the signal from the shortest terminal.
There is a problem in that the timing to be determined is determined based on the signal from the farthest terminal.

In addition, in CCITT There is a problem.

[Means for solving problems]

Means for solving the above-mentioned problems will be explained with reference to the principle block diagram shown in FIG. In the present invention, the connection form between the network termination device and the terminal is identified by the delay time difference from the sending timing of the transmission frame at the network termination device to the reception timing of the reception frame, and a retiming clock is selected according to the connection form. A first detection circuit 10 detects the reception timing of a received frame by detecting a violation of received frame bits to one polarity side.
1. A second detection circuit 102 detects that the bit immediately before the received frame bit has the same polarity as the violation, and compares the reception timing detected by the first detection circuit with a predetermined reference time. A comparison circuit 103 identifies the connection form between the network termination device and the terminal device based on the comparison result, and when the second detection circuit detects that the previous bit has the same polarity as the violation, A network termination device comprising a holding circuit 104 that holds the identification result of a comparison circuit at the immediately previous identification result, and a selection circuit 105 that selects a retiming clock according to the connection form according to the identification result of the comparison circuit. A clock selection control device is provided.

[For production]

When the second detection circuit detects that the bit immediately before the received frame bit has the same polarity as the violation, the comparison result of the comparison circuit is held at the state immediately before that bit. This prevents connection type identification errors from occurring and improves reliability.

〔Example〕

A clock selection control device for a network termination device as an embodiment of the present invention will be described below.

1Lit ■ Deep bottom The main part block diagram of the apparatus of this embodiment is the same as that shown in FIG.

In FIG. 5, a received signal S (1) from a terminal is guided to a receiver 1. The output signal of the receiver 1 is connected to the shortest terminal distance identification circuit 2 and the digital phase synchronization circuit 3, respectively.
, and to the retiming circuit 4. The transmission frame timing signal (al) is introduced from the transmission control circuit 6 to the shortest terminal distance identification circuit 2. The selection input terminal of the selector 5 receives the reproduced clock from the digital phase synchronization circuit 3 and the fixed phase signal from the transmission control circuit 6. A clock is guided, and a detection signal (h) from the shortest terminal distance identification circuit 2 is guided to the control input terminal.The selection output signal of the selector 5 is supplied to the timing circuit 4.

A block diagram of the shortest terminal distance identification circuit 2 in the apparatus shown in FIG. 5 is shown in FIG. In FIG. 11, the output signal from receiver 1 is guided to frame detection circuit 21. In FIG.

The frame detection circuit 21 outputs a detection signal (C) when the balanced bit L immediately before the received frame bit is "L" and a detection signal (d) when the balanced bit L is "H". The detection signal (C) is guided to the AND circuit 23, and the detection signal (d) is guided to the clock input terminal of the D flip-flop 27.

The monostable multipipe lake 22 has a transmission frame timing signal (al) guided from the transmission control circuit 6 to its input terminal, and its output signal (bl is ANf) circuit 23.
guided by. The output signal of the AND circuit 23 is guided to the set input terminal of the RS flip-flop 24, and the output signal (e) of the RS flip-flop 24 is sent as an output signal (g) via the OR circuit 28 to the data input of the D flip-flop 7 block 25. guided to the terminal.

The output signal (h) of the D flip-flop 25 is guided to the data input terminal of the D flip-flop 27, and the output signal <r> of the D flip-flop 27 is guided to the AND circuit 28. Further, the transmission frame timing signal (a) from the transmission control circuit 6 is guided to the reset input terminal of the RS flip-flop 24, the clock input terminal of the D flip-flop 25, and the clear input terminal of the D flip-flop 27, respectively.

A detailed circuit configuration of the frame detection circuit 21 in the receiver 1 and the circuit in FIG. 11 is shown in FIG. 13. Receiver 1 consists of comparators CMPI and CHF2, and compares the received signal S(1) with predetermined thresholds THI and TI(2) using comparators CMPI and CHF2 to set the positive and negative sides to "H" level, respectively. Detects the “0” bit.

These detection signals 5(2) and 5(3) are transmitted to the frame detection circuit 2.
1 rise detection circuit 211 and rise detection circuit 212
guided by each.

The rise detection circuit 211 is a circuit that detects the rise of the received signal S (1) to the positive polarity side, and is a circuit that detects the rise of the received signal S (1) to the positive polarity side. FF2. It is configured to include a NAND circuit G1. Also, the rising edge detection circuit 212 detects the received signal S (1)
This circuit detects the rise of D flip-flops FF3. FF4. and NAND circuit G2
It consists of: The output signal of rising detection circuit 211 is guided to detection circuits 213 and 215. Detection circuit 2
13 is a circuit that detects the pi-o-ray cycle of “00” that rises continuously to the positive side, and is connected to the shift register S.
It is composed of RI and OR circuit G3.

The detection circuit 217 is a circuit that detects a violation with 1 in between, such as "010", and includes RS flip-flops FF5. D flip-flop FF6. OR circuit G4
Consists of.

The operation of the device of this embodiment will be explained below with reference to the waveform diagram of FIG. 12. Figure 12 is a signal waveform diagram of each part of the circuit in Figure 11, and each waveform indicated by letters (a) to (h) in the figure is a waveform diagram of each part of the circuit shown in Figure 11. It is a signal waveform. Here, signals (C) 1 to (h) I are single bus connections, and (C) 2 to (h) 2 are point-to-point or extemporized.
This is an example of a signal for a bus.

The operation when the detection signal (C) is output from the frame detection circuit 21 is the same as described above. In other words, the transmission frame is input to the monostable multipipe lake 22.
When the timing signal (a) is supplied, the monostable multivibrator 22 generates "
The frame detection circuit 21 outputs a signal peak of "H" level). This fixed time is set to a time range that is determined to be a single bus based on the transmission frame timing signal (a). On the other hand, the frame detection circuit 21 outputs When a received signal is received, a received frame timing signal (C) is extracted from the signal by violation and output.

The received frame timing signal (C) and the output signal (b) from the monostable multivibrator 22 are connected to an AND circuit 2.
3, and the comparison result is the RS flip-flop 2
4 and D flip-flop 25 output as an "H" or L level detection signal depending on the connection type.

That is, when the received frame timing signal (c) I is output from the frame detection circuit 21, AND
This signal (C) via the circuit 23 sets the RS flip-flop 24 and outputs the output signal (e)I, which is sent via the OR circuit 28 to a signal (phantom).

As a result, the output of the D flip-flop 25 is always an "H" detection signal (h), and it can be determined that the connection type is a single bus.

On the other hand, when the output signal from the frame detection circuit 21 is the received frame timing signal (C) 2, this signal (
C)2 is cut off by the AND circuit 23, so the RS flip-flop 24 is never set, so its output is always "L", and the D flip-flop 25
A detection signal (h) 2 of L'' level is output from , and it can be determined that the connection type is an extemped bus or point-to-point.

Next, when the detection signal (d) when the balanced bit immediately before the received frame bit is "H" is output, this detection signal (d) causes the D flip-flop 27 to output the identification detection signal (h ) and gives the corresponding output signal (f) as a signal (Shu) to the data input terminal of the D flip-flop 25 via the OR circuit 28.Thereby, when the detection signal (d) is output, the distance identification is performed. is not performed, and the D flip-flop 25 maintains the previous output state,
Stable output can be obtained. The above operation is performed by the detection signal (d)I.

(d) The same applies to both of 2.

The operation of the frame detection circuit 21 in FIG. 13 is substantially the same as that described with respect to FIG. In this case, the circuit shown in FIG. 13 is not provided with a detection circuit 214 for detecting violation on the negative electrode side.

Then, the detection circuit 217 outputs a detection signal (C
) is sent out, and on the other hand, the detection circuit 215 sends out a detection signal (d) that is output when the balanced bit L immediately before the reception frame bit F is "H". According to such a circuit configuration, the circuit is simplified and more economical.

〔Effect of the invention〕

According to the present invention, when the balance bit immediately before the reception frame focus is at H" level and the judgment of the reception frame timing becomes uncertain, the output state immediately before that is maintained, so that the network terminal device This makes it possible to more reliably detect the connection form with the terminal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIGS. 2 to 4 are diagrams showing the connection form between a network termination device and a terminal, and FIG. 5 is a block diagram of a main part of a clock selection control device of the network termination device. 6 is a block diagram of the conventional shortest terminal distance identification circuit in FIG. 5, FIG. 7 is a signal waveform diagram of each part in the circuit of FIG. 6, FIG. 8 is a detailed circuit diagram of the conventional frame detection circuit, and FIG. 8 is a diagram showing the signal waveforms of various parts in the circuit, FIG. 10 is a diagram showing the frame formant, FIG. 11 is a block diagram of the shortest terminal distance identification circuit showing an embodiment of the present invention in FIG. 12 is a signal waveform diagram of each part in the circuit of FIG. 11, and FIG. 13 is a detailed circuit diagram of the frame detection circuit in the circuit of FIG. 11. DESCRIPTION OF SYMBOLS 1... Receiver, 2.2'... Shortest terminal distance identification circuit, 3... Digital phase synchronization circuit, 4... Retiming circuit, 5... Selector, 6... Transmission control circuit, 21, 21'...frame detection circuit, 22...
Monostable multivibrator, 23...AND circuit, 24...RS flip-flop, 25, 27...D flip-flop, 28...O
R circuit, 211, 212...Rise detection circuit, 213.214
, 217...detection circuit. Point-to-point configuration Figure 5 Block diagram of clock selection control device 16
Figure 91' Block diagram of the conventional shortest terminal distance identification circuit
Fig. 8 Circuit diagram of conventional frame detection circuit
9 Figure 5 (5) Signal waveform diagram of each part in Figure 8
”“5 (14)
・0# Fig. 11 Shortest terminal distance identification circuit according to an embodiment of the present invention Fig. 12 Signal waveform diagram of each part in Fig. 11

Claims (1)

[Claims] The connection form between the network termination device and the terminal is identified by the delay time difference from the sending timing of the transmission frame to the reception timing of the reception frame in the network termination device, and a retiming clock is determined according to the connection form. In the clock selection control device of the selected network termination device, a first detection circuit (101) detects the reception timing of the received frame by detecting a violation of the received frame bits to one polarity side; a second detection circuit for detecting that the bit immediately before the bit has the same polarity as the violation;
102), a comparison circuit (103) that compares the reception timing detected by the first detection circuit with a predetermined reference time and identifies the connection form between the network termination device and the terminal device based on the comparison result;
, a holding circuit (104) that holds the identification result of the comparison circuit at the immediately previous identification result when the second detection circuit detects that the immediately previous bit has the same polarity as the violation; , a selection circuit (105) that selects a retiming clock according to the connection form according to the identification result of the comparison circuit.