JPS61218963A - Logic circuit - Google Patents

Abstract

PURPOSE:To minimize added circuits and wiring and to test easily a logical function by setting specified data on a means for designating whether or not the access to a memory means installed on each memory means becomes possible through other parts. CONSTITUTION:After a reset signal RST resets all FFs 103-1-103-n, a set signal ST sets only the FF 103-1, whereby the access to a register 102-1 and those to other registers become possible and inhibited, respectively. Then a testing write signal TXW and the prescribed data signal DATA are inputted to write the prescribed data in the register 102-1. By switching a mode, a combined circuit 101 executes the logical arithmetic with the aid of the data on the register 102-1, and its result is outputted to a register 102-1, after which the operation is again switched to a test mode. After the signal SRT resets the FF 103-1, the signal ST sets the FF 102, and the access to the register 102-2 becomes possible. Then the signal TXR is inputted, and the data on the result is read out of the register 102-2 through a data bus 106.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a logic circuit that can easily perform logic function tests.

[Technical background of the invention and its problems]

Tests for logic integrated circuits include a DC characteristics test that tests the DC characteristics of the circuit, an AC characteristics test that tests the AC characteristics, and a logic function test that tests the logic function. Among these, logic function tests are always performed both in pass/fail judgment tests on mass production lines and in acceptance inspections by users, and it is important to perform them efficiently and with appropriate IF.

When testing on a mass production line, the conventional method was to directly apply a needle to a semiconductor chip on which a logic integrated circuit was formed to monitor the logic state of the necessary nodes. However, as logic integrated circuits become increasingly finer, it is becoming extremely difficult to accurately target the nodes to be monitored using this method. Furthermore, in recent years, automatic placement and routing programs have been increasingly used to design logic integrated circuits, and it has become difficult to accurately specify desired nodes. There are many problems with this method of directly applying a needle to a semiconductor chip to monitor the state of the necessary nodes.

Furthermore, the conventional scan method and parallel scan method are known as methods for easily conducting logic function tests. The scanvase method is constructed by adding flip-flops to each storage element such as a flip-flop or register connected to a combinational circuit in a logic circuit, and connecting the whole circuit in a shift register manner. During a logic function test, first input initial data into these storage elements in test mode, then perform calculations using the combinational circuit in calculation mode.
The resulting data is read from these storage elements again in test mode. This scanspace method is extremely effective when flip-flops are distributed within a logic circuit. However, in this method, it is necessary to provide one 7-lip 70-tub for each flip-flop in the logic circuit, so there is a problem that the additional circuit becomes large in a logic circuit with many flip-flops.

The parallel scan method is a method in which addresses are given to storage elements such as 7 lips and registers in a logic circuit, and these addresses are used to access these storage elements. However, in this method, it is necessary to either give the address to the storage element externally or set the address in an address register, and in order to access each storage element, a circuit for decoding the address is required.
Wiring is required to provide access enable signals to each storage element. Therefore, when a parallel scan type logic circuit is integrated, external terminals for giving addresses to storage elements are required, and the number of additional internal wirings increases.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a logic circuit that requires fewer additional circuits and additional wiring, is easy to control, and can easily perform logic function tests.

[Summary of the invention]

In order to achieve the above object, the logic circuit according to the present invention provides each storage means with designation means for designating whether or not access to the storage means is enabled, and specifies data from other parts to these designation means. It is characterized in that it can be set.

[Embodiments of the invention]

A logic circuit according to a first embodiment of the present invention is shown in FIG.

This logic circuit performs the original logic operation by the combinational circuit 101. This combinational circuit 101 receives an input signal I! 1
109-1 to 109-n and output signal lines 110-1 to
Multi-bit registers 102-1 to 10 by 110-n
2-n are connected. Input data, output data, etc. to the combinational circuit 101 are stored in these registers 102-1 to 102-1.
02-n. Registers 102-1 to 102-
A calculation clock PCK is inputted to n by a signal 1104.

A control signal line 105 for inputting a test write signal TXW and a test read signal TXR, and a data bus 106 for inputting/outputting a data signal DATA are connected to the registers 102-1 to 102-n.

By inputting the test write signal TXW in the test mode, data is transferred to the register 102-1.
102-n and input the test read signal TXR to read data DATA from the registers 102-1 to 102-n.

In addition, flip-flops (
FF) 103-1 to 103-n are connected. These flip 70 tabs 103-1 to 103-n enable access to registers 102-1 to 102-n (
This is provided for specifying whether to enable use) or disable (prohibit use). this flip 70
The reset signal line 107 is connected to the knobs 103-1 to 103-n.
and set signal 11108 are connected, and reset signal R8
The specified data is 7 rip 7 by T and set signal ST.
It is set to 0 bits 103-1 to 103-n.

In the test mode, an operation will be described in which, for example, data is written to the register 102-1, a logical operation is performed in the combinational circuit 101, and then data resulting from the logical operation is read from the register 102-2. First, all the 7 flip-flops 103-1 to 103-n are reset by the reset signal R8T, and then the 70 flip-flops 103-n are reset by the set signal ST.
Set only 03-1. As a result, register 102
-1 becomes accessible and other registers 102-2 to 102-1
Access to 02-n is prohibited. Next, input the test write signal TXW and a predetermined data signal DATA,
Write predetermined data to register 102-1. Next, switch from test mode to calculation mode, register 102-1
The combinational circuit 101 performs a logical operation using the data, and after the resulting data is output to the register 102-2, the mode is switched to the test mode again. Next, after the flip 70 tab 103-1 is reset by the reset signal R8T, the flip 70 tab 103-2 is set by the set signal ST. This makes only register 102-2 accessible. Next, a test read signal TXR is input, and the resulting data is read from the register 102-2 via the data bus 106.

As described above, according to this embodiment, data can be input/output to/from any register by simply adding 70 flips, which is extremely small compared to the total number of bits of the register.

FIG. 2 shows a logic circuit according to a second embodiment of the invention.

This embodiment differs from the first embodiment in the method of setting designated data to the flip 70 knob 103-1. In this embodiment, flip 70 tabs 103-1 to 103-n are connected in series,
A cert data signal line 112 is connected to the first seven lip-flops 103-1. flip 70 tube 103
-1 to 103-n are set by inputting set data 5TDT in series from the set data signal line 112. For example, in order to enable only register 102-1, flip-flop 103-1 is enabled.
When setting 1, n bits “00...
・01'' set data 5TDT may be sequentially input to the set data signal line 112.

According to this embodiment, only the set data signal line is required as a signal line (designated data can be set in the flip 70 tube with a very small number of additional wiring lines).

FIG. 3 shows a logic circuit according to a third embodiment of the invention.

In this embodiment, flip 70 tabs 103-1 to 103-n are provided in registers 102-1 to 102-n, respectively.
Connect in a ring shape.

That is, the flip-flops 103-1 to 103-n are connected in series, and the final stage flip-flop 103
-n to the first flip-flop 103-1.

Further, a shift clock SCK is inputted to these flip-flops 103-1 to 103-n via a signal line 113. Further, a setting signal SS of designated data is inputted to each flip-flop 103-1 to 103-n via a signal line 114. This signal 1114 is connected to the set input terminal S of the flip 70 knob 103-1 and the flip 70 knob 103, for example.
-2 to 103-n reset input terminals R. Therefore, when the setting signal SS is input, only the flip-flop 103-1 is set to "1", and the other 7-lip 70-tubes 103-2 to 103-n are reset to "0". If it is desired to set the other 7 lip-flops, a predetermined number of pulses are input as the shift clock SGK to sequentially transfer designated data. For example, if you want to set the fourth 7-lip 70-tub 103-4 and access the register 102-4, first input the setting signal SS and set the flip-flop 103-1 to "1".
After setting , a 3-pulse shift clock SGK may be input to transfer designated data only in 3 stages.

According to this embodiment, data can be set in any 7 and 70 bits using a small number of signal lines and a simple tJIm signal.

FIG. 4 shows a logic circuit according to a fourth embodiment of the present invention.

In the logic circuit according to this embodiment, the flip-flop 103
A decoder 116 is provided to set designated data to -1 to 103-n. This decoder 116
15, decodes the address ADR8 input via
A set signal is output to the flip 70 knob at that address. The addresses for determining the flip-flops may be determined by using the upper bits of the addresses consecutively assigned to the registers 102-1 to 102-n, or separately assigned to the flip-flops 103-1 to 103-n. It is also possible to use the address given. flip 70 tube 1
Signal lines 117-1 to 117-n from the decoder 116 are connected to the set input terminals S of 03-1 to 103-n, and a reset signal line 107 is connected to the reset input terminal R. . First, all the 7-lip 70-tubes 103-1 to 103-n are reset by the reset signal R8, and then the address ADR8 of the flip-flop to be set is input to the decoder 116. Decoder 11
6 decodes the input address ADR8 and enters the predetermined 7
Outputs a set signal to the lip 70 tube.

In this way, in this embodiment, the desired 7 lips and 70 lips can be directly set by inputting the address, so that a quick test can be performed.

〔Effect of the invention〕

As described above, according to the present invention, only an arbitrary storage means can be accessed with a small number of additional circuits and wiring, and a logic function test can be performed easily and quickly.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a logic circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a logic circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a logic circuit according to a second embodiment of the present invention. FIG. 4 is a circuit diagram of a logic circuit according to a fourth embodiment of the present invention. 101...Combination circuit, 102-1 to 102-n...
・Register, 103-1 to 103-n...Flip-flop (FF), 116...Decoder, PCK...
Arithmetic clock, TXW...Test write signal, TXR
...Test read signal, DATA...Data, R3
T...Reset signal, ST...Set signal, 5TD
T...set data, SGK...shift clock,
SS...setting signal, ADR8...address. Applicant's agent Kiyoshi Inomata Figure 2

Claims (1)

[Claims] 1. A plurality of storage means, a plurality of designation means provided for each of these storage means for specifying whether or not to enable access to the storage means, and designation data stored in these designation means. A logic circuit comprising a setting means for setting. 2. In the logic circuit according to claim 1, the plurality of specifying means are connected in series, and the setting means sequentially inputs specifying data to the plurality of specifying means connected in series. Characteristic logic circuit. 3. In the logic circuit according to claim 1, the plurality of specifying means are connected in a ring shape, and the setting means sequentially transfers the specified data set to the plurality of specifying means. logic circuit. 4. In the logic circuit according to claim 1, the setting means has a decoding means for decoding the addresses of the plurality of specifying means, and the setting means sends specified data to the specifying means of the address decoded by the decoding means. A logic circuit characterized by setting.