JPS61217999A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To use and select as two types of memories of an ECC circuit incorporating type of non-incorporated type by providing a means for selecting and controlling a function of the ECC circuit provided on a memory chip to a valid condition or to an invalid condition in accordance with the result detecting whether an ECC circuit selecting signal is impressed to an external terminal or not. CONSTITUTION:There is provided an ECC circuit selecting signal detecting circuit 5 for detecting whether an ECC circuit selecting signal is impressed or not within a fixed period in an external terminal 1. There is provided an ECC function selecting control means 6 that in accordance with an output signal of this detecting circuit 5, a connecting condition of an ECC circuit and a memory circuit 3 is changed over and controlled to a valid or an invalid condition. As enbodiment of this selecting control means 6, a switch circuit for selecting and controlling the circuit connection of the ECC circuit 4 and the memory circuit 3 may be disposed, or a part of gates in the ECC circuit 4, for example, a parity inspection result data inputting AND gate 39 in a correction data producing circuit 37 may be changed so as to perform a gate control by an ECC function selecting control signal from the ECC circuit selecting signal detecting circuit 5.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory in which an error correction circuit (ECC circuit) for detecting and correcting data errors is mounted on a chip, and the present invention relates to a semiconductor memory in which an error correction circuit (ECC circuit) for detecting and correcting data errors is mounted on a chip. The present invention relates to a semiconductor memory capable of selecting a high-speed read operation mode that does not use an ECC circuit and a high-reliability read operation mode that suppresses the probability of outputting an error through an ECC circuit depending on the situation.

[Technical background of the invention]

In semiconductor memory, in order to provide high reliability by relieving soft errors induced by radiation such as alpha rays or No-P errors that are more likely to occur due to miniaturization of circuits, Examples of devices equipped with ECC circuits are well known. For this ECC circuit, from a practical point of view that takes into account the simplicity of the configuration, a system that corrects a one-pit error in data is often adopted. As an example of a conventional ECC circuit, FIG. 3 shows "Self-correction circuit in IMb DRAM" published by Date et al. in IEICE Technical Report [Semiconductor-Transistor] 8SD84-2IP, 51-58. In this ECC circuit,
When reading (6), when writing is due, and when refreshing (R.
f), error detection and correction is performed in units of four pits, and one bit from the four pits is selected as output data. Here, 31 is a data capuffer, 32 is an update data generation circuit, 33 is a multi-breather, 34 is a memory cell array, 35 is a selector, 36 is an arm check circuit, 37 is a correction data generation circuit, 3
8 is a data output part 7a.

Semiconductor memories equipped with such ECC circuits certainly have a lower probability of read data errors, but the data
By passing through the CC circuit, writing and reading times become longer than in a memory without an ECC circuit.

On the other hand, semiconductor memory that is not equipped with an ECC circuit is
Currently, it is widely used and speeding up reading and writing is being achieved, but as memory cell arrays become smaller, soft errors due to alpha rays, etc., and node errors due to minute turns are becoming a problem. However, high reliability cannot be guaranteed if it is left as is.

[Problems with background technology]

By the way, in large computer systems that require extremely high reliability, or systems that are so small that an ECC circuit cannot be installed on the system side and that require a certain degree of high reliability, the user can access them as memory. Even if it means sacrificing some time, I have no choice but to choose a highly reliable model equipped with an ECC circuit. On the other hand, there are fields of use where a certain amount of errors in read data due to soft errors etc. do not pose much of a problem. For example, E on the system side
Examples include medium-sized computer systems, where the reliability achieved by introducing CC circuits is already sufficient, and the field of processing image signals such as video signals. In these fields, the error rate of output data may be high to some extent, but the requirement for high-speed readout is critical, so there is a problem in that the memory equipped with the ECC circuit cannot be used.

Therefore, in order to meet the wide range of table demands for semiconductor memories, manufacturers had to simultaneously develop and manufacture two types: one with a built-in ECC circuit and one without.

In addition, on the user side, it is necessary to consider the field of use of the memory in advance and purchase the two types of memory mentioned above. could not be used freely in other fields with different fields. In other words, it is wasteful for both the manufacturer and the user to deal with two kinds of memories classified by high reliability and high speed.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and controls the function of the built-in ECC circuit to be enabled or disabled depending on whether or not an ECC circuit selection signal is applied to an external terminal. It is possible to use the same hardware memory, but it is possible to choose between two types of memory, one with a built-in ECC circuit and one without a built-in ECC circuit.
The present invention provides a semiconductor memory that reduces waste in terms of manufacturing and use.

[Summary of the invention]

That is, the semiconductor memory of the present invention selects the function of the ECC circuit provided on the memory chip to be enabled or disabled depending on the result of detecting whether or not the ECd circuit selection signal is applied to the external terminal. It is characterized by providing a control means.

Therefore, while using the same hardware memory, E
It is possible to choose between two types of memory, one with a built-in CC circuit and one without a built-in CC circuit, and when developing, manufacturing, and using memory, it is easier to narrow down to one type than when targeting ZSI types. You can eliminate waste.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Figure 1 shows a part of a dynamic memory with a built-in ECC circuit, and 1 is an external input to which a row address strobe signal (RAS) is input, which makes it possible to time-divisionally input address signals. It is a terminal.

2 is applied to the above external terminal 1 and the rise of the 9°C signal,
This is an image signal circuit that detects the falling edge and controls the operation of the memory circuit 3. As mentioned above, the operation of the memory internal circuit induced by a certain control signal such as the RAS signal input is determined only by the initial transition of the control signal, and the subsequent operation depends on the control signal for a certain period of time. A function that automatically continues and terminates within the memory circuit regardless of the situation is called a timeout function, and the memory of this example has a RAS timeout function. In this embodiment, focusing on the timeout function, an ECC circuit selection signal of the same level as a normal external input signal is applied for a certain period of time when the external terminal 1 becomes unnecessary for the 61 signal after the signal is input. Depending on whether the ECC circuit 4 is applied or not, the built-in ECC circuit 4 is selectively controlled to be enabled or disabled (or vice versa)9, and this memory is applied to the above ECC circuit selection signal. The presence or absence of application and timing can be controlled by software on the system side. In order to realize this, an ECC circuit selection signal detection circuit 5 is provided for detecting whether or not an ECC circuit selection signal is applied to the external terminal 1 within the predetermined period.
GC for controlling the connection state between the 100 circuit 4 and the memory circuit 3 to be enabled or disabled according to the output signal of
c-Function Function selection control habits 6. As a specific example of this selection control means 6, a switch circuit for selectively controlling the circuit connection between the ECC circuit 4 and the memory circuit 3 may be provided, or a switch circuit for selectively controlling the circuit connection between the ECC circuit 4 and the memory circuit 3 may be provided. As shown in FIG. 2, the AND gate 39 for inputting the normality inspection result data in the corrected data generation circuit 32 is controlled so that dart control is performed by the ECC function selection control signal from the ECC circuit selection signal detection circuit 5. There is a way to change it.

That is, in the memory with the above configuration, the RAS input terminal 1
The ECC circuit selection signal detection circuit 5 detects whether or not the ECC circuit selection signal is applied during a certain period after inputting the image signal, and the detection output determines whether the ECC circuit function is valid or invalid. A function as a memory with a built-in ECC circuit or a function as a memory without a built-in ECC circuit is selectively controlled. In this way, it is possible to select between two types of memory by selecting functions using external signals, but since the memory hardware is the same and standardized, various advantages can be obtained as follows. .

In other words, (1) Manufacturers developed two types of memo + 3 at the same time in terms of research, development, and manufacturing (one with no built-in ECC circuit and therefore high error rate but capable of high-speed operation, and one with ECC
Since the circuit is built-in, the error rate is low, but all the waste (labor costs, mask costs, etc.) associated with low-speed operation being set to 0 can be eliminated. (2) The user side can save a lot of waste (such as purchasing spare parts for each type when there is no flexibility in changing the use, etc.) by purchasing the two types of memory according to the purpose. (3
) If the error rate due to erroneous errors that occur in the memory used differs depending on the system usage environment, the appropriate memory function can be set according to the system usage environment by simply switching the software and reversing the presence/absence of the ECC circuit selection function in the same system. You can choose. (4) When using an ECC circuit with built-in memory for relieving node errors, select the ECC circuit function if the node error is within the allowable range and use it as a means of low-speed operation. Those that do not occur can be used as high-speed operation types without selecting the GCC circuit function, which is useful for improving yield and memory performance.

Note that the present invention is not limited to the above-mentioned embodiment, and the external terminal 1 may be other than the i signal input terminal as long as it is connected to an internal circuit having a timeout function. In addition, by applying the gcc circuit selection signal,
The two functions are selected during the read operation, and we focused on the fact that the data input terminal Din is not needed at this time (the write enable signal WE input is at a high level and is not used for data writing). The selection of the two functions may be switched depending on whether or not an ECC circuit selection signal is applied to the data input terminal at the same time. Further, semiconductor memories to which the present invention can be applied are not limited to dynamic memories.

〔Effect of the invention〕

As described above, according to the semiconductor memory of the present invention, the function of the built-in ECC circuit can be set and controlled to be either enabled or disabled depending on whether or not an ECC circuit selection signal is applied to the external terminal. Since it is the same hardware, it is possible to select whether to use it as two types of memory: a type with a built-in ECC circuit or a type without a built-in ECC circuit. therefore,
Compared to developing, manufacturing, and using the above two types of memories, developing, manufacturing, and using the memory of the present invention results in less waste.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a part of a dynamic memory according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the GCC function selection control means in FIG. 1, and FIG. 1 is a configuration explanatory diagram showing an ECC circuit system of a conventional dynamic memory. 1... External terminal, 2... RAS signal circuit, 4...
ECC circuit, 5... ECC circuit selection signal detection circuit, 6
...ECC function selection control means. Applicant's agent Takehiko E, patent attorney Figure 1 Figure 3

Claims (4)

[Claims] (1) Control means for selectively controlling the function of the error correction circuit provided on the memory chip to be enabled or disabled depending on the result of detecting whether or not an error correction circuit selection signal is applied to an external terminal. A semiconductor memory characterized by comprising: (2) A control signal is input to the one external terminal as a normal input signal, and the internal circuit to which this control signal is input is activated only by the initial transition of the control signal input, and the control signal is input for a certain period of time after activation. The error correction circuit selection signal has a timeout function that automatically continues the operation regardless of the state of the error correction circuit, and the application timing of the error correction circuit selection signal is set within the certain period of time. Range 1
Semiconductor memory described in Section 1. (3) The semiconductor memory according to claim 2, wherein the one external terminal receives a row address strobe signal. (4) The one external terminal is a data input terminal, and the application timing of the error correction circuit selection signal is set within a period when this data input terminal is not used for data writing. A semiconductor memory according to claim 1.