JPS61216074A - Direct memory access system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for performing direct memory access (hereinafter abbreviated as DMA) using a cycle steal method.
In particular, the present invention relates to a system in which lower-order devices such as input/output devices and slave processors that require long data set-up times and data hold times can perform DMA.

The main memory and input/output devices or slave processors controlled by the main processor reduce the burden on the main processor.
It is already known to use the DMA method when mutually transferring data without being controlled by the main processor.

There are various DMA methods such as bolt cycle steal, bolt burst, and tri-state control cycle steal, but all of them stop the main processor and access the main memory, so the data set-up time and There are no particular problems with input/output devices or slave processors that have long data hold times.

However, in the cycle-stealing method that allows data to be transferred at high speed, measures must be taken to take in data from input/output devices and slave processors, depending on the machine cycle speed of the main processor.

[Conventional technology]

FIG. 3 is a diagram illustrating the timing of DMA using the conventional cycle steal method.

As shown by the dotted line inside the clock in FIG. 3, conventionally, one clock cycle of the operating clock of the main processor is stopped, and
The period shown in parentheses (2) is used as a DMA cycle. As shown in the DMA data, the input/output device or slave processor that performs DMA transfers data with the main memory in this one machine cycle.

[Problem that the invention seeks to solve]

As mentioned above, DMA using the conventional cycle steal method
Since the DMA cycle is only one machine cycle,
When an input/output device or a slave processor with a long data set up time or data hold time performs DMA, there is a problem in that there may not be enough time to capture the data.

[Means for solving problems]

The problem mentioned above is that the main memory bus is connected to a direct memory bus.
a connection means for connecting to a bus of a lower-order device to be accessed;
latch means for latching transfer data between the lower device and the connection means; a control means for sending out a gate signal for operating the connection means and a signal for sending out the data latched by the latch means following the gate signal; The problem is solved by the direct memory access method according to the present invention, in which the data read from the main memory is supplied to the lower device by the gate signal, and the data latched by the latch means is continuously supplied.

[Effect]

In other words, the DM instructs the bus control circuit that connects the main memory bus to input/output devices or lower-order devices such as slave processors to operate.
Sends the A gate signal to send the transfer data read from the main memory to the lower device, supplies this transfer data to the latch circuit to latch it, and sends out the data latched by the latch circuit following the DMA gate signal. Ilo to do
A CS signal is supplied to a latch circuit, and transfer data is supplied to a lower-order device over two machine cycles.

By doing this, it is now possible to supply data in two machine cycles, whereas previously there was only one machine cycle to supply data, and the main memory can send out transfer data in one machine cycle as before. , it was possible to ensure that there was no difference in the operating time of the main processor.

〔Example〕

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 2 is supplied with a time clock to explain the operation of FIG. 1, and accesses the main memory 2 via the bus. As an input/output device, for example, the floppy disk control circuit 7 is
The main memory 2 is accessed via the bus control circuit 3 to send and receive data.

Therefore, the floppy disk control circuit 7 stores the data in the main memory 2 on the floppy disk via DMA via the bus control circuit 3, and also writes the data read from the floppy disk into the main memory 2 using DMA.

That is, when the floppy disk control circuit 7 accesses the main memory 2 by DMA, it controls the DMAIIJi circuit 6 and controls the bus control circuit 3 and the clock generation circuit 4 by using the DM in FIG.
Send the DMA gate signal as shown in the A gate.

The clock generation circuit 4 stops the clock supplied to the main processor 1 by one clock, as indicated by the dotted clock line, and the bus control circuit 3 connects the bus of the main memory 2 to the floppy disk control circuit 7.

The data read from the main memory 2 is supplied to the floppy disk control circuit 7 as shown in DMA data, and is also supplied to the latch circuit 5 and latched.

Following the sending of the DMA gate signal, the DMA control circuit 6 sends out the <Ilo CS signal to the latch circuit 5 as shown in FIG. , DMA data is supplied to the floppy disk control circuit 7 over two machine cycles.

The bus control circuit 3 only connects the bus of the main memory 2 to the floppy disk control circuit 7 while the DMA gate signal is being supplied, and the clock generation circuit 4 only stops supplying one clock worth of clocks. , the operating time of the main processor l remains the same as before.

〔Effect of the invention〕

As explained above, the present invention allows input/output devices and slave processors with long data set up times and data hold times to take in data in sufficient machine cycles.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, FIG. 2 is a time chart explaining the operation of FIG. 1, and FIG.
The figure is a diagram illustrating the timing of DMA using the conventional cycle steal method. In the figure, 1 is a main processor, 2 is a main memory, 3 is a bus control circuit, 4 is a clock generation circuit, 5 is a latch circuit, 6 is a DMA control circuit, and 7 is a floppy disk control circuit. Pavilion 2 Prisoner (C++ DMA-7--Nu-(D- Tea 3 figure

Claims (1)

[Claims] In a system that performs direct memory access using a cycle-steal method, a connection means connects a main memory bus to a bus of a lower device that performs direct memory access, and latches transferred data between the lower device and the connection means. a control means for sending out a gate signal for operating the connection means and a signal for sending out the data latched by the latch means following the gate signal; A direct memory access method characterized in that the read data is supplied via the bus and the data latched by the latch means is successively supplied.