JPS61214562A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To make the device resistant to noise and to make unnecessary a signal processing circuit using a preamplifier, by providing an optical signal- digitizing means of converting an optical signal into a digital signal corresponding thereto. CONSTITUTION:When a light is applied to a photodiode 1, an electric charge corresponding to the amplitude of a signal is accumulated in the diode 1. When a vertical charge transfer pulse is impressed on a vertical switch MOSFET 3 through a terminal 10, subsequently, the charge accumulated in the diode 1 is all transferred to a capacitor 9. FET 3 turns OFF from this state, and thereafter the same operation is repeated. Since the vertical charge transfer pulse is inputted into one input of a logic gate element 11 from the terminal 10 on the occasion, a signal is outputted from the element 11 the earlier in time in synchronization with the vertical charge transfer pulse as more an amount of charge is accumulated in the diode 1. Moreover, by providing a pulse counting circuit 12 and a binary-coding circuit 13 in the rear stage of the element 11, the number of pulses outputted from the element 11 is counted and binary-coded, and a value thus obtained is outputted from a terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state TI image device using a solid-state image pickup device.

[Conventional technology]

FIG. 3 is a diagram showing a conventional solid-state imaging device disclosed in, for example, Japanese Unexamined Patent Publication No. 54-27311.
1 is a photodiode that accumulates charge according to the optical signal;
2 is a vertical signal line, 3 is a vertical switch MO3) transistor that transfers the charge of the photodiode 1 to the vertical signal line 2, 4 is a horizontal signal line, and 5 is a transfer of the charge of the vertical signal line 2 to the horizontal signal line 4. 6 is a horizontal clock pulse input terminal, 7 is a vertical switch selection pulse input terminal, and 8 is a signal output terminal.

Next, the operation will be explained.

First, a charge corresponding to the optical signal is accumulated in the photodiode 1, and this charge is transferred to the vertical signal line 2 by turning on the vertical switch MO3) transistor 3 in response to a pulse input from the vertical switch selection pulse input terminal 7. be transferred.

Next, the horizontal switch MO3) transistor 5 is turned on by a pulse inputted from the horizontal clock pulse input terminal 6, so that the charge is transferred to the horizontal signal line 4. The signal charge is then output from the signal output terminal 8.

[Problem that the invention seeks to solve]

A conventional solid-state imaging device is configured as described above, and extracts an optical signal as an analog signal called the amount of charge. Therefore, noise leaks into the signal charge, especially the vertical switch MO5I-transistor 3 and the horizontal switch MO3).
The leakage of pulses to operate the transistor 5 is very large, and it is necessary to take out only the signal charge, amplify it, and process the signal while taking these noises into consideration.The design of the pre-stage amplifier for this purpose is extremely complicated and complicated. It had become something important.

The present invention was made to solve the above-mentioned problems, and aims to provide a solid-state TI image device that is resistant to noise and can eliminate the need for a pre-stage amplifier, which was conventionally required.

[Means for solving problems]

A solid-state imaging device according to the present invention is provided with an optical signal digitizing means for converting an optical signal, which is an analog signal, into a corresponding digital signal.

C Effect] In the present invention, since the optical signal digitizing means converts the optical signal into a corresponding digital signal and outputs it, the influence of noise leaking into the signal charge is eliminated.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a solid-state imaging device according to an embodiment of the present invention, and shows the configuration of one pixel. In the figure, 20
is a photoelectric conversion element; in the element 20, 1 is a photodiode that accumulates charge according to an optical signal, and 3 is a vertical switch (MO3) transistor (MOS switch transistor).

Further, 30 is an optical signal digitizing means for converting the charge transferred by the MO3) transistor 3 into a digital signal corresponding to the optical signal, and in the means 30, 9
10 is a vertical charge transfer pulse input terminal;
12 is an AND gate element which outputs a number of pulses corresponding to the potential of the capacitor 9 according to a vertical charge transfer pulse applied to the gate of the transistor 3; 12 is an output from the AND gate element 11; a pulse counting circuit for counting the number of pulses generated; 13;
14 is a MOS reset transistor for resetting the charge of the capacitor 9 at fixed time intervals; 15 is a MOS reset transistor for operating the MoS reset transistor 14; A reference pulse input terminal 7) is used to reset the count value of the pulse counting circuit 12, and 8 is a signal output terminal.

FIG. 2 shows the relationship between the input pulse and the output of the device of the above embodiment. In the figure, the width T of the vertical charge transfer pulse is T<<
It is assumed that Δt is satisfied, and the following t7-t6=t6-t5-
The operation will be explained as t5-t4-t4-L3=t3-t2-t2-t1ΣΔt.

The reset pulse shown in FIG. 2 (al) is input to the reset pulse input terminal 15 in FIG. 1, and the vertical charge transfer pulse shown in FIG. 2 (bl) is input to the vertical charge transfer pulse input terminal 10 in FIG. Now, the count value of the pulse counting circuit 12 is reset at time tQ by the reset pulse, and the MOS reset transistor 14 is turned on by this reset pulse, thereby resetting the charge in the capacitor 9 at the time t'Q. When the photodiode is irradiated with light for a time Δt from this state, charges corresponding to the magnitude of the optical signal are accumulated in the photodiode 1.

Next, at time t1, when a vertical charge transfer pulse is applied to the gate of the vertical switch MOS transistor 3 via the terminal 10, a voltage difference between the capacitance ICO of the photodiode 1 and the capacitance C1 of the capacitor 9 becomes CO If the following relationship holds true, all of the charge on the photodiode 1 is transferred to the capacitor 9. Further, the potential of the capacitor 9 at this time, that is, the input potential v1 of one side of the AND gate element 11 is as follows, assuming that the charge stored in the capacitor 9 is Ql.
Vl-Ql/CI. From this state, the vertical charge transfer pulse becomes low level (ΣOV), and the vertical switch MO
3) The transistor 3 is turned off, and then for a period of time Δt,
When the photodiode is irradiated with light, M charges are accumulated on the photodiode 1 again, and when a vertical charge transfer pulse is input to the vertical switch MO3I-transistor 3 at time t2, the charges are accumulated on the photodiode 1 at this time. Charge Q2 is transferred to capacitor 9, charge of Q1+Q2 is accumulated in capacitor 9, and one input voltage v2 of AND gate element 11 becomes V2- (Q1+Q2)/
Becomes a CI. Here, of course, V2 satisfies the relationship vl<v2.

If the same operation is repeated thereafter, if the capacitance C1 of the capacitor 9 is very large, the time tn (where n=0.1
．． 2.3.4, 5.6.7), between the charge Qn (however, Qo-0) stored in the capacitor 9 and one input voltage Vn of the AND gate element 11, Q md > Q m- P.

(However, the following relationship holds true: m=0.1.2.3.4.5.6).

Here, a high level signal is output from the AND gate element 11 only when one input voltage of the AND gate element 11 is at a high level equal to or higher than a certain appropriate level, and at the same time, the other input voltage is at a high level. Output. Therefore,
In this embodiment, one input of the gate element 11 is the potential of the capacitor 9, and the other input is the vertical charge transfer pulse, so that the larger the amount of charge accumulated in the photodiode 1 during Δt, the more A high-level pulse synchronized with the vertical charge transfer pulse is sent to the AND gate element 11 earlier in time.
This will result in more output. Furthermore, a pulse counting circuit 12 whose count value is reset by a reset pulse inputted from a terminal 15 after this AND gate element 11
By providing a binarization circuit 13, the number of pulses output from the AND gate element between each reset pulse is counted, and this is binarized and output from the signal output terminal 8.

As a more specific example, the output of each block when this solid-state imaging device 8 (1 m) is operated with respect to light sources with different luminances of 8 (ial) will be explained with reference to FIG.

Figure 2 (C) - (Jl indicates the output of each solid-state imaging device operated with light sources of different brightness, and the output of the solid-state imaging device operated with the light source with the highest brightness is shown in the figure (
(d) in the same figure, (
81, (f), (cap..., (j)).

In the case of the same figure (C), the potential of the capacitor 9 reaches a "high level" due to the charge accumulated in the photodiode 1 at time Δt, and from time t1, the pulse synchronized with the vertical charge transfer pulse is activated by the next reset pulse. It is output from the AND gate element 11 until it is input. At this time, a signal "7" is sent from the next stage pulse counting circuit 12 to the binarization circuit 12.
3, and the binarization circuit 13 outputs a signal "111".

Next, in the case of the same figure (dl), the potential of the capacitor 9 does not reach the "high level" only with the charge accumulated in the photodiode 1 during the first Δt time, and the charge accumulated in the photodiode 1 during the next Δt time does not reach the "high level". In other words, the potential of the capacitor 9 reaches the "high level" for the first time due to the charges accumulated in the photodiode l during the time 2Δt, and the vertical charge transfer starts from time t2. A pulse synchronized with the pulse is output from the AND gate element 11 as in the case of FIG.
The signal “6” is output from the next stage pulse counting circuit 12.
It is output to the digitization circuit 13, and is output as “110” from the binarization circuit 13.
” is output.

In the case of (e) in the figure, a pulse is output from the AND gate element 11 from time t3, and the pulse number circuit 12 outputs "5".
”, and the binarization circuit 13 outputs 101”.
This signal is output.

Similarly, in the case of (f) in the figure, the pulse counting circuit 12 outputs "4" and the binarization circuit 13 outputs "100". Similarly, (g) and (t+) in the same figure.

In the case of (1), U), “3” is output from the pulse counting circuit 12.
”.

"2", '"1", and "0" are outputted, and each is binarized by the binarization circuit 13 to 011.010.
．． 001,000 is output.

In this way, according to this embodiment, the optical signal is converted into pulses whose number corresponds to the amount of irradiated light near the photoelectric conversion element and is counted, so that the optical signal can be converted into a digital signal on the solid-state image sensor. This has the effect of making it possible to convert the signal, making it resistant to noise, and eliminating the need for an amplifier that requires a complicated design.

In the above embodiment, the output of the binarization circuit 13 is a 3-bit signal, but the number of bits can be easily increased by increasing the number of vertical charge transfer pulses between each reset pulse. Specifically, if the number of vertical charge transfer pulses is 63, it will be 6 bits, and if it is 255, it will be 8 bits.

【Effect of the invention〕

As described above, according to the solid-state imaging device according to the present invention,
Since the charge transferred from the photoelectric conversion element is converted into a digital signal corresponding to the optical signal, it is resistant to noise and has the effect of eliminating the need for a signal processing circuit using a pre-stage amplifier that was previously required. .

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a solid-state imaging device according to an embodiment of the present invention, FIG. 2 (al to (j)) is a diagram showing the relationship between input pulses and output of the device of FIG. 1, and FIG. 3 is a diagram of a conventional solid-state imaging device. 1 is a configuration diagram of a solid-state imaging device. In the figure, 20 is a photoelectric conversion element, 1 is a photodiode, 3 is a MOS switch transistor, 30 is an optical signal digitizing means, 9 is a capacitor, 11 is an AND gate element, 12 is a pulse counting circuit, 13 is a binarization circuit, 14
is a MOS reset transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A solid-state image sensor in which photoelectric conversion elements are arranged, each consisting of a photodiode that accumulates charges according to an optical signal and a MOS switch transistor that transfers the charges, and a sensor that corresponds to each of the photoelectric conversion elements. Provided above MO
A solid-state imaging device comprising: optical signal digitizing means for converting the charge transferred by the S switch transistor into a digital signal corresponding to the optical signal. (2) The solid-state imaging device according to claim 1, wherein each of the optical signal digitizing means is provided near each photoelectric conversion element on the solid-state imaging device. (3) The optical signal digitizing means includes a capacitor for sequentially accumulating the charge transferred by the MOS switch transistor, a MOS reset transistor for resetting the charge accumulated in the capacitor, and a MOS reset transistor for resetting the charge accumulated in the capacitor. a gate element that outputs the same number of pulses in synchronization with a vertical charge transfer pulse applied to the gate of the MOS switch transistor; a pulse counting circuit that counts the output of the gate element; and a pulse counting circuit that binarizes the output of the counting circuit. 2. The solid-state imaging device according to claim 1, further comprising a binarization circuit.