JPS61214537A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to micronize a semiconductor device as well as to enhance the integration thereof by a method wherein a first SiO2 film, a first Si3N4 film and a second SiO2 film are laminated on the specific region of the Si substrate, and after that, the second SiO2 film is covered with a second Si3N4 film and a third SiO2 film, an anisotropic etching is performed on the third SiO2 film, whereby the second Si3N4 film is made to expose, an aperture is provided, the second SiO2 film is removed, a selective oxidation is performed and after a flattening is performed, the first Si3N4 film is removed. CONSTITUTION:An SiO2 film 2, an Si3N4 film 3 and an SiO2 film 4 selectively provided on a P-type Si substrate 1 are covered with an Si3N4 film 5 and an SiO2 film 6, and an anisotropic etching is performed on the SiO2 film 6 to expose the Si3N4 film 5, an aperture is provided and parts of the film 6 are left on the side surfaces. After B implanted layers 7 are formed, the exposed Si3N4 films 6 are etched away, successively the SiO2 films 4 and 6 are removed. Then, when a selective oxidation is performed on the parts of 10 using the Si3N4 film 3 and residual Si3N4 films 8 and 9 as masks, an encroachment of bird's beak onto the element regions is prevented by the width part of each film 8 and the height part of each film 9. An etching is performed on parts of the oxide films 10, which are higher than the surface of the substrate, and the oxide films 10 are formed into layers 10a. The rest is performed according to a well-known process, whereby the semiconductor device, NchMOSLSI, is completed. According to this constitution, a highly reliable element isolation can be performed as the mask pattern is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to integrated circuits (ICs), such as large scale integrated circuits (L
The present invention relates to a method for manufacturing semiconductor devices such as SI), and particularly to a method for isolating elements that enables high integration.

[Background technology]

In an IC 1, for example, an LSI, a large number of elements are built into one chip to form a circuit, so each element must be electrically insulated and separated. The element isolation method currently commonly used in the LSI manufacturing process is LOCO5 (
Local Oxidation of 5ilicon
) method, which utilizes the high oxidation resistance of Si and N4 films to selectively oxidize a silicon nitride (Si, N,) film as an oxidation mask. This method is used, for example, in the Philips Research Report (Phili
ps Research Reports) 25.11
8 (1970) etc.

In the case of this method, when Si and N4 films are directly deposited on a silicon (Si) substrate and selective oxidation is performed, S
A defect occurs on the i-substrate. Therefore, generally pad 5iO
A method has been used to alleviate stress by inserting a thermal oxide film (Sin film) called 1 between the Si, N film and the Si substrate.

Therefore, a pad 5iO1 is formed on the Si substrate, a 5ilN4 film is further formed on it, this 5isN film is patterned in the shape of the element region, and selective oxidation is performed using the remaining 5ilN4 film as a mask to field oxidize the element isolation region. Forms a film.

However, during this selective oxidation, oxidation progresses in the lateral direction through the pad 5ift, so the oxide film digs into the element region from the element isolation region in the shape of a bird's beak (a so-called bird's beak phenomenon occurs.The length of this bird's beak is Although it varies depending on the thickness of 5101g, 5ilN, film thickness, and oxidation conditions, it is usually about 0.5 to 0.8 μm.

Due to this bird's beak phenomenon, the width of the element area of the LSI is reduced by the bird's beak, and therefore the effective area of the element area of the LSI' is reduced accordingly. Moreover, as the degree of integration of LSI increases and the width of the element region becomes 3 to 2 μm or less, the influence of bird's beak becomes significant and becomes a major hindrance to improving the degree of integration. For example, in a standard dynamic RAM, if the minimum line width (mask design value) of the element region and element isolation region is 2 μm, the integration density is 1.3×106 cells/I:M2 when no bird's beak occurs. On the other hand, when o, spm bird's beak occurs, 9X
down to 10' cells/cm2.

Furthermore, in the element isolation region, approximately half of the thick field oxide film is not buried in the Si substrate but is formed on the Si substrate, so that the difference in level between the element isolation region and the element region is This is a big problem in achieving higher integration of LSIs.

[Purpose of the invention]

An object of the present invention is to provide a novel device isolation method in which the bird's beak does not dig into the device region, and therefore the difference in dimension conversion from the mask pattern (photoresist pattern) is zero.

Another object of the present invention is to provide a novel device isolation method that can significantly reduce the level difference between the device region and the device isolation region and achieve planarization.

Another object of the present invention is to provide a semiconductor technology that enables even higher integration of ICs such as LSI and VLSH.

The above and other objects and novel features of the present invention include:
It will be clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, after three layers of a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film are sequentially deposited and patterned into the shape of an element region, the side surfaces of the three layers and the surrounding silicon substrate are deposited. A second silicon nitride film is formed on the surface of the first silicon nitride film. When forming an element isolation region by oxidizing the region not covered by the second silicon nitride film, the second silicon nitride film is used as a stopper to prevent bird's beaks from entering the element region, and the formed element isolation region By etching the silicon oxide layer to approximately the position of the silicon substrate surface or a position close to it, the difference in level between the element region and the element isolation region can be significantly reduced, and planarization can be achieved, thereby facilitating miniaturization and high integration. It is something that will be realized.

〔Example〕

FIGS. 1(a) to (i) show N-channel MI according to the present invention.
An embodiment of the SLSI manufacturing method is shown, and the second parts (a) and (bl) show modifications of the main steps in FIG. 1.The present invention will be explained below using FIGS. I will explain.

First, a P-type Si substrate is prepared, and its surface is thermally oxidized to form the first S t Ot film 2 . Furthermore, a first Si@N4 film 3 and a second S
An iOs film 4 is deposited as shown in FIG. 1(a).

The thicknesses of the 5iOy film 2, 5isN film 3, and the 5isN film 3 are preferably set to such a thickness that crystal defects will not occur in the silicon substrate during field oxidation. For example, the Sing film 2 is heated to 50 O
A. It is preferable to set the 5ilN4 film 3 to about 1500A. The role of the 5iO1 film 4 formed by the CVD method and the reason for setting the film thickness will be clarified in the explanation of FIG. 4(d).

Next, the first 5iQz film 2. The three-layer film of the first 5isN film 3 and the second Sin film 4 is patterned into the shape of the device region as shown in FIG. At this time, the three layers may be etched successively by the RIE method, or the 5iO1 film 4 and the Si, N4 film 4 may be etched by the RIE method and then etched by the S.
i. The 5ift film 2 may be wet etched using the N4 film 3 as a mask. Note that it is desirable that the etching shape be vertical, and this can be achieved more easily than by using the RIE method.

In the present invention, since the bird's beak is small, there is no need to take the length of the bird's beak into consideration when patterning this element region.

The dimensions of the element area actually used are sufficient.

Next, a relatively thin second 5ilN4 film 5 and a third Sin film 6 are deposited by CVD as shown in FIG.

The thickness of the 5ilN4 film 5 can be appropriately set within a thick range to prevent defects from occurring during later field oxidation.

In this case, Si 3 N, the film is made of Si in a nitrogen atmosphere.
Although it is possible to form the S l s N4 film by combining it with the substrate, the S l s N4 film formed by this method does not have a sufficient film thickness and cannot sufficiently prevent the 5iO1 film from entering the element region. Since it cannot be used as a product, it is preferable to deposit it using the CVD method.

Thereafter, the 5ift film 6 and the Si@N4 film 5 formed by the CVD method are etched by the RIE method. Since the RIE method is a highly directional etching method, the CV of the side surface of the stepped portion is
The D Si Ot film 6 (6a) remains without being etched. Using this 5iQ1 film 6a as a mask, Si, N
By etching the 4 film 5, a thin 55NJI7 with a certain width remains around the first Si3N4 film 30 which is patterned in the shape of the device region.
N□column 7 (hereinafter referred to as Off-Sera) Si, N, film 7. ) covers the side surface of the pad Si ion film 2 and is directly attached to the Si substrate, forming a structure as shown in FIG. 2(d). The offset 5ilN and the width of the film 70 can be controlled by the C V D Si Os film 6a remaining on the sidewalls of the pattern. In other words, the 5iQ1 film 6 shown in FIG.
It can be controlled by the thickness. For example, S iQ
1 Thickness of film 6 (thickness is off-sera) Si, N4 film 70
It is possible to form it with a wide width. Also, the second SiQ
, membrane 4 also plays an important role. In other words, in order to coat the pattern sidewall with the 5i02 film 6a with good reproducibility (remaining pattern), the stepped portion must have a sufficient height, and the 5ift film 4 plays the role of increasing this height. In other words, Sin, film 6 (6
In order to retain a) with good reproducibility, this 5iQ1 film 4. si
,N.

Membrane 3. It is necessary to set Sin and the film 4 so that the sum of the thicknesses of the pad Sin and the film 2 is at least thicker than the thickness of the film 6. As will be described later, this 5iO1 film 6
Thickness of a, that is, width of Si@N4 film 70 and 5ilN, film l
The height of O can prevent the bird's beak from entering the element region. After the above steps, boron ions (B+) for a channel stopper are implanted with the Sin film 6a remaining on the sidewalls of the pattern to form a boron implanted layer 8. It goes without saying that the thickness of the KSiOt film 4 should be selected so that the element region is not affected by this ion implantation. Note that the etching of the second 5ilN4 film 5 may be performed continuously with the reactive ion etching of the 5ift film 6, or the etching of the 8i0. membrane 6
Etching may be performed by wet etching using (6a) as a mask. Further, the ion implantation for the channel stopper may be performed before or after etching the Si, N4 film 5.

Next, the SiO* film 4, sio, and film 6a are removed by wet etching as shown in FIG.
, Na film 3 and off-cella) SilN, selective oxidation is performed using the film 7 as a mask, and a field 5iO1 film 9 is formed in the element isolation region.
is formed as shown in the same figure (f). At this time, the presence of the offset S i HN4 film 7 can prevent the bird's beak from digging into the element region. In addition, at the end of the element region, a second Si3N4 film 1 is formed on the sidewall of the pattern.
0 exists vertically and has a thickness of 5ilN, which is substantially equivalent to the height of the first nitride film, and is equivalent to having a film directly below it, so oxidation in the lateral direction is constant even in this part. The period can be stopped.

In other words, in the present invention, the field sto
It is possible to prevent the W film 9 from entering the element region.

Furthermore, the thicker the offset Si, N4 film 7 is, the gentler the step shape of the field Sin, film 9 becomes.

That is, the step shape of the field 5iQ1 film 9 can be controlled by the thickness of the offset S l s N+ film 7. Although the offset 5ilN4 film 7 is directly attached to the Si substrate 1, no crystal defects occur because the width is narrow and the film thickness is set thin. In this embodiment, the penetration of the bird's beak into the element region is zero, that is, the difference in dimension conversion from the mask is zero, and a good cross-sectional shape can be obtained.

Next, as shown in the same figure (gl K, Si, N4 film 3 + 7
．． 10 as a mask, an anisotropic etching method such as RI
The field Si0g film 9 is etched from approximately the surface of the Si substrate 1 to approximately the height of the 5iO1 film 2 using the E method. The remaining field Sin and film 9a are substantially buried in the Si substrate 1.

After this, as shown in the same figure (h) (SilN4 film 3, 7.10
is removed by wet etching. As a result, a substantially flat element isolation region is formed.

Next, the first 5iO1 film 2 is removed by etching.

At this time or in subsequent normal processing steps (for example, gate formation), most of the field Sin and film 9a above the surface position of the Si substrate 1, including the protrusion 9b, are etched and flattened. At the same time, the level difference between the element region and the element isolation region is eliminated, and the entire surface is flattened.

Then, by following the well-known process, N-channel MO8LSI
is prepared as shown in the same figure (i). In the same figure (i), l] is a gate oxide film, and gate electrodes 13a and 13b constitute the source and drain regions, respectively -f6N"
Diffusion layer, 14 Interlayer insulating film using CV D Si Ot film or phosphorous silicate glass (PSG) film, 1
5 is a contact, and 16 is a pad page membrane.

In the MO8LSI manufactured according to this example, element regions and element isolation regions can be obtained according to the mask dimensions. Furthermore, it is possible to eliminate the protrusion of the element isolation region and remove the portion of the field 5iQ1 film 9 that exists above the surface of the Si substrate 1, and is also substantially flattened, so that the separation between the element region and the element isolation region can be removed. There are almost no steps and the entire surface is flattened. For this reason, the MO8L after this
Patterning accuracy in the SI manufacturing process can be improved. Therefore, high integration becomes possible.

〔effect〕

1. By forming an offset 51 mN4 film, it is possible to prevent the bird's beak from digging into the element region.

2. At the edge of the element region, the Si3N4 film exists vertically on the sidewall of the pattern, and the Si3N4 film has a thickness substantially corresponding to the height of the Si3N4 film.
Since this is equivalent to directly attaching the i,N film, lateral oxidation can be prevented in this part as well.

3. The step shape of the field Si ion film can be controlled by adjusting the offset Si, N, and film thickness.

4. Off-Cera) The Si, N, film 7 is directly attached to the Si substrate, but due to its narrow width and thin film thickness, no crystal defects occur.

5. Since the second 5ilN4 film is formed by the CVD method, it can be made thicker than the Si, N4 film formed by nitriding silicon, and therefore the above 1 to 4 can be carried out more effectively. I can do it.

6. The sum of the thickness of the first 5iO1 film, the thickness of the first 5i3Na film, and the thickness of the second SiOx film is the third 5iO1 film.
By determining the thickness of the second Si0g film so that it is thicker than the thickness of the y film, the contents of 1 to 4 above can be effectively
xO7set) SilN film can be formed.

7. In an integrated circuit, especially an LSI, produced according to the present invention, the element area matches the mask dimensions according to 1 to 6 above.

An element isolation region can be obtained.

8. By etching the silicon oxide layer in the element isolation region that exists above the surface of the silicon substrate, the surface of this silicon oxide layer can be flattened, and the level difference between the element region and the element isolation region can be almost eliminated. (The whole surface can be flattened.)

9. The level difference between the element region and the element isolation region can be almost completely eliminated, and the entire surface can be flattened, which improves the burr patterning accuracy in the subsequent manufacturing process of semiconductor devices, especially LSI. can.

10. The above 7 to 9 enable high integration in LSI.

Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Not even. For example, FIG. 1(g) in this example.

In (h), the field 5iO1 film 9 is etched by an anisotropic etching method (for example, RIE method), and then the field 5iO1 film 9 is etched.
Although the i6N4 film 3.7.10 is etched, the following method is more effective. That is, the field 5iO1 film 9 was etched by anisotropic etching, for example RIE, to a position approximately at the height of the first Sio film 2, and a heptonic acid-based etching solution was further used for the remaining field 5iO1 film 9a. Wet etching is performed to etch the field 5iO1 film 9a to approximately the surface of the Si substrate 1.

At this time, the field S io in the lower part of the Si3N4 film 7
.

5ilN is applied to the protruding portion 9b of the film 9a, and stress (
Because of the applied stress, the etching speed of the protruding portion 9b is faster than that of other portions. When the etching to the above-mentioned position is completed, the protruding portion 9b is etched as shown in FIG. 2(a). Therefore, the remaining field Sin
, the film 9c is located approximately above the surface of the Si substrate 1.
The o1 film 9a is etched and its surface is flattened, and the field Sio and film 9c are almost buried in the surface of the Si substrate 1. Next, Figure 1 (hl
Si, N, film 3.7. When the IO is etched, it becomes as shown in FIG.
is created as shown in FIG. 1(i). Doing this is more effective than the case of this embodiment (FIG. 1).

[Application field]

In the above explanation, the invention made by the present inventor will be mainly explained in relation to N-channel MI, which is the field of application that formed the background thereof.
Although the case where the present invention is applied to an SLSI semiconductor device has been described, it is not limited thereto (for example, it can be applied to a P-channel MISLSI semiconductor device, a complementary MISLSI conductor device, a bipolar LSI semiconductor device, etc.). It can be applied to any technology that forms an insulating film by oxidation.

□

[Brief explanation of the drawing]

1(a) to 1(i) are cross-sectional views showing the main steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention. FIGS. 2(a) and (b) are the main steps of FIG. It is a process sectional view showing a modification of 1... Si substrate, 2... First 5ift film, 3...
・First Si, N4 film, 4... Second 5i01 film, 5
...Second 5iIN4 film, 6.6a = third 5iQ1
Film, 7...Offset Si, N4 film, 8...Boron implantation layer, 9 #9 a +90 is field 5iQ
1 film, 10...second 5ilN. Vertical remaining part of the film, ]]...Gate oxide film, 12
...gate electrode, 13a, 13b...N diffusion layer,
14... Interlayer insulating film, ]5... Contact, 16.
... Pudge Page eye membrane. ””＋＋−− Figure 1 Figure 1 Figure 2 ((L) (b)

Claims (1)

[Claims] 1. A step of forming three layers of a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film on the surface of a silicon substrate, and a step of etching three layers, a step of depositing two layers of a second silicon nitride film and a third silicon oxide film over the entire surface, and a step of depositing the third silicon oxide film on the surface of the silicon substrate. a step of removing the second silicon nitride film using an anisotropic etching method until the surface of the second silicon nitride film is exposed; a step of etching the exposed second silicon nitride film until the surface of the silicon substrate is exposed; a step of removing the second and third silicon oxide films; a step of oxidizing the silicon substrate surface using the first and second silicon nitride films as masks to form a silicon oxide layer as an element isolation region; etching the silicon oxide layer in the element isolation region located substantially above the surface of the silicon substrate using the first and second silicon nitride films as masks; A method for manufacturing a semiconductor device, comprising a step of removing. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second silicon nitride film is formed by a vapor phase chemical reaction method. 3. The sum of the thicknesses of the three layers of the first silicon oxide film, the first silicon nitride film, and the second silicon oxide film,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the third silicon oxide film is greater than that of the third silicon oxide film. 4. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein anisotropic etching is used in etching the silicon oxide layer in the element isolation region. 5. When etching the silicon oxide layer in the element isolation region described above, the silicon oxide layer is removed by anisotropic etching to approximately the height of the first silicon oxide film, and then wet etching is performed to remove the silicon oxide layer. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon oxide layer is removed to approximately the surface of the silicon substrate.