JPS61214297A - Leak current sense circuit - Google Patents

Abstract

PURPOSE:To set an optimum refresh operating allowance without being influenced by the change of the threshold of a transistor by a change of a process by giving two types of potentials to two sets of capacitors forming a leak monitor circuit together with a transfer gate. CONSTITUTION:The reduction below the predetermined value of the voltage of the joint N3 of a leak monitor circuit 11 similar to a RAM consisting of capacitors C1, C2 impressed with a boosted voltage Vp, the respective voltage Vb and an N channel Q2 of a transfer gate connecting to the P channel Q1 of a threshold voltage VTP is detected by the precharge discharge type inverter 12 of a P channel Q3, an N channel Q4 and the like. When a boosted voltage Vp is impressed to the joint N3 to set an optimum refresh operating allowance, an allowance voltage Vmgn becomes a value satisfying equation I and non- related to the threshold voltage of the transistor. Accordingly, the optimum refresh operating allowance can be set without being influenced by the change of the threshold the N, P channel transistors by the change of a process.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory device, particularly a dynamic WRAM.
The present invention relates to a leakage current sensing circuit used in a refresh circuit of (random access memory).

[Technical background of the invention]

Some of the recent dynamic RAMs have an automatic refresher circuit for automatically performing a refresh operation mounted on the memory chip to make usage and peripheral circuits more convenient.

This automatic refresh circuit has, for example, an oscillator 81 and a fresh address counter 82 as shown in FIG. 8, and automatically sets a refresh address to perform a refresh operation when the memory is not performing a normal operation. ing. In this case, if the leakage current of the memory cell is not taken into consideration in the refresh operation, the current consumption of the refresh circuit will become larger than necessary. In other words, the above leakage current increases as the temperature rises, so in order to perform automatic refresh operation over the entire temperature range, it is necessary to set a short Kairi Thresh. This is because it must be set to a period.

In view of these circumstances, in order to reduce the power consumption required for refresh, 1. A completely automatic refresh type MOS storage device that controls refresh operations to be performed automatically at the maximum necessary cycle was developed in Japanese Patent Application Laid-Open No. 59-9 -5629
This is proposed in Publication No. 1. In addition, automatic refresh has lower power consumption compared to this MOS storage device.

The control circuit is a patent application filed in 1972 by the applicant of this application.
FIG. 9 shows a circuit according to an embodiment of the circuit proposed in the No. 754 application. The basic operation of these automatic refresh methods is to detect that the holding voltage of the capacitor in the leak monitor circuit has fallen below a predetermined value,
It controls the initiation or intermittent interval of refresh operations. In addition, in FIG. 9, the leak monitor circuit 90 has the same configuration as the memory cell, and has one memory holding capacitor C and one transfer boot Q connected in series. 9I is a recharge-discharge type inverter.

By the way, if the charge charged in the capacitor C of the leak monitor circuit 90 is inappropriate, the time (leak time) until the holding voltage of the capacitor C falls below a predetermined value is monitored by the memory cell. It cannot be said that this accurately reflects the actual leak time. In view of this point, a specific example for appropriately charging the capacitor of the leak monitor circuit was proposed in Japanese Patent Application No. 1977-262202 "Leak Current Sense Circuit" filed by the applicant of the present application. ing. This leak current sensing circuit is as shown in FIG. 10, and includes a leak monitor circuit 100 and a precharge circuit that detects when the holding voltage of the monitoring capacitor C of this leak monitor circuit 100 has fallen below a predetermined value.・Discharge type inverter 1
01, VDD power supply and the leak monitor circuit 1 0 0
The transformer 77f-} (MOS transistor) is connected between the control terminal of the transfer gate 102,
103 and transfer canopys 104 and 105, a charge transfer unit 106 for transferring charging pulses,
Transfer r-) of the leak monitor circuit 100
A discharging transfer gate 107 is connected to the control end of the Q and discharging the charge of the transfer capacitor 105 at a predetermined timing. In this circuit, the charge transfer section 106 transfers l''-to 102,1
Since the voltage and width of the charging pulse applied to the leak monitor circuit 100 can be adjusted depending on the timing of the driving pulse applied to each control terminal of the discharge transfer gate 107 and the discharge transfer gate 107, the sensing operation margin can be adjusted to an optimum value. Can be set to In this case, when detecting the leakage time by the precharge/discharge inverter 101, the threshold voltage VAN of the N-channel transistor 1090 inserted between the P-channel transistor 108 and the VDD power supply and whose drain and gate are connected together, and the leakage Since the threshold voltage VTN of the transfer gate (N-channel transistor) Q of the monitor circuit 100 is canceled out,
This eliminates dependence on threshold fluctuations of N-channel transistors due to process changes.

[Problems with background technology]

However, in the above leakage current sensing circuit, the threshold voltage V? of the P channel transistor 108 in the precharge/discharge type inverter 101 for detecting leakage time? There is a problem in that P depends on process changes and the leak time detection operation is affected by the variation in VTP.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides an N-channel transistor using process changes.

The present invention provides a leakage current sensing circuit that can set refresh and operating margin to optimal values without depending on threshold voltage fluctuations of each P-channel transistor.

[Summary of the invention]

That is, the leak current sensing circuit of the present invention uses a circuit in which a first and second capacitor are connected to a transfer gate as a leak monitor circuit, and applies a pulse voltage to the control terminal of the transfer gate at a predetermined timing, A certain potential Vb is applied in advance to one end of the first canister, and the potential Vp is applied to one end of the second canister at a predetermined timing. The present invention is characterized in that a precharge/discharge board inverter detects that the voltage at the connection point between the second capacitor and the transfer gate has fallen below a predetermined value.

With this configuration, two capacitors and two types of potential V
By using b and Vp, the amount of increase in potential at the connection point between the second capacitor and the transfer f-) before and after the put-out (s7res, operating margin) can be set to the optimum value, and this operating margin is limited to the N channel due to process changes. transistor, P
It is not affected by fluctuations in the threshold voltage of the channel transistor.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. The leakage current sensing circuit shown in FIG. 1 is provided in an automatic refresh control section of a dynamic RAM, and Q□ to Q4&t MOS-FETs (insulated date field effect transistors), C□ and C2 are connected to the first.
Second Cano'? These elements form a leak monitor circuit 11 and a precharge/discharge type inverter 12. That is, in the leak monitor circuit 11, the source of the first conductive type (P channel in this example) transistor is connected to the VD'D power supply, the drain and gate are connected to each other, and the second conductive type (P channel in this example) is connected to the transistor. In the example, the capacitor C is connected to the drain of the transistor Q2 (N channel in the example), and the source of the transistor Q2 is connected to the capacitor C.
D. Each end of C2 is connected. Here, the above N
Channel transistor Q, and
, C1 are configured to have characteristics equivalent to a memory cell having a one-transistor, one-capacitor configuration in a dynamic RAM.
The y-to (control end) is transferred to the second node N3. The source is called a third node Ns, the other end of the capacitor C□ is called a fourth node N4, and the other end of the capacitor C1 is called a fifth node N. In the inverter 12, the source of a P-channel transistor Q for recharging is connected to a VDD power supply, the drain is connected to the drain of an N-channel transistor Q4 for discharging, and the source of this transistor Q is connected to a VaS power supply (ground potential). )
It is connected to the. Here, the gate of the P-channel transistor Q3 is connected to the third node N3, and the drain interconnection point (output node) of the transistor Qs=Q4 is connected to the sixth output node N, the date of the transistor Q4. is referred to as a seventh node N.

Next, the operation of the leakage current sensing circuit will be explained with reference to FIGS. 2 and 3. The potential of the first node N is always set to VDD "" vT by the transistor Q1.
It is P. Here, VTP is the threshold voltage of a P-channel transistor. In advance, the second node N is given a ground potential, the fourth node N4 is given a Vb potential, and the fifth node N is given a vp potential (
Vp>Vb), the transistor Q is in an off state. At time t, the V& potential is applied to the 20th node N, and the transistor Q is turned on. At this time, the potential of the third node N3 does not depend on the threshold voltage VTN of the N-channel transistor Q, since the 20th node N□ is gated to the Vp potential, and is at the same potential as the 10th node N1. VDD -'/TP, and C1((VDn-Vtp) Vb) p C2(
(Vno-VTP)-v, ) is often accumulated.

Time t! , the second node N2 changes from the v1 potential to the ground potential, and the transistor Q becomes off. At time t3, the potential of the fourth node N4 changes from Vb to v
Gate to p. At this time, the electric charge in the capacitors C, , C, is conserved, so that the potential of the third node N, increases.

If this increase is expressed as vmgn, then the third node N
s is 'VDD -VTP + Vmgn at the above time t3
become.

On the other hand, the seventh node N is supplied with the VDD potential until time t, and becomes the ground potential at time t. Therefore, the discharge transistor Q4 of the inverter 12 is in an on state until time t3, and during this time, the discharge transistor Q is mistakenly turned on and the sixth node (output node) N , leak time sense is avoided to output 4 ruses. Note that the time from time t8 to time t is set to be very short, and it is possible to ignore the leakage of the charge of the canon, l C1e C*, during this time.

From the time t, leakage of charges from the four-stage transistor C1, C starts, and the potential of the third node N3 gradually decreases,
When this potential becomes VDD + VTP, the inverter 12
The precharge transistor Qm is turned on, and the sixth precharge transistor Qm is turned on.
The potential of the node (output node) N rises from the ground potential up to that point to the VDD potential, and leak time sensing can be obtained.

In the above operation, since the potential VDD-VTp of the third node N before being put is equal to the potential VDD-VTP during leak time sensing, the potential of the third node N,
The difference between the potential VDD"""l'?P before the pull-out and the potential VDD -VTp +Vmgn after the pull-out,
The potential increase Vmgn before and after the boot is refreshed,
There is plenty of room for movement.

Here, the refresh operation margin Vmgn will be determined with reference to Fig. 3. In other words, the monitoring capacitors C, , C, before the output have the above-mentioned throughput Ct ((VDD-Vtp)-Vb)Cm ((Vn
Charges are accumulated at o-Vtp)-vp). On the other hand, immediately after the put, (Cs +Cs) ((VDD -VTII +Vm
A charge of gH) -Vp) is accumulated. Since the charges of the capacitors C1 and C are conserved before and after the output, the following equation holds true.

Ct ((VDD-VTP)-Vb)+C*((
VDn-Vtp)+Vp)=(C1+C!) (
(VDn-VTp+Vmgn) -Vp )・°・V
= −(Vp −Vb)mg” c1+c
.

As is clear from the above equation (1), the refresh operation margin does not depend on changes in the N-channel transistor threshold voltage VTN e P-channel transistor threshold voltage vTP due to process changes, and the
1, C, and the fourth node N4. It is possible to set the applied voltages Vb and Vp of the fifth node N to an optimal value. In this case, the optimal value is the amount necessary to charge the monitoring capacitors C and C8 so that the leak current sensing circuit can accurately sense the monitor time before the actual leak time in the memory cell. It is a value.

The leakage current sensing circuit shown in FIG. 4 shows a modification of the circuit shown in FIG. It is designed to boot to the VDD, and the same parts as in FIG. 1 are given the same reference numerals. According to this circuit, even if the VDD power supply voltage changes suddenly, leak time sensing is prevented by this operation.

The leak current sensing circuit shown in FIG. 5 shows yet another modification of the circuit shown in FIG.
Nine N-channel transistors Q, whose gates and sources are connected to each other between 1 and VS and the power supply, are additionally connected, and an N-channel transistor Q is connected between the sixth node N6 and the V□ power supply.
- is additionally connected, and this transistor Q,? -) to VD
It is connected to the D power supply, and the same parts as in FIG. 1 are given the same reference numerals. In this circuit, since the transistors Qs-Qs with small conductance are provided, when the respective nodes NL and N are in a floating state for a long time, the node N is caused by the Sarasressian island hold leakage of the transistors Ql-Ql.

It is possible to prevent the potential of N from rising to VDD. In addition, the above-mentioned transistor Q with small conductance,
, Q may be replaced with a high resistance.

Furthermore, the leakage current sensing circuit of FIG. 6 shows another embodiment of the present invention, and is different from the circuit of FIG. Of these, the connection of the transistor Q for the capacitor C connected to the fourth node N4 for date (transformer 77ff-) was changed from the source side to the drain side, and the above-mentioned transfer gate transistor Q
The boot operation is carried out while transistor 8 is in the on state, except that the on period of the transistor Q is different. The voltages at each node in this circuit are as shown in FIG. 7, and the following operation is different from that of the previous embodiment. In other words, at time t, the 40th
The auto of the node N4 is performed and the first node N1 is at the previous potential VDD-V! .

When the voltage rises above, transistor Q8 turns off and the first
There is no charge replenishment to the node N of . At this time, the third node N is connected through the on-state transistor Q.
, the potential of is v! ngn increases, and time 1. After the transistor Q2 is turned off, the monitoring capacitor C is turned off.
3 leak will start. In the leak monitor circuit 61, the transfer gate Qs and the capacitor C1 have the same structure as a memory cell.

Therefore, in this circuit as well, the operating margin can be set to an optimum value without being affected by fluctuations in the threshold voltages of the N-channel transistor and the P-channel transistor, as in the previous embodiment.

Furthermore, in the circuit of FIG. 6, the VDD power supply potential is applied to the fifth node N, or the VDD power potential is applied to the tenth node Ni and the sixth node, as in each modification of the circuit of FIG. It is possible to implement a modification such that a MOS transistor is additionally connected to each of N and N.

〔Effect of the invention〕

As described above, according to the leakage current sensing circuit of the present invention, two capacitors are used in the leakage monitor circuit, and the potential t at one end of one capacitor is connected at a predetermined timing to detect a pN channel transistor due to a process change. , even if the threshold voltages of the P-channel transistors vary, the sense operation margin in the automatic refresh circuit can be set to an optimal value without being affected by the variation. Further, by applying the power supply potential as the potential at one end of the other of the two capacitors, it is possible to prevent an erroneous sensing operation from occurring when the power supply voltage changes suddenly.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the leak current sensing circuit according to the present invention, FIG. 2 is a waveform diagram showing voltages at various parts of the circuit in FIG. 1, and FIG. J? 4 and 5 are circuit diagrams each showing a modification of the circuit in FIG. 1, and FIG. 6 is a diagram showing another embodiment of the present invention. A circuit diagram showing an example, Figure 7 is a waveform diagram showing voltages at various parts of the circuit in Figure 6,
FIG. 8 is a configuration explanatory diagram of an automatic refresh circuit in a dynamic RAM, FIG. 9 is a configuration explanatory diagram showing a conventionally proposed automatic refresh control circuit, and FIG. 10 is a circuit diagram showing a conventionally proposed leakage current sensing circuit. It is a diagram. 11.61...Recycle monitor circuit, 12...Precharge-discharge type inverter, Q1-Q,...M
OS Transistor, C,, C, -- Capacitor, N
1 to N, ... Node. Applicant's representative Patent attorney Takehiko Suzue s1 Figure 3 Figure 4m! l 1jhn' Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (5)

[Claims] (1) It is configured using a transfer gate and two capacitors in order to monitor leakage of memory cells that require a refresh operation, and the potential at one end of the first capacitor of the two capacitors is set at a predetermined level. A leak monitor circuit that is booted according to the timing, and a precharge circuit that detects that the voltage at the connection point between the transfer gate and the second capacitor of the two capacitors in this leak monitor circuit has become below a predetermined value. A leakage current sensing circuit characterized by comprising a discharge type inverter. (2) The leak monitor circuit includes a first MOS transistor of a first conductivity type whose source is connected to a V_D_D power supply and whose drain and gate are connected to each other;
A second MOS transistor of a second conductivity type, the transistor and the drain of which are connected to each other, and a pulse voltage is applied to the gate at a predetermined timing; and a first capacitor, each of which has one end connected to the source of the second MOS transistor. and a second capacitor, a potential V_p is applied to the other end of the second capacitor, a potential V_b is applied in advance to the other end of the first capacitor, and the second MOS transistor 2. The leak current sensing circuit according to claim 1, wherein a potential increase from the V_D potential to the V_p potential is applied after the application of the pulse voltage to the gate ends. (3) The leak current sensing circuit according to claim 2, wherein a V_D_D power supply potential is used as the V_p potential. (4) The leak monitor circuit includes a first MOS transistor of a first conductivity type whose source is connected to the V_D_D power supply and whose drain and gate are connected to each other;
a second MOS transistor of a second conductivity type whose transistor and drain are connected to each other and a pulse voltage is applied to the gate at a predetermined timing; a first capacitor whose one end is connected to the drain of the second MOS transistor; a second capacitor having one end connected to the source of the second MOS transistor, a potential V_p is applied to the other end of the second capacitor, and a potential V_p is applied to the other end of the first capacitor in advance. Claim 1, wherein V_b is being applied, and an increase in potential from the V_b potential to the V_p potential is applied during the application period of the pulse voltage to the gate of the second MOS transistor. The leakage current sensing circuit described. (5) The leak current sensing circuit according to claim 4, wherein a V_D_D power supply potential is used as the V_p potential.