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JPS6121100U - Sampling and hold circuit - Google Patents

Sampling and hold circuit

Info

Publication number
JPS6121100U
JPS6121100U JP10298084U JP10298084U JPS6121100U JP S6121100 U JPS6121100 U JP S6121100U JP 10298084 U JP10298084 U JP 10298084U JP 10298084 U JP10298084 U JP 10298084U JP S6121100 U JPS6121100 U JP S6121100U
Authority
JP
Japan
Prior art keywords
sampling
voltage
circuit
fet
rectifier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10298084U
Other languages
Japanese (ja)
Inventor
隆司 石塚
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP10298084U priority Critical patent/JPS6121100U/en
Publication of JPS6121100U publication Critical patent/JPS6121100U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の一実施例を示すものであり、第1図は電
気回路図、第2図は電圧波形図である。 図面中、1は電源トランス、2は整流器、10及び11
は三端子レギュレータIC,12.13はオペアンプ、
14はFET,15はコンデンサ、17は制御回路であ
る。
The drawings show an embodiment of the present invention, and FIG. 1 is an electric circuit diagram, and FIG. 2 is a voltage waveform diagram. In the drawing, 1 is a power transformer, 2 is a rectifier, 10 and 11
is a three-terminal regulator IC, 12.13 is an operational amplifier,
14 is an FET, 15 is a capacitor, and 17 is a control circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] サンプリング時にオンされるFETと、このFETがオ
ンされた時に入力電圧に応じた電圧を保持するコンデン
サと、サンプリング終了後コンデンサに保持された電圧
に基いてサンプリング時の入力電圧に応じた出力電圧を
発生するホールド用オペアンプと、交流電源を直線化す
る整流回路とくこの整流回路からの直流電圧を降圧し且
つ安定化して前記オペアンプの電源端子に供給する定電
圧回路と、前記整流回路の出力電圧が制御電源として供
給されて前記FETのサンプリング動作を行わせる制御
回路とを具備してなるサンプリングアンドホールド回路
A FET that is turned on during sampling, a capacitor that holds a voltage corresponding to the input voltage when this FET is turned on, and an output voltage that corresponds to the input voltage during sampling based on the voltage held in the capacitor after sampling is completed. A hold operational amplifier is generated, a rectifier circuit linearizes the AC power supply, a constant voltage circuit that steps down and stabilizes the DC voltage from the rectifier circuit and supplies it to the power supply terminal of the operational amplifier, and the output voltage of the rectifier circuit is A sampling and hold circuit comprising: a control circuit that is supplied as a control power source and causes the FET to perform a sampling operation.
JP10298084U 1984-07-06 1984-07-06 Sampling and hold circuit Pending JPS6121100U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10298084U JPS6121100U (en) 1984-07-06 1984-07-06 Sampling and hold circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10298084U JPS6121100U (en) 1984-07-06 1984-07-06 Sampling and hold circuit

Publications (1)

Publication Number Publication Date
JPS6121100U true JPS6121100U (en) 1986-02-06

Family

ID=30662370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10298084U Pending JPS6121100U (en) 1984-07-06 1984-07-06 Sampling and hold circuit

Country Status (1)

Country Link
JP (1) JPS6121100U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015397U (en) * 1983-07-13 1985-02-01 株式会社 タカラ doll toy
JPS6136690U (en) * 1984-08-10 1986-03-06 株式会社トミー robot toy
JPS63156692U (en) * 1987-03-31 1988-10-14
JPH01129607A (en) * 1987-10-28 1989-05-22 Burr Brown Corp Insulated amplifier including precision voltage-dutycycle converter and low ripple high band width charge balance demodulator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015397U (en) * 1983-07-13 1985-02-01 株式会社 タカラ doll toy
JPS6136690U (en) * 1984-08-10 1986-03-06 株式会社トミー robot toy
JPS63156692U (en) * 1987-03-31 1988-10-14
JPH01129607A (en) * 1987-10-28 1989-05-22 Burr Brown Corp Insulated amplifier including precision voltage-dutycycle converter and low ripple high band width charge balance demodulator

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