JPS6120868A - Speed signal detecting device - Google Patents

Abstract

PURPOSE:To eliminate the variation in the amplitude of a signal and bias value and to detect with good accuracy by detecting the speed signal which is synthesized by differentiating the sinusoidal wave transmitted from an encoder, with providing a bias correction means and amplitude correction means. CONSTITUTION:Sinusoidal signals A, B are made diatomic with inputting into zero cross compartors ZCA, ZCB, also made to an absolute value with inputting into polarity changeover amplifiers PA, PB. These signals are then inputted into a micro processor muP and a bias correction value and amplitude correction value are calculated. In this case, if the amplitude value of the sinusoidal wave signal is + or -a and the bias value b, the peak values gamma, q of the plus and minus of the signal thereof are detected and the amplitude alpha and bias value beta are found from the sum and difference thereof. Then with inputting into pulse width modulators PWM1A, 2A, 1B, 2B, the pulse width is modulated with the bias correction value and the signals k-n having no pulse sliding are obtd. Since the amplitude vibration and bias sliding are corrected, the variation of signals can be thus eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a speed signal detection device that generates a speed signal from an output signal of an encoder.

(Prior art) Better from an encoder When creating a speed signal by differentiating and synthesizing sinusoidal signals, the signal from the encoder undergoes large temperature changes and changes over time, causing large changes in amplitude and bias values. The signal fluctuates significantly.

(Purpose) It is an object of the present invention to provide a speed signal detection device in which the speed signal does not fluctuate due to fluctuations in the amplitude and bias value of the signal from the EA encoder.

(Structure) The present invention provides a speed signal detection device that detects a speed signal by differentiating and synthesizing sinusoidal signals from an encoder, which is provided with bias correction means and amplitude correction means. The bias correction means and the amplitude correction means perform analog/digital conversion of the sinusoidal signal and perform addition and subtraction using the arithmetic means, and have a duty ratio proportional to the result of the subtraction.

A pulse train is generated by a pulse train generating means and smoothed by a smoothing means. Bias correction is performed by adding the output signal of this smoothing means to the signal before or after the amplitude correction for the sinusoidal signal and before or after the speed signal rendering process. Further, the pulse train generating means generates a pulse train having a duty ratio inversely proportional to the addition result of the arithmetic means, and the pulse train generates a signal before or after bias correction for the sinusoidal signal and before or after speed signal detection processing. Turn on and off to smooth and perform amplitude correction.

If the sinusoidal signal obtained from the encoder has an amplitude range of +L0 and a bias value of ■ as shown in Figure 4, these values can be determined by detecting the positive and negative peak values ■ and ■ of this signal. It can be determined from the sum and difference. That is, ■-(■+■)/2 ■-(O-■)/2. A wave signal can be obtained from the signal obtained from the encoder using the above formula.

FIG. 1 shows an embodiment of the present invention that performs amplitude correction and bias correction based on the above-mentioned principle, and FIG. 2 shows signals of various parts thereof. In general, two signals A and B with a 90° phase difference are often extracted from the encoder in order to produce a rotating direction in the case of a rotary encoder and a reverse direction in the case of a linear encoder.This embodiment deals with this case. This is an example.

Two sinusoidal signals A, B&'! from the encoder. The false code that is binarized in OV is detected by zero-cross comparators ZCA and ZCB, and converted into absolute values by polarity switching amplifiers PA and PB. The output signal C1d of the polarity switching amplifiers PA and PB is sent to the analog/digital converter A in time division by the switches SA and SB.
/D is converted into an analog/digital signal and sent to the microprocessor μP. In addition, the switches SA and SB are turned on alternately, and the output signal of the analog/digital converter A/D and the zero clock signal are
Detect the peak values ■ and ■ for the valley waveforms A and B from the output signals a and b of the I/-tactors ZCA and ZCB, and calculate the amplitude ■ and bias (direction ■ using the above formula, and calculate from this).7. For each sine wave signal A,
℃ calculation for H (Lusse width modulator pWMIA.

Send to PWMZA, PWinIB, and PWM2B.

Pulse width modulator PWM2A for bias correction.

P'WM2B is the microprocessor μP power) and 0) Bias and correction for each waveform A and B (directly (-■,) and
The las width is modulated and the ratio flJ is
Output the Noculus sequences g and h having the duty ratio.

The pulse trains g,'h't'L) (which are positive or negative depending on the sign of the Iass correction value, and are respectively low) are smoothed by filters LPFA and LPFB to become an analog signal '+J. This analog signal i, jfJ
″-original sine wave signal A, BK7] 11 arithmetic circuit Σl,
By performing a calculation using Σ2, t is obtained as a signal with no ias deviation.

Noculus width modulator PWtJIA regarding amplitude correction,
PvVjv! [IB1! Microprocessor μP power) and σ each waveform A.

The pulse width is modulated by the amplitude correction value ■/■ for B and has a duty ratio proportional to the bias correction value of the lever.
, n'Ls inverter N2. It is inverted at N3 and the duty ratio becomes inversely proportional to the bias correction. Switches S2A and 82B are input/output terminals N2. The adder circuit Σ1 is opened and closed by the pulse train from N3. By turning t on and off for the output signal of Σ2, this signal becomes 1.
97 pulse width modulation, switch S2A.

82B output signal 0. P is a low-pass filter L P
The signals q and r are smoothed by F2A and LPF2B to remove modulation frequency components, and subjected to bias correction and amplitude correction.

The subsequent signals are as shown in FIG.
The signal is binarized by v, differentiated by differentiators D'A and DB, converted to absolute values by polarity switching amplifiers P2A and P2B, and added by addition circuit Σ3 to form a speed signal y. The speed signal y obtained in this manner remains stable even if the amplitude and bias value of the sinusoidal signals A and B output from the encoder vary.

In the above embodiment, the process is performed before the differentiators DA and DB, but it may also be performed for the speed signal y output from the adder circuit Σ3. Further, although the manual input of the differentiators DA and DB was a signal that has been subjected to bias correction, it may be a signal that has not been subjected to bias correction. In other words, ■Addition circuit Σ1. Bias correction by Σ2, ■Switch S2A.

82B and low-pass filter LPF'2A, LPF2
Amplitude correction by 8, ■Differentiators DA, DB, zero cross comparators ZC2A, ZC2B, polarity switching amplifier P2
In the above embodiment, the detection of the speed signal by A, P2B and the adder circuit Σ3 was performed in the order of ■→■→■, but other orders such as ■→■→■, ■→■→■, ■→■→■, ■→■→■,
It is also possible to perform one of ■→■→■.

(Effects) As described above, according to the present invention, in a speed signal detection device that generates a speed signal from a sinusoidal signal from an encoder, amplitude fluctuations and bias deviations of the sinusoidal signal are corrected, so that It is possible to eliminate amplitude fluctuations in the signal and fluctuations in the speed signal due to bias deviation.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Figs. 2 and 3 are waveform diagrams showing signal waveforms of various parts of the embodiment, and Fig. 4 is a diagram explaining the correction principle of the embodiment. It is. PA, PB, P2. A, P2B...Polarity switching amplifier,
ZCA, ZCB, ZC2A, Z02B...Zero cross comparator, SA, SB, S2A, 82B...Switch, A/D...Analog/digital converter, μP・
・MicroProcera f, PWMIA-P'WM2B・
...Noculus width modulator, LPFA, LPFB, LPF2
A, LPF2B...Low pass filter, Σ1 to Σ3
...additional MF circuit, N1-N3...inno(-ta, DA, DB...differentiator.) −−−−−ru to～■几）−１”−−−− ゝ'−,−−／” γ0/douji\8k.

Claims (1)

[Claims] A velocity signal is detected by differentiating and synthesizing the sinusoidal signal from the encoder, and before or after this detection processing, bias correction corresponding to the bias value of the sinusoidal signal is performed, and before or after this bias correction. A speed signal detection device that performs amplitude correction corresponding to amplitude variation of the sinusoidal signal after and before or after the detection processing, and means for converting the sinusoidal signal from analog to digital; an arithmetic means for adding and subtracting output signals of the arithmetic means; a first pulse train generating means for generating a pulse train having a duty ratio inversely proportional to the addition result of the arithmetic means; a second pulse train generating means for generating a pulse train having a ratio;
means for smoothing the pulse train from the pulse train generating means; and adding the output signal of this means to the signal before or after the amplitude correction for the sinusoidal signal and before or after the detection process, Adding means for performing bias correction and a pulse train from the first pulse train generating means turn on/off and smooth the signal before or after the bias correction for the sinusoidal signal and before or after the detection processing. A speed signal detection device characterized in that it has means for performing the amplitude correction as bias correction means and amplitude correction means.