JPS61201363A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To utilize a resource effectively and to improve the reliability of a nonvolatile memory by storing and holding data in the nonvolatile memory part as code data by the error detecting and correcting function of a CPU. CONSTITUTION:An encoding means is made by a CPU 103 to function and 8-bit data is converted into 13-bit data (8-bit data plus 4 check bits plus 1 parity bit) and written on the code data storage area 106-1 of an EEPROM 106. When data stored in the EEPROM 106 are used for processing, the code data is read out and checked by a decoding means to obtain the 8-bit data. When access needs to be attained fast, the initial setting program in a ROM 105 is executed and all code data which are stored in the EEPROM 106 and need to be accessed fast are corrected and restored to the 8-bit data successively by using the decoding means, so that the data are stored in a RAM 104.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a single-chip microcombinator. In particular, a program storage unit that stores programs, a data storage unit that stores data, and a data input/output unit,
Central processing unit (hereinafter referred to as CPU) that processes data
In addition, the present invention relates to a single-chip micro combinator having a non-volatile memory section that holds and stores various information.

With the rapid progress of LSI technology in recent years, it has become possible to realize single-chip microcombinations equipped with non-volatile memory.

Non-volatile memory has the characteristic of retaining data even when it is not in operation.
ble & Electrical PIograma
ble Read OnlyMemory) EEP
ROM can write and erase data by controlling the voltage applied to the control gate of the memory transistor, so it is used for controlling automobile engines using micro combinators, electronic channel control for televisions, and servo motors. It can be used in many industrial fields such as control.

(Conventional technology and its problems) As mentioned above, non-volatile memory is being put into practical use in many industrial fields, but EEPR? ) Various types of non-volatile memory represented by M are manufactured using complicated processes in order to achieve non-volatility, which is their greatest feature, so they are much more expensive than ordinary volatile semiconductor memories. Therefore, it is extremely difficult to economically incorporate nonvolatile memory into a single-chip microcomputer that integrates a CPU, 111,110 functions, a program storage section, and a data storage section.

Furthermore, even under the current situation where the data retention characteristics of non-volatile memory have improved, data errors still occur due to data deformation caused by the application of high energy, erasure or writing, external noise, and other causes. There is still a possibility that it will.

Therefore, the first object of the present invention is to economically realize a single-chip microcombiator with a built-in nonvolatile memory by using error detection and correction functions.
This can be achieved by effectively utilizing the resources originally present in a single-chip microcombiner, without adding special components such as ing code circuits.

A second object of the present invention is to protect data in non-volatile memory from errors during operation on an application system of a single-chip microcomviator with built-in non-volatile memory.

(Means for Solving the Problems) The microcomputer of the present invention has a data input/output section, a program storage section for storing a program, a data storage section for storing data, and a data input/output section for storing data on a single semiconductor substrate. In a single-chip microcombination system equipped with a CPU that processes various data and a non-volatile memory section that stores and retains data even when it is not operating, the CPU stores predetermined data according to the program in the program storage section. An encoding means for converting the encoded data into encoded data, and a decoding means for decoding the encoded data by a CPU according to a program in a program storage section to generate predetermined data, and the encoded data is stored and retained in a non-volatile memory section. It is characterized by the following.

(Embodiment) FIG. 1 shows an embodiment of the present invention which includes a built-in non-volatile memory and has an error detection and correction function.

In this embodiment, EBPR is used as the nonvolatile memory.
? >M, the data handled is 8 bits, and the error detection/correction method is a Hamming code with 4 check bits for 2-bit error detection and 1-bit error correction, and 1 even parity bit. Use.

The single-chip microcombiator 100 includes an external input line 101, an input/output unit 102, a CPU 103 that performs data calculation and processing, a RAM 104 that stores various information, and a ROM 1os that stores programs and system constants.
, an EBPROM 106 that holds and stores information, and an internal bus 107. CPUI 03 is
encoding means for converting B-bit data into code data;
Although it has decoding means for converting code data into 8-bit data, that is, detecting and correcting errors using the code data, illustration thereof is omitted to avoid complication of the drawing.

The operation of the error detection/correction function will be described below with reference to FIG.

The 8-bit data is converted into 13-bit encoded data (
The data is converted into 8 bit data + 4 check pits + 1 parity bit) and written into the code data storage area 106-1 of the EEPROM 106. That is, EEPRO
M106 stores data in the form of encoded data. Therefore, when using data stored in the EEFROM 106 for processing, read the code data of the data,
A check is performed using a decoding means, and the resulting 8-bit data is used.

However, in the case of data that requires high-speed access, an initial setting program in the ROM 105 is executed. The initial setting program sequentially uses a decoding means to correct all the coded data that is held and stored in the EEFROMI06 and requires high-speed access to 8-bit data, and then converts the newly generated 8-bit data into 8-bit data. When you need to write data to a given address, first
The 8-bit data in the data area of the RAM 104 is rewritten, the encoding means is executed for the new 8-bit data, and the encoded data is written into the EEPROMIO 6. In order to confirm whether the rewritten data has been correctly stored in the EEPROM 106, the data is read out again and the decoding means is executed on the encoded data. As a result, if an error exceeding the correctable range has occurred, a signal is sent to notify this fact.

Next, specific examples of the encoding means and decoding means will be explained in detail using FIGS. 2, 3, 4, 5, and 6.

FIG. 2 details the CPU 03 of FIG. 1, and shows the input/output unit 102. RAMI 04. ROMIO3 and EEP
3 is a block diagram shown together with a ROM 106. FIG. Referring to FIG. 2, the CPU 103 includes an instruction register (hereinafter referred to as IR) 2o1, a control circuit section 202, an achi emulator (hereinafter referred to as Acc) 203, and a first
A temporary register (hereinafter referred to as TR1) 204, a second temporary register (hereinafter referred to as TR2) 205, an arithmetic logic unit (hereinafter referred to as ALU) 206, and a program status word (hereinafter referred to as PSW) 207 including a carry flag. and address point register 20
8, a loop counter 209, and a shifter 210.

In the error detection/correction method of this embodiment, the check bits are provided by a linear combination of each bit of data. That is, by addition in mode (MODE) 2, an operation is applied that gives 0 if the sum of each bit of data is an even number and 1 if it is an odd number.

The code generation matrix B is (4×8) as shown in equation (1)
Given as a matrix, each row vector J1~I! This is preset on the ROM 105 as 8-bit data of 4.

8-bit data is converted into A proverb (a7a, a, a, as
a2a, io ), check bit Ci('
-1s 4) is ct-B, -J (mod 2
) (where the operation ・indicates the inner product of vectors). Thus, the popular code H-(a, a.

a, a, a3a2a, aoc4c, c2c1)
The even parity -P of this 12-bit data is calculated and added as the final element of the Hamming code H, and 1
It is assumed to be 3-bit code data.

FIG. 3 shows a general flowchart of encoding, and FIG. 14 shows Acc203. The contents held in TRI204 and TR2205 are shown.

The encoding operation will be described in detail below with reference to FIGS. 2, 3, and 4.

First, the 8-bit data to be converted is stored in Acc203.The encoding command (state (1) in FIG. 4) is lR2O.
When latched to 1, the control circuit section 202 decodes the encoded instruction code, generates a control signal at a predetermined timing, and performs the following operations.

Transfer the data of Acc 203 to 'rR1204 (Fig. 3-(1), Fig. 4-(2)), then Fig. 3-(2))
Process. That is, first, RO is applied to TR2205.
Read the data of row vector B4 set in the table of M105 (Figure 4-(3)), TRI 20
The ALU 206 performs a bitwise AND operation on the data of 4 and puts the result in the TR 2205 (Figure 4-(4)
)). Next, kcc 203 is shifted to the left by 1 bit by shifter 210, and 18" is stored in loop counter 209.
(Fig. 4-(5)).

While decrementing the contents of the loop counter 209 by 1, shift the contents of the TR2205 including the carry by 1 bit to the right until the value becomes 0, and if the carry is 1°, invert bit 0 of the Acc 203 (4th Figure-(6
)-3). If the carry is 10', repeat the process (Fig. 4-(6)-2) until that time (Fig. 4-(6)-2).
(1) to Figure 4-(6)). As a result of such processing, check bit C4 is generated in the least significant bit of Acc203 (Fig. 4-(6)-
5).

The processes in FIG. 3-(3), FIG. 3-(4), and FIG. 3-(5) are executed in the same way as the process in FIG. 3-(2) described above.
(7) to (11)), data information to be encoded is set in bits 4 to 11 of Acc 203, and check bits C1 to C4 are set in bits 4 to 3 (the fourth Figure-(12)).

The parity bit set in Figure 3-(6) is Acc2
Please set the contents of 03 to TR2205.
)), shift the contents of Acc203 to the right by 1 bit, and set 1121 in the loop counter 209 (Fig. 4-(
14)), While decrementing the contents of the loop counter 209 by 1, shift the contents of TR2205 including the carry by 1 bit to the right until the value becomes O, and if the carry is 111, invert the p)O of Acc203. 101
If so, it is generated by performing loop processing similar to FIG. 4-(6). (Figure 4-(
15)).

Through this series of processing, code data is generated by adding 4 check bits of a Hamming code and a quality pit to 8-bit data.

Next, the decoding process will be explained. First, error information (error flag) is obtained from a 12-bit Hamming code excluding parity bits using a check matrix M. The check matrix M is a (4x16) matrix, and each row vector of it is
RO as word type row data M1 to M4
It is preset on M105.

So, the code data excluding the parity bit is A”
(0000ay R6aB R4113a2a1ao
C4Cs Cx Ct), error bit e, (
txl, 4) is given by e1=#B A (mod 2). Further, code data A is parity-checked using parity bit P, and a value is obtained as a result. (oo...Oe4e3e, el) is called an error flag. Error flag = 0. e.

− If 〇, no error has occurred, and the decryption process ends normally.

If the error flag is not 0 and ep is "11",
A 1-bit error occurs in 12-bit data. This error can be corrected, and the value of the error flag is information on the bit where the error occurred, and the correction is performed using pattern data for inverting the error bit, which is set in the table.

In cases other than the above, that is, the error flag is O and ep is +1+1, or the error flag is not O (ep is “0”).
° If the error exceeds the error correction range of this method (
2 or more errors have occurred, a predetermined control signal is generated.

Below are Figure 1, Figure 2, Figure 5, which is a schematic flowchart of decoding, and Acc203 and TRI during the decoding process.
The operation of the decoding command will be specifically explained using FIG. 6 showing the contents held in TR 204 and TR 2205.

When the decoding command is latched into the IR 201, the control circuit unit 202 decodes the decoding command code, generates a control signal at a predetermined timing, and performs the following operations. First, T
Clear RI 204 to %01 and EEPROMI06 addressed by address point register 208
5 (1), FIG. 6-(1)), and then read out the code data held in Acc203.
Rotate the contents of 03 to the right by 1 bit (Figure 6-(2))
.

Next, the process shown in FIG. 5(2) is performed. TR2205, R
Read the decoding matrix data M4 set in the table of OMI O5 (Figure 6-(3)), perform an AND operation between its contents and Acc203, and send the result to TR2205.
(Figure 6-(4)) and turn the TRI 204 to the left 1
The bit is shifted and 112' is set in the loop counter 209 (in this case, there is no change since the TRI 204 is cleared) (FIG. 6-(5)). While decrementing the contents of the loop counter 209 by 1, the contents of the TR2205 including the carry are shifted to the right by 1 bit until the value becomes 0. If the carry is 111, the TRI204 is The process of inverting bit 0 of (FIG. 6-(6)-2) and leaving it as is if it is l g l is repeated.

In this way, error bit e4 is set in bit 0 of TRI 204 ((6)-4 in FIG. 6).

The processes in FIG. 5(3), FIG. 5(4), and FIG. 5(5) are also executed in the same manner as the process in FIG.
Error bits e1 to e4 are set in bits 0 to 3 of 4 (FIG. 6-(12)).

Next, the parity check shown in FIG. 5-(6) is performed. A
Rotate the contents of cc203 one bit to the left in Figure 6 (13
)) and set its contents to TR2205 (Fig. 6-
(14)). Shift the contents of TR2205 including the carry one bit to the right (Figure 6 (15)), TRI2
The contents of 04 including the carry are shifted to the left by 1 bit and the OIC parity bit of TRI 204 is set ((16) in FIG. 6). Loop counter 209
(Fig. 6-(16))), while decrementing the contents of the loop counter 209 by 1, shift the contents of TR2205 including the carry by 1 bit to the right until the value becomes 0. If,
Repeat the process of inverting bit O of TRI 204 and leaving it as is if it is not '0° (Figure 6-(18))
. As a result, the parity check bit ep is set in the OK bit of TR1204 ((20) in FIG. 6).

If the content of TR, 1204 is 0, error 7 lag, e
Since both p are '0', there is no error and the decoding ends. TRI≧2. e, m'l'', a 1-bit error has occurred, so the error correction process shown in FIG. 5-(7) is performed as follows.

Based on the value of the error flag of TRI 204, R,0
Read the ninth pattern data that inverts the erroneous bit of the code data from the table set in M105,
Figure 6-(21) As an example, it should be set in TR2205.
(if as is incorrect), TR2205 and Acc 20
3] and stores the result in Acc 203 (FIG. 6-(22)).

If the contents of TRI 204 are other than the above, an error outside the correctable range has occurred, so see Figure 5-(8).
It outputs a predetermined signal, such as setting a flag for that purpose and generating an interrupt signal. With the above operations, correct code data is stored in Acc203,
End the decryption process.

In the main program, if you want to use it as correct 8-bit data, shift Acc203 to the right by 5 bits.
0 to a are used. Also, when rewriting,
The contents of Acc203 are written to EEPROMIO6 addressed by address pointer 208.

In this embodiment, a method for correcting one error and detecting two errors using a Hamming code and parity is used for one 8-bit data.However, in order to reduce the ratio of additional bits to one data, multiple data It is also possible to realize false detection and correction using an encoding/decoding means that treats the data as one block of data.

(Effects of the Invention) As described above, the present invention is a system that can effectively utilize the inherent resources of a microcomputer and greatly improve the reliability of data held in nonvolatile memory. In addition, it also contributes to improving the yield of the product.
It is possible to economically realize a single-chip microcombinator with non-volatile memory, and its practicality is extremely high.

[Brief explanation of the drawing]

10 is a simple block diagram of a single-chip microcomputer showing an embodiment of the present invention, FIG. 2 is a more detailed block diagram of FIG. 1, FIG. 3 is a general flowchart of encoding, and FIG. The figure shows the register contents when the encoding means is executed, Figure 5 is a general flowchart of decoding, and Figure 6
The figures each show the contents of the registers when the decoding means is executed. 100...Single chip microconverter, 101...External input line, 102...
・Input/output unit, 103...Central processing unit (CPU
), 104...RAM, lQ5...R
OM, 105-1...Reset log 2M, 106...EEPROM, 106-1...
... code data storage area, 107 ... internal path, 201 ... instruction access register (
IR), 202... Control circuit section, 203...
...Akyemureta (Acc), 204...
・1st tempo 2 reregister (TR1), 205...
...Second temporary register (TR2), 206...
...Arithmetic unit (ALU), 207...Program status word (psw), 208...
... Address point register, 209 ... Loop counter, 210 ... Shifter. Tachibana 4 times (1) Accθ0071 l2 (Ira, 1l-ttp
tz mouth beef times

Claims (1)

[Scope of Claims] A data input/output unit, a program storage unit that stores programs, a data storage unit that stores data, and a central processing unit that processes various data according to the program on a single semiconductor substrate. , a single-chip microcomputer equipped with a nonvolatile memory unit that stores and retains data even when the computer is not in operation, comprising: encoding means for converting predetermined data into encoded data by the central processing unit according to a program in the program storage unit; a decoding means for decoding encoded data by the central processing unit according to a program in the program storage unit to generate predetermined data, and the encoded data is stored and retained in the nonvolatile memory unit. A single-chip microcomputer.