JPS61198752A - semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To inspect whether desired signals are written in a switch matrix or not by a simple test pattern, by providing two switch-element lines and two shift registers. CONSTITUTION:In a structure comprising a circuit block 1 and a switch matrix 2, a first switch-element line 9, a first shift register 11 a second shift register 14 and a second switch-element line 17 are added. The element line 9 is turned OFF by using an outer terminal 10. Then, the matrix 2 to be inspected is not affected by an output 3 of the block 1. Thereafter, the register 11 is operated by using an outer terminal 12 and a clock 13. Thus, the output signal line 3 in the matrix 1 can freely determine the high and low states. These states are set in the input of the register 14 when the element line 17 is turned ON by an outer terminal 18. The element line 17 is turned OFF, and the information in the register 14 can be read out through an outer terminal 15 by using a clock 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit whose chip functions are programmable.

[Technical background of the invention and its problems]

In recent years, the following LSIs have appeared in response to the demand for high-mix, low-volume production.

(1) Circuit blocks with basic logic functions used in standard cell type LSIs are registered in advance in a computer [7], and automatically processed by the computer to place and route these circuit blocks to achieve the desired final design. Get the product.

(2) Gate array method The basic circuits constituting logic gates are arranged in an array on a wafer in advance, and the wiring pattern is determined by automatic wiring in the same way as in the standard cell method, and the desired LS
Get I.

Although these have a shorter development period than completely hand-designed LSIs, they require a manufacturing process using link graph technology, and there is a problem in that it takes several weeks to several months from the completion of the design to the completion of the LSI.

In response, the applicant has proposed the following method (
(Patent Application No. 157718/1982).

That is, as shown in FIG. 2, a plurality of circuit blocks 1a are constructed of one or more logical functional elements.

1b...IN is fabricated on the board after completing the wiring process using a dedicated IC method, and the input and output signals of each circuit block are guided onto a switch matrix that can electrically write ON and OFF states. , all the input signals of each circuit block can be connected via a switch element 7 such as an E"FROM or a MOSFET equipped with a 1-bit memory. 3 is a T-shaped signal output wiring, 4 is a T-shaped signal output wiring. is the signal input wiring.

According to this method, since it is field programmable, the user can write the logic functions by hand to create a desired I/F with high functionality. You can get 9I significantly faster. Moreover, the LSI can be designed by connecting input signals and output signals of circuit blocks having a certain logical function, and is easy to understand even for designers who are accustomed to designing logic on a board.

In this new method, the completed LSI has, as input/output terminals, signal terminals originally necessary for the operation of the LSI and signal terminals for writing ON/OFF information of the switch matrix. ON/OFF information of the switch matrix can be written into this write signal terminal. There is a problem in that a complicated test must be performed using the input/output terminals of the completed LSI to determine whether the information has been written without error.

[Aspects of the invention 1] This invention improves the above-mentioned drawbacks by using a simple circuit and some external terminals to check whether the ON/OFF information of the switch matrix is written correctly and where it is wrong. The purpose of the present invention is to provide an LSI that can be identified by a simple test pattern by adding the following information.

[Summary of the invention]

According to the present invention, input signals and output signals of a plurality of circuit blocks having basic logic functions as shown in Japanese Patent Application No. 58-157718 are guided on a switch matrix that can eliminate electrical ON/OFF states. In a logic circuit in which all output signals of a circuit block can be connected to all input signals through a switch element, a first switch element that electrically disconnects all output signals of the circuit block and the switch matrix. a first shift register for transmitting a signal to an output line of the circuit block; and a second switch element column for reading information on an input line of the circuit block connected to the output line of the circuit block. , a second shift register allows checking the ON-OFF state of the switch matrix.

The gl shift register may be connected to the input line, and the second shift register may be connected to the output line.

〔Effect of the invention〕

According to the present invention, it is possible to easily realize a logic integrated circuit having a desired logic function.In a semiconductor integrated circuit, it is possible to easily realize a logic integrated circuit having a desired logic function. By adding a simple circuit and some external terminals, it is possible to perform inspection using a simple test pattern. Also, since you can find out what went wrong, rewriting the switch matrix becomes a prize.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, the layout will be explained using FIG. 3.

That is, a circuit block la is placed on one side of the S L wafer.

1b...IN is built in, each circuit block is 4 in, and logic functional elements such as NAND gates are 0M.
It has an O8 configuration, and is a dedicated IC, that is, a hand-written standard cell in a standard cell system, or a gate array with 6 wires.

Complex logic functional elements may be formed by combining standard cells with interconnections using a standard cell method.

The configuration of the circuit block is as follows.

■ Block with two 4-input NAND gates
...15 ■ 2 inputs) Block with 4 NAND gates
...14 ■ Block with one 8-input NAND gate ...
1 piece■ Block that holds 4 inverters...10
0 ■ Block of 8-bit registers...19 ■ Block with two D-type flip-flops
...19 ■ Block with two 4-input AND gates ■ Block with four 2-to-1 data selectors...1
3 ■ Block with two 4-bit binary counters
...1) Block with two 02-4 line decoders...7 Block with two 03-8 line decoders...3 blocks @4-1 block with two selectors...5 ( 38
-Block with 1 selector...Block with 4 08-bit serial parallel output shift registers
...3 [phase] 8-bit parallel block with serial output shift registers
...Block with 3 08-bit serial input and serial output shift registers ...2 O
Pro7 with two monostable multiviprator
...4 pieces @ 2 inputs O
Block with 4 R gates
・・・ 4
Block with 4 input NOR gates
...3 pieces @AND-O
Block with two R inverters: 3 pieces 064-bit RAM block: 3 pieces @
2 A:y7', ) EXCLUSIVE-O
R,'y''-t 4 blocks
...2 04-bit comparator blocks
・Block with 2 flip-flops in 3 @J-
- 4 09-bit even/odd parity generator/checker blocks
...Block of 3 x 04-bit binary full adders...Block with 4 x 2 x 02 input multiplexers
・Block with 4 5 pieces 08-R latches ・2 pieces @ ALU block
...1 block of 8-bit addressable latch - 1 block of 0 lookahead carriage generator
. . . A circuit block consisting of one MSI, that is, 274 MSIs, is provided, so that LSIs of all functions can be extracted from 18 chips. The average number of inputs and outputs of each circuit block is 8 and 4, respectively. The input section and output section of the logic functional element serve as the input section and output section of the circuit block, and each output section is provided with an output buffer (
(not shown). The output section is connected to a T-shaped signal output wiring 6, and the input section is connected to a signal input wiring 4 that intersects with this. Then, at the intersection, the decoder turns ON.
, switch elements 7 and 8 which are turned off are provided. Therefore, the connection between the input and output parts basically requires only one switch, and the length of the equipotential wiring accompanying one current path is, as can be seen from Fig. 2, an average of 2. 5!
This prevents delays due to time constants.

In the circuit shown in FIG. 2, in order to test the ON/OFF state of the IJ switch 2, a complex test pattern is required that takes into account the operation of the circuit 1.

The present invention improves this point, and a typical example thereof is shown in the first example.
As shown in the figure. Here, the first switch element row 9 is shown in FIG.
, a first shift register 1), a second shift register 14, and a second switch element array 17 are added.

By electrically turning off the first switch element array 9 using the external terminal 10, the switch matrix 2 to be tested is no longer influenced by the output 3 of the circuit block 1. Next, by operating the first shift register using the external input terminal 12 and clock input 13, the output signal line 3 of the circuit block in the switch matrix can freely determine the high state or low state. can. These states are set to the inputs of the second shift register when the second switch element array 17 is turned on via the external terminal 18. Next, by turning off the second switch element array 17 using the external terminal 18, the second shift register 14 is no longer influenced by the switch matrix 2. Here, using the clock manual 16, the second
The information in the shift registers can be read out one after another through the external terminal 15. In this way, it is possible to apply a signal to the switch matrix and read it out independently of the circuit block 1, so it is possible to check the ON/OFF state of the switch matrix from this information.

This inspection method is shown in Figure 3 for a relatively small scale case.
This will be explained using FIG.

FIG. 3 is an example of a circuit block having three output lines and six input lines. FIG. 4 shows part of the matrix connection analysis of this circuit.

First, the signal S1 is set to LOW level using an external terminal to electrically turn off the first switch row 9. At this stage, the output 3 of the circuit block 1 is electrically disconnected from the signal 3' on the switch matrix. The shift register 9°14 used here receives the clock signal CI, 0
It is assumed that the shift occurs at the start of step 2. External input terminal 1
2. 0 to operate the clock input terminal 13 as in the fourth
That is, C1 is clocked twice with DI set to LOW, and then C1 is clocked with DI set to HIGH. This causes the signal line 3-1 to go High, and the signal line 3-2 to
．． 3-3 becomes a Low state (point A). After this, when the signal S2 is made High by the external terminal 18 and the second switch element 17 is turned on, only the input signal line 4 of the circuit block 1 connected to the signal 3-1 becomes High, and the second shift is started. The input of register 14 is set. Next, the second switch element row 17 is turned off by the external terminal 18.
Then, the clock 16 of the second shift register 14 is activated. In the case of this figure, the signal DO at the external output terminal 15 becomes High at the first and sixth times of the clock signal C2. Therefore, the output of the first circuit block 1 is
It can be seen that it is connected to the inputs of the first and sixth circuit blocks.

[Other embodiments of the invention]

(1) When turning on the second switch element row 17, the first
The output data of the second shift register 1) and the output data of the second shift register 14 overlap in a wired-OR manner. If the drive ability of the output Q of the first shift register 1) is sufficiently larger than the drive ability of the output Q of the second shift register 14, the first shift register 1
4, the data is correctly read into the second shift register 14. In order to roughly ensure this operation, the output Q of the second shift register 14 must be a shift register that can be turned on and off by an external terminal. Just use it.

Further, during normal circuit operation, the output of the circuit block 1 may overlap the output of the shift register in a wired-OR manner. In order to ensure the operation of the output of the circuit 1), it is preferable to use a similar shift register as the first shift register 1).

Figure 5 shows a conventional shift register, and Figure 6 shows an example of a shift register in which the Q output can be turned on and off using an external terminal.
As shown in the figure.

In FIG. 5, an output 20 of a normal shift register 19 is directly connected to a signal line 21 of a switch matrix 2. In FIG.

In FIG. 6, the output 20 of the shift register 19 is connected to the signal line 21 of the switch matrix 2 through a switch element 22 controlled by an external terminal 23.

+21. The external terminal 10 of the AI switch element row 9 and the external terminal 18 of the second switch element row 17 can be made common. In other words, when the second switch element row 17 is turned on during inspection of the switch matrix 2, , the information of the switch matrix is transferred to the second shift register column 1
4, and then the second switch element row 17 is turned off.
It is fine as long as this information remains available until F. Therefore, as shown in FIG. 7, the external terminal 24 is connected to the second switch element row 17, further inverted by an inverter 25, and connected to the first switch element row 9. When inspecting the switch matrix 2, the first switch element row 9 is turned off and the second switch element row 17 is turned on.
Then, when the first shift register 1) obtains the data in the signal 3, the data in the signal 4 is set in the second shift register 14. At this time, the external terminal 24 connects the second switch element array 17 to the oFp, xi shift register 1.
) is turned on, the output data of the circuit block 1 enters the switch matrix, but since the second switch element row 17 is turned off, the second shift register 1
Since signal 4 is not affected, the data of signal 4 can be read correctly.

The same thing is possible in the case of FIG.

In FIG. 8, a delay circuit 26 is used in place of the inverter 25 in FIG. 7. The inspection method is to use the external terminal 24 to connect the first. The second switch element arrays 9 and 17 are turned off, and data is written to the signal 3 by the first shift register array 1). Thereafter, the switch element array 17 is turned on and then turned off by the external terminal 24. The data of signal 4 during this period is set in the second shift register column 17. At this time, the switch element array 9 is also turned on, and the output data of the circuit block 1 enters the switch matrix 2, but since this timing is shifted by the delay circuit 26, the data set in the second shift register array 14 is is not affected.

It goes without saying that a combination of the methods shown in FIGS. 7 and 8 is also possible.

(3) Also, for example, the external input terminal 10 shown in FIG.
Since terminals 12, 13, and 18 are for testing the switch matrix, they are not relevant during normal LSI operation.

Therefore, these terminals must be fixed so as not to affect this during normal operation. To this end, L
Using SI package pins is not economical. Therefore, as long as these terminals are not touched except when inspecting the switch matrix, it is desirable that the potential be fixed at a potential that will not cause any problem during normal operation.

As shown in Figures 9 and 10, the
7, it can be realized by using a resistor 29 whose one end is connected to the power supply VDD 28 or the ground line V8, 30, depending on whether the switch is P-ch or N-ch, for example.

[Brief explanation of drawings]

1 is a plan view explaining the present invention, FIG. 2 is a plan view of a programmable LSI, FIG. 3 is a small-scale plan view showing the present invention, and FIG. 4 is a switch matrix of FIG. ) IJ
A signal waveform diagram of a test program for wax inspection; FIG. 5 is a circuit diagram showing a conventional shift register; FIG. 6 is a circuit diagram showing another embodiment of the present invention; FIGS. 9 and 10 are circuit diagrams showing other embodiments of the invention. FIGS. 9 and 10 are circuit diagrams showing other embodiments of the invention. In the figure, 1... functional block, 2... switch matrix, 3... output signal line of circuit block, 4
... Input signal line of circuit block, 5... Signal line for connecting output signal line 3 and input signal line 4 in switch matrix, 6... Contact point of output signal line 3 and signal line 5, 7... OFF state at the intersection of the switch matrix,
8...ON state, 9...First switch element row, 1
0... Its external terminal, 1)... First shift register, 12.13... External data input terminal and clock input terminal of the first shift register group, 14... Second shift register , 15... External output terminal of the final stage of the second shift register, 16... Clock input external terminal of the second shift register group, 17... Second switch element array, 18... The External terminal, 19... Shift register, 20... Output terminal thereof, 21... Output signal line or input signal line of circuit block, 22... Switch element, 23. 24... External terminal, 25 ...Inverter, 26...Delay circuit, 27...Input buffer,
28...Power supply, 29...Grounding, 30...Resistance. Representative Patent Attorney Kensuke Chika (and 1 other person) Figure 2 Figure 3 - ~ , ~ , +-1'
Qli's Li uQQFigure 5Figure 6Figure 7Figure 8Figure 10

Claims (5)

[Claims] (1) Built into the board, it has its own logical function;
and a plurality of circuit blocks having a signal input section and a signal output section, and a wiring region formed on the substrate and adjacent to a circuit block region composed of the plurality of circuit blocks, the circuit block region being The wiring area is composed of a group of signal input wirings and a signal output wiring group that intersect with each other, and the signal input wiring group is connected to the signal input section of each circuit block. The signal output wiring group is connected to the signal output part of each circuit block, and these connections are made in the wiring area where the circuit block is adjacent to the signal input wiring group and the signal output wiring group. A semiconductor device in which a switch element is provided at each intersection with a wiring group, and by controlling the ON/OFF state of the switch element, the input/output relationship of signals between each circuit block is determined and a desired integrated circuit is constructed. In the integrated circuit, a first shift register is provided between the circuit block area and the one wiring group via a first switch element row, and a second switch element is provided in the other wiring group. A semiconductor integrated circuit characterized in that a second shift register is provided through a column. (2) At least one of the first and second shift registers is a shift register in which the connection between the output of the shift register and the input/output terminal of the circuit block can be electrically turned ON/OFF by an external terminal. The semiconductor integrated circuit according to claim 1, characterized in that the semiconductor integrated circuit uses: (3) The first switch element row and the second switch element row are electrically turned on and off from the same external terminal, and their ON and OFF relationships are inverted or delayed. A semiconductor integrated circuit according to claim 1 or 2, characterized in that: (4) When there is no external input, install an input buffer that fixes the external terminals of the switch element array so that the first switch element array is electrically ON and the second switch group is electrically OFF. A semiconductor integrated circuit according to any one of claims 1 to 3, characterized in that: (5) The above-mentioned patent is characterized in that it has an input buffer that fixes the clock input external terminal of the first and second shift registers so that at least one of the first and second shift registers does not operate when there is no external input. A semiconductor integrated circuit according to claims 1 to 4.