JPS6119547Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power amplifier circuit that performs an amplification operation with almost the same power efficiency as a class B amplification operation and does not generate switching distortion.

Conventionally, single-enterpush pull (hereinafter abbreviated as SEPP) circuits have been frequently used in power amplifier circuits for audio, and because of their particularly good power efficiency, they are designed to allow a predetermined idling current to flow. B class biased to perform class action
SEPP power amplifier circuit is adopted.

However, in a class B SEPP power amplifier circuit, switching of the transistor is performed during the application of input signals of positive and negative half cycles, which cause load current exceeding twice the idling current to flow, and this is due to the carrier accumulation effect of the transistor. As a result, there was a drawback that switching distortion occurred.

The present invention has been developed in view of the above, and it eliminates the above drawbacks, performs amplification operation with almost the same power efficiency as class B amplification operation, and avoids switching of transistors over the entire period of the input signal. The object of the present invention is to provide a power amplifier circuit in which switching distortion does not occur, and the present invention will be explained below with reference to embodiments.

The figure is a circuit diagram of an embodiment of the present invention.

A power amplifier circuit according to an embodiment of the present invention has a resistor 5 connected between the emitter of the transistor 1 for the drive stage and the collector of the transistor 3 for the output stage.
Transistors 1 and 3 are inverted Darlington connected, and the collector of transistor 3 is connected to resistor 7.
A resistor 6 is connected between the emitter of the drive stage transistor 2 and the collector of the output stage transistor 4 to connect the transistors 2 and 4 to an inverted Darlington. The collector of the transistor 4 is connected to the load 9 through the resistor 8, and the individual bias circuit 10 that provides a constant bias voltage is connected between the base of the transistor 1 and the base of the transistor 2 to form a SEPP power amplifier circuit. Configure.
This SEPP power amplifier circuit is further connected to a first inverting amplifier 19 having an input resistor 17 and a feedback resistor 23.
and a second inverting amplifier 20 having an input resistor 18 and a feedback resistor 24. On the other hand, a series circuit of resistors 11 and 12 is connected between the emitter of transistor 1 and the emitter of transistor 2, and the voltage between the emitters of transistors 1 and 2 is divided at the common connection point B of resistors 11 and 12. SEPP
A diode 15 is used to cut off the voltage at the output end of the power amplifier circuit, that is, the common connection point A between the resistors 7 and 8.
is applied to the inverting input terminal of the first inverting amplifier 19 via the input resistor 17, and the first inverting amplifier 19 is configured to operate when the voltage at the output terminal A is equal to or higher than the reference voltage. Similarly, the reference voltage is applied to the non-inverting input terminal of the second inverting amplifier 20 via the diode 14, and the voltage at the output terminal A is applied to the non-inverting input terminal of the second inverting amplifier 20 via the input cutoff diode 16 and the input resistor 18. The second inverting amplifier 20 is configured to operate when the voltage at the output terminal A is equal to or lower than the reference voltage. Further, the output of the first inverting amplifier 19 is applied to the emitter of the transistor 1 through the resistor 21, and the output of the second inverting amplifier 20 is applied to the emitter of the transistor 2 through the resistor 22.

Note that the diodes 13 and 14 are connected to compensate for the forward voltage drop of the input cutoff diodes 15 and 16, and are biased so that current always flows in the forward direction.

In the power amplifier circuit configured as described above, the circuit between the positive power supply +B side and the output terminal A and the negative power supply -
The circuit between the B side and the output terminal A is selected to be equal to the resistance value of each resistor.

First, the case when there is no input signal will be explained. When no signal is input, transistors 1, 2, 3, and 4 are in an on state due to the bias voltage of fixed bias circuit 10, and a predetermined idling current flows through transistors 3 and 4. However, there is no potential difference between the output terminal A and the common connection point B, the inputs of the first inverting amplifiers 19 and 20 are zero, and the emitter currents of the transistors 1 and 2 are
and to resistors 6 and 22. Note that a constant current always flows through the resistors 11 and 12.

Next, when a negative half-cycle input signal is applied to the above power amplifier circuit, the base potentials of transistors 1 and 2 move to the negative side, and the collector currents of transistors 2 and 4 are This increase in collector current increases from the value at the time of the input signal, and flows into the load 9 through the resistors 6 and 8, causing the load 9 to generate power that is an amplification of the negative half-cycle input signal.

As the collector currents of transistors 2 and 4 increase, the voltage drops across resistors 6 and 8 increase, and the potential at output terminal A becomes higher than the potential at common connection point B, that is, the reference voltage.

On the other hand, when a negative half-cycle input signal is applied, the current flowing through the resistor 5 decreases from the value when no input signal is applied, or flows in the opposite direction (from the collector of transistor 3 to the emitter of transistor 1), causing the 1 attempts to transition to the off state. However, as mentioned above, because the potential of the output terminal A became higher than the potential of the common connection point B, the first
The first inverting amplifier 19 works and the first inverting amplifier 19
The potential of the output terminal of is lowered. So resistance 21
The emitter current of the transistor 1 flowing through the resistor 5 increases, and the change in the emitter current of the transistor 1 flowing through the resistor 5 is compensated by the increase in the emitter current of the transistor 1 flowing through the resistor 21. Therefore, the base-emitter voltage of transistor 1 is maintained at a value that turns transistor 1 on, and transistor 1 is maintained on.

At this time, since the input of the second inverting amplifier 20 is cut off by the diode 16, the closed state is maintained when there is no input signal.

Also, when a negative half cycle input signal is applied, resistors 5, 7, 17, 21 and 2
3, a bridge circuit is formed. Now resistance 7
If we ignore the resistor 7 because the current flowing through the resistors 5, 17, 21, and 23 is small, the bridge circuit is formed by the resistors 5, 17, 21, and 23, and the resistance values of the resistors 5, 17, 21, and 23 are R ₅ , R ₁₇ , R ₂₁ , and between R ₂₃
The bridge circuit is balanced when there is a relationship of R ₁₇ · R ₂₁ = R ₅ · R ₂₃ . If the resistance values of resistors 5, 17, 21, and 23 are selected so that the relationship R ₁₇・R ₂₁ = R ₅・R ₂₃ is established, the potential difference between the potential of common connection point B and the potential of the emitter of transistor 1 is is equal to the potential difference when there is no input signal, regardless of the magnitude of the current flowing through resistor 8, and transistor 1 is in the on state when the same value of emitter current as when no input signal is flowing through transistor 1. It will be maintained. Furthermore, when the condition R ₁₇ · R ₂₁ = R ₅ · R ₂₃ is not satisfied, transistor 1 is maintained in the on state as described above, but in this case, the emitter current value of transistor 1 is the same as that of transistor 1 when there is no input signal. is different from the emitter current value.

As described above, by maintaining transistor 1 in the on state, transistor 3 is also maintained in the on state.

Next, the operation when a positive half-cycle input signal is applied is also the same as in the above case, and detailed explanation thereof will be omitted. In this case, the bridge circuit explained above has resistors 6, 18, 22.
and 24, and the equilibrium condition is that the resistance values of resistors 6, 18, 22 and 24 are R ₆ , R ₁₈ ,
Assuming R ₂₂ and R ₂₄ , R ₁₈ ·R ₂₂ =R ₆ ·R ₂₄ .

In the figure, the positive power supply +B and transistor 1
The resistors 25 and 26 connected between the collector of the transistor 2 and the collector of the transistor 2 and between the negative power supply -B and the collector of the transistor 2 may be omitted.

Also, the above explanation is for the case where the reference voltage is obtained by dividing the voltage between the emitter of transistor 1 and the emitter of transistor 2, but the voltage between the base of transistor 1 and the base of transistor 2 is divided. The same is true when the reference voltage is set as the reference voltage.

As explained above, according to the present invention, regardless of the polarity of the input signal, all the transistors do not perform a switching operation throughout the entire cycle.
It always operates in the on state and no switching distortion occurs.

Furthermore, the transistors that cause current to flow through the load are switched depending on the polarity of the input signal, and the amplification operation is performed with the same power efficiency as in class B operation.

In addition, the inputs of the first and second inverting amplifiers are balanced when no input signal is applied, and the emitter potential of the driving stage transistor is changed by the output of the first or second inverting amplifier only when an input signal is applied. Because of the similar configuration, the bias stability is also good when there is no input signal.

[Brief explanation of the drawing]

The figure is a circuit diagram of one embodiment of the present invention. 1 and 2...Transistor for drive stage, 3 and 4...Transistor for output stage, 9...Load, 10...Fixed bias circuit, 19 and 20
...first and second inverting amplifiers.

Claims (1)

[Scope of utility model registration request] A drive stage transistor and an output stage transistor connected in an inverted Darlington,
In a single-ended push-pull power amplifier circuit with a fixed bias, the circuit has a resistor connected between the emitter of the transistor for the drive stage and the collector of the transistor for the output stage. or the voltage between the bases is divided into a reference voltage, and the reference voltage is the first voltage.
The voltage at the output terminal of the single-entry push-pull power amplifier circuit is applied to the non-inverting input terminal via a second diode, and the voltage at the output terminal is applied to the reference voltage. A first inverting amplifier that operates in the above cases, the reference voltage being applied to the non-inverting input terminal via a third diode, and the voltage at the output terminal being applied to the inverting input terminal via a fourth diode, and a second inverting amplifier that operates when the voltage at the output terminal is equal to or lower than the reference voltage, the output voltage of the first inverting amplifier being applied to the emitter of the transistor for one drive stage through the first resistor. 1. A power amplifier circuit characterized in that the output voltages of two inverting amplifiers are separately applied to the emitters of transistors for the other drive stage through a second resistor.