JPS61195429A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To shorten an instruction reading time and to promote a processing speed by reading out an instruction from an instruction buffer in case the instruction to be executed has been stored at the instruction buffer. CONSTITUTION:At the outset of instruction code reading cycles, a control circuit 2 checks for an output of an instruction buffer reading signal 29. When the signal 29 is outputted and the instruction code to be executed in the second place is situated within the instruction buffer 20, the instruction code is read from the corresponding address within the instruction buffer 20 and is outputted to an internal bus 10. Successively such an output is housed at an instruction register 6 and is analyzed by an instruction decoder 7 to execute. On the other hand, if the instruction code to be executed is not housed at the instruction buffer, the control circuit 2 outputs a control signal to a memory control circuit 13 to start a memory reading.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field 1 The present invention relates to an arithmetic processing device that reads instructions from a storage device such as a main memory and executes arithmetic processing according to the read instruction code.

[Prior Art] Conventionally, in this type of arithmetic processing device, an instruction program, which is an execution procedure, is stored in the main memory, and the instruction program sequence in the main memory is sequentially stored starting from the address corresponding to the value held in the program counter. Read and execute.

A schematic block diagram of this conventional arithmetic processing device is shown in FIG.

In the figure, 3 is a control circuit that manages the overall control, 4 is an accumulator (hereinafter referred to as ALtJ) that performs arithmetic processing, and 5 is a memory location after an instruction. 6 is an instruction register, 7 is an instruction decoder that analyzes the instructions in the instruction register 6, 8 is a memory address register, 9 is a memory data register, 13 is a memory control circuit, and 14 is a memory for storing program instruction sequences. It is a memory that temporarily stores data generated during one process in an arithmetic processing unit. Then, the program instruction sequence in the memory 14 normally stores the contents of the program counter 5 in the memory address register 8, sends the address data from this memory address register 8 to the memory control circuit 13, and the corresponding data, that is, the program instruction, is stored in the memory address register 8. The instruction code is read into the data register, sent to the instruction register 6, analyzed by the instruction decoder 7, and the analysis result is sent to the control circuit 3, which executes processing according to the analysis result. At this time, the value of the program counter 5 is counted up by one after its contents are stored in the memory address register 8, and when the next instruction code is read, this value counted up by one is stored in the memory address register 8. become.

In this way, each time a certain instruction is executed, the instruction code is stored in memory 1.
4, and when reading this instruction, the address data to the address bus must be output and determined, and then a control signal must be output from the control circuit 3 to the memory control circuit 13. Therefore, the reading time of this instruction is was delaying the analysis execution processing time of other instructions.

In addition, in order to avoid this and speed up processing, a large CP
Pipeline processing is performed in the U device, but
Execution control also becomes complicated.

The configuration also became complicated, leading to higher prices. In this case as well, it is fine if instructions are read from the main memory at consecutive address values, but even if program loose processing is performed in short steps, each time there is a branch instruction (or the instruction code of the next address value) (If the next instruction code is not required), the next instruction code must be newly read from the main memory, which causes a delay in the processing of the CPU.

[Objective] The present invention has been made in view of the above-mentioned drawbacks of the prior art, and its object is to provide a processing unit with a means for storing executed command data of a certain number, and to store a command to be executed next. It is an object of the present invention to provide an arithmetic processing device which shortens instruction reading time by reading instructions to be executed from the means when they are stored in the means, thereby achieving higher processing speed and efficiency.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to drawing F1.

FIG. 2 is a block diagram of an embodiment according to the present invention, in which the same components as in FIG. 1 are given the same numbers, and the description of the same components will be omitted since it will be redundant.

In FIG. 2, reference numeral 2 denotes a control circuit that manages the overall control, and in the control circuit 2, a built-in microprogram is selected according to the analysis result of the instruction to be executed analyzed by the instruction decoder 7, and corresponds to instruction processing. Output of various signals,
Then, reading 1 determination processing of various signals is executed. Here, it goes without saying that the control circuit 2 is not of the microprogram built-in type, but may be formed entirely of logic circuits.

Further, 20 is an instruction buffer for sequentially storing instruction code strings read from the memory 14.

The instruction buffer can be read/written at high speed, and read/write data is exchanged via the internal bus 10. That is, the write data to the instruction buffer 20 is sent from the memory data register 9 to the internal bus IO, and the address value stored in the instruction buffer 20 at this time is given as P address data 26 by the program counter 5. Further, the read data is transferred to the internal bus 10, and the output data is given to the instruction register 6 via the signal @30 as necessary, and is directly stored in a register (not shown) or the like as necessary. The lower address E of the program counter value, which is the instruction value of the P address data 26, is selected and output to the instruction buffer 20.

-7j21 is the start program address holding M8 (hereinafter referred to as SPC) that holds the start address in the memory 14 of the instruction code string stored in the instruction buffer 20; 22 is the memory 1 to be stored next in the instruction buffer 20;
These 5PC21 and EPC are final program address holding units (hereinafter referred to as EPC) that hold the address values of
The data stored in the PC22 is set from the P address data 26 to the 5PC21 via the comparison circuit S23, or to the EPC22 via the comparison circuit E24.

The relationship between the 5PC 21 and EPC 22 and the instruction buffer 20 is shown in FIG.

As shown in FIG. 3, the 5PC 21 holds the first storage position of the instruction string stored in the instruction buffer 20, and the last storage position +1, that is, the instruction corresponding to the position indicated by the program counter 5 to be stored next. EP the position of buffer 20
It is held by C22. The shaded area in FIG. 3 is the area where valid instruction code strings are stored.

When the instruction code string is stored for the capacity of the instruction buffer 20, the first stored instruction code at the 5PC21 position is deleted, the contents of 5PC21 are changed to the next instruction buffer 20 position, and this is the new EPC22. becomes the indicated position,
An empty area is created and a new instruction code is stored.

Also, 23 and 24 in Figure 2 are 5PC21 and EP
C22 is compared with the instruction code to be read next from the memory 14, that is, the address value indicated by the program counter 5, and it is determined whether the instruction code corresponding to the indicated address value is stored in the instruction buffer 20. They are a comparison circuit S and a comparison circuit E. Comparison circuit S23 compares P address data 26 (all address data of program counter 5) and data of 5PC21, and (SPCI≦L
P address], outputs S output 27.

Further, the comparison circuit E24 compares the P address data (all address data of the program counter 5) 26 and the data of the EPC22.

If LEPcI≧LP address, S output 28 is output. Both the S output 27 and the S output 28 are input to the AND circuit 25, and when both outputs are present, that is, when the instruction code to be read by the program counter 5 is stored in the instruction buffer 20, the instruction buffer is read. A signal 29 is output.

The program instruction read processing and instruction execution processing of this embodiment having the above configuration will be described below with reference to the flowchart of FIG. 4.

The control circuit 2 outputs the instruction buffer read signal 2 in step 41 at the beginning of the instruction code read (memory access) cycle.
9 is output or not, that is, [SPC]≦[PC]
< [Check whether it is EPCJ or not. At this point, the instruction buffer read signal 29 is output, and if the next instruction code to be executed is in the instruction buffer 20, step 42 is performed.
The instruction code is read from the corresponding address in the instruction buffer 20 (in this embodiment, the address value indicated by the lower address value of the program counter 5), and the instruction code is read out from the internal bus 10.
Output to. The storage address of the instruction buffer 20 may be a unique address value instead of the lower address E of the program counter 5.

Then, in step 43, the program counter 5 is incremented by one, and in the following step 44, the instruction code output to the internal bus 10 is stored in the instruction register 6, the instruction decoder 7 analyzes the instruction code, and the control circuit 2
The corresponding process is executed. Here, if the instruction code output to the internal bus 10 is the calculation data or data transferred to the register, this instruction code may be changed to
It is set to LU4, a register (not shown), etc.

Necessary processing will be executed. Then, the process returns to step 41 again to execute the reading process of the primary instruction.

If the instruction code at the memory 14 location specified by the program counter 5 to be executed at step 41 is not stored in the instruction buffer 20, the process proceeds to step 45;
The contents of the program counter 5 are set in the memory address register 8, and in the following step 46, the control circuit 2 outputs a control signal (memory read start signal) to the memory control circuit 13. Then, in step 47, the control circuit 2 compares the value of the program counter 5 and the value of the EPC 22 in the comparator circuit E24, and if the two values match, the match signal 30 is outputted, so this match signal 30 is output. When the match signal 30 is input, that is, when the previously executed instruction is not a program branch instruction, the process advances to step 48 to check whether the instruction buffer is full. If it is full here, step 4
The process proceeds to step 9, where the content specified by the 5PC21 is cleared, and the subsequent step 50 increments 5PC2,1 by one, and the process proceeds to step 52.

10,000 If the instruction buffer 20 is not full in step 48, the process advances to step 52. Here, whether or not the instruction register 20 is full is determined by LEPCI +1 (the specified position of the next instruction buffer specified by the EPC) in this embodiment.
However, if the address of the instruction buffer 20 is not completely circular, for example, shift the instruction code string of the instruction buffer 20 by one, discard the oldest code string, and change the address of 5PC21. It may be controlled to advance by one.

On the other hand, if the result of the previous instruction processing in step 47 is a program branch instruction to an instruction code string other than the instruction code string stored in the instruction buffer 20, the process proceeds to step 51, and the instruction buffer 20
5P to invalidate (clear) all stored instruction sequences in 0
Program counter (PL) 5 in C21 and EPC22
Stores the contents of.

The process then proceeds to step 52, in which the instruction code from the memory 14 that has been read out and set in the memory data register 9 is transferred to the internal bus in accordance with the memory 14 reading start command instructed to the memory control circuit 13 in step 46. 10
is stored in the instruction buffer/20 via the . Then, in step 53, the program counter 5 is incremented by one,
In the following step 54, the incremented value of the program counter 5 is stored in the EPC 22. The process then proceeds to step 44.

As explained below, according to this embodiment, since the instruction code read from the memory 14 is stored in the instruction buffer 20 in the CPU, execution is performed in a short processing loop (in most cases, the instruction code is executed in a short processing loop). ), this process can be executed simply by reading the instruction code in the instruction barrage 20 without requiring access to the memory 14, and during this time the address bus, data bus, etc. are occupied, and the memory 14 is occupied. You can also reduce the amount of time you spend doing it.

This not only improves the processing time of the CPU itself in the car! DMA transfer (tie-left memory access transfer) between the secondary I10 device and the memory can also be performed very efficiently and in a short time.

Moreover, even if the processing according to this embodiment is executed, no changes are required to the program, and the great effect of increasing the processing speed of the program can be obtained.

Effects As described above, according to the present invention, it is possible to provide an efficient arithmetic processing device that can speed up the program processing time without requiring any changes to the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an instruction reading processing section of a conventional arithmetic processing device. FIG. 2 is a block diagram of an embodiment according to the present invention. FIG. 3 is a diagram showing the relationship between the instruction buffer and 5PC1EPC of this embodiment. Figure $4 is a flowchart showing instruction analysis and instruction processing in this embodiment. In the figure 2.3...Control circuit, 5...Program counter, 6...Instruction register, 7...Instruction decoder, 1
0... Internal path, 13... Memory control circuit, 14.
...Memory, 20...Instruction buffer, 21...SP
C, 22... EPC123, 24... Comparison circuit. Patent applicant Canon Co., Ltd. Figure 3 Figure 4

Claims (2)

[Claims] (1) An arithmetic processing device that reads an instruction code from a storage means and executes arithmetic processing according to the read instruction code, an instruction storage means that sequentially stores an instruction code string to be read and executed from the storage means, and the instruction address storage means for storing address values of the storage means that have read the first and last instruction codes stored in the storage means;
determination means for determining whether or not an instruction code to be executed next is stored in the instruction storage means; when the determination means determines that the instruction code is stored, the instruction code is read from the instruction storage means; An arithmetic processing device characterized by executing. (2) If the instruction code read from the storage means and executed is an instruction that branches to an instruction code other than the instruction code stored in the instruction storage means, a new instruction code from the branch instruction is stored in the instruction storage means, and the previously stored instruction code is The arithmetic processing device according to claim 1, wherein the arithmetic processing device clears the information.