JPS61190647A - Data processor - Google Patents

Abstract

PURPOSE:To make it possible to connect a low-speed and large-capacity memory by inserting a latch having the data holding function between a buffer connected to a CPU and a memory. CONSTITUTION:An address (a) of a CPU1 is connected to memories 4A and 4B, a buffer 3C, and a decoder 6A, and the buffer 3C is connected to a memory 4C and a decoder 6B through a buffer 3D, and data (b) is connected not only to memories 4A and 4B but also to the memory 4C through buffers 3E and 3F and latches 5A and 5B. The access time of memories 4A, 4B, and 4C is made shorter than that of the CPU1. In case of write to the memory 4C, data is written in the latch 5A and just preceding dummy data is written in the memory 4C simultaneously, and the same operation is repeated once more, thereby writing normal data in the memory 4C.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to data transmission between microprocessors and memory.

[Technical background of the invention and its problems] In recent years, many devices and products using microprocessors (hereinafter referred to as CPUs) have been seen in all fields. The CPU normally operates with the memory 10 connected to it, and not only accesses the memory 10 (writes data, reads data), but also manages system devices including the CPU itself.

Recently, high-speed CPUs have been used to increase the processing speed of systems managed by the CPU. cpu
The CPU operates in synchronization with a clock, and the higher the clock frequency, the faster the CPU. On the other hand, similar to CPUs, the speed of memories, which are peripheral elements, has been increased, and an increasing number of devices have shortened access time T1, which is the time required to read data from the memory and the time required to write data to the memory. However, in general, many high-speed memories have small capacities, and many large-capacity memories are still slow.

When connecting low-speed, large-capacity memory to a high-speed CPU,
It is necessary to make the CPU access time T2 longer than the memory access time T1, and an input line is connected to the CPU to adjust the length of the access time T2. ,R
T2 for the time that the EADY signal) is input.
For example, by making it longer.

However, as described above, since the CPU is synchronized with the clock, the signal input to its input line must be input at a certain timing with respect to the clock.

For example, as shown in FIG. 2, the READY signal generator 2A and the memories 4A and 4B are connected to the CPUI, and the READY signal generator 2B and the memory 4C are connected via the buffers 3A and 3B and the buffers 3C and 3D. Consider the case where the address is connected to data in the memory via buffers 3E and 3F. It is not uncommon for buffers to be inserted between signals, such as in many cases where data transmission and reception between systems is performed via buffers to protect against noise.

Now, when controlling the length of the CPUI access time T2 from the READY signal generator 2B, the buffer 3A
, 3B signal delay due to T3. T4 and the output of the READY signal generator from the clock (hereinafter, fllliA
Ts is the maximum time delay until the output of the DY signal
, the CPU setup time after inputting the READY signal T6, the sum of T3 to T5 must be below a certain value, and if it exceeds a certain value, normal writing and reading to the memory cannot be performed. In the state that C
When PU 1 accesses memories 4A and 4B, memory 4A.

The access time T1 of the memory 4B should be T1≦T2 compared to the access time T2 of the CPU i, but the access time T1 of the memory 4C! Buffer 311! , considering the delay time Tr and Ta when passing through 3F, T1≦T2−(
Tt+T a ).

As a solution, there is a method of lowering the clock frequency and lengthening the CPU access time T2 in order to increase T2, but this reduces the processing speed of the entire system managed by the CPU. There is also a method of using high-speed memory to reduce the memory access time T1, but high-speed memory generally has a small capacity, and if you want to increase the capacity, the number of memories increases and the implementation efficiency decreases. This also leads to a decrease in reliability due to the increase in the number of parts.

[Objective of the Invention] The object of the present invention is to solve the problem that when a plurality of memories are connected to a high-speed CPU and buffers are provided between the CPU and several memories, it is impossible to control the access time of the CPU using the READY signal. The object of the present invention is to provide a data processing device that can connect a low-speed, large-capacity memory even in the case of a large-scale storage device.

[Summary of the Invention] When a buffer exists between a high-speed CPU and memory, the present invention inserts a latch between the buffer and memory.

By accessing twice in succession, C
Even if it is impossible to control Pu access time, it is possible to connect low-speed, large-capacity memory without lowering the CPU frequency or using high-speed memory to guarantee memory access time. It is something.

[Embodiments of the invention] An embodiment of the present invention is shown in FIG.

The CPU has input/output functions for address a, data b, memory write signal (hereinafter referred to as ■ signal) c, memory read signal (hereinafter referred to as MR multiplication signal) d, and data b. Address a is the memory 4A, 4B, buffer 3
c, connected to decoder 6A. Also, buffer 3C,
It is connected to the memory 4C and decoder 6B through 3D.

Data b is similarly connected to memories 4A and 4B, or to memory 4C through buffers 3E and 3F and latches 5A and 5B. The decoders 6A and 6B select which memory to access from address a, and send a chip selection signal (hereinafter referred to as C5 signal) to that memory.
1 ne 2. Output a3.

In the above configuration, the access time Tt of the memories 4A, 4B, and 4C is TI with respect to the CPUI access time T2.
≦T2.

When writing from CPU to memory 4A, cput outputs address a, data b, and MV signal. The address a is the address of the memory 4A, and the C5 signal e! selected by the decoder 6^ is the address of the memory 4A. Data b is written into the memory 4A from the MV signal. In the case of reading, a VR multiplied signal is output instead of the signal C, and data b in the memory 4A is read. The same thing can be said about memory 4B.

At this time, no problem arises in terms of processing speed for the system including the CPUI and memories 4A and 4B.

When writing to memory 4C, C of decoder 6B
The memory 4C is selected by the 3 signal e3, and the old CPU attempts to write to the memory 4C, but the data from the CPUI is written to the controller 5A. At this time, since the access time to the latch is extremely short, no speed problem occurs in accessing the latch.

On the other hand, the memory 4C has 1 which the catch 5A is currently latching.
The previous dummy data is written. By repeating the same operation once more, normal data is written into the memory 4C. In the case of reading as well, since data is latched once in the latch 5B, it is necessary to repeat the same operation twice.

Here, by writing and reading by accessing twice, the delay due to buffers 3A and 3B is included in the first access, and the access time TI of memo 1J4c is different from the access time T2 of CPUI, even if T1≦T2. If so, there is no need to make memory 4C a high-speed memory,
A large-capacity, low-speed memory that satisfies T+ST2 becomes available.

Note that unidirectional drivers are used for the buffers 3A, 3B, 3C, and 3D, and bidirectional transceivers are used for the buffers 3E and 3F. Furthermore, flip-flops can generally be used for the latches 5A and 5B.

[Effects of the Invention] As described above, according to the present invention, a plurality of memories are connected to a high-speed CPU, and there are buffers between the several memories and the CPU, and when the READ'/ signal is unavailable, In order to guarantee the memory access time, it becomes necessary to increase the speed of the memory by the delay time of the buffer, but by inserting a latch between the buffer memories and performing two consecutive accesses,
It is possible to use a low-speed, large-capacity memory without the need to speed up the memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data processing apparatus showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional data processing apparatus. 1...cpu, 2A-2B...READY signal generator. 3A to 3F...Buffer, 4A to 4C...Memory. 5A, 5B...Latch, 6A, 6B...Decoder. (7317) Representative Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2

Claims (1)

[Claims] In a data processing device having a memory connected to a microprocessor via a buffer, a latch with a data retention function is inserted between the buffer and the memory, and the memory is accessed continuously. A data processing device characterized in that a low-speed, large-capacity memory can be connected to a processor via the buffer.