JPS61183787A - Data variation detecting circuit - Google Patents

Abstract

PURPOSE:To detect quickly a variation of a data by comparing new and old data by a harware, comparing its difference, generating an interruption if a variation occurs, and requesting a transfer suspension to a CPU. CONSTITUTION:When reading out a memory 1 by a CPU, a memory selecting signal inversion MS and a reading-out signal inversion RD become L, a bus buffer 4 makes a signal pass through to the right from the left, and the contents of the memory 1 are sent out onto data buses D0-D3. When executing write to the memory 1, a data sending-out signal DT/inversion R becomes H, and a signal ALE appaering in the beginning of a machine cycle becomes H. Therefore, an output signal SA of an AND gate 7 becomes H, and an output signal Qa of D-flip-flop 5a becomes H only at 1 clock time. In this way, the bus buffer 4 cuts the connection of the memory 1 and the data buses D0-D3. Also, read-out is requested to an inversion RD terminal of the memory 1 by an inversion output signal Qa of a D inversion flip-flop 5a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that detects a change in an input signal and performs data processing corresponding to the change, and particularly relates to a circuit that detects a change in an input signal and performs data processing corresponding to the change.
The present invention relates to a change detection circuit applied to a relatively small-scale data processing system using an input/output processing circuit such as a programmable controller.

[Conventional technology]

A conventional program (8088
compliant) is shown below, and the flowchart of this program is shown in Figure 3.

(1) MOV CX, 1lu (2) MOV SI, 1lv (3) NOV DI, key W (4) NOV AL, (SI) (5) C
MP AL, CDI) (8) JNZ r
5yori J (7) INC5I (8) 18CDI (13) LOOP (1G) NOV CX, l1u (11) M
OV Sl, Kurev (12) MOV DI, Han w (13)
MOV AL, (Sl) (14) NOV
(DI), AL (15) INC5l (lEt) INCDI (17) LOOP In other words, the above program: (1) Doors the number of bytes U to the general-purpose register CX (here used as a repeat counter), and (2) sets the address V. (3) Process address W as index register DI (31), (4) Transfer register S to lower 8 bits AL of accumulator.
(5) Subtract the contents of address W stored in register DI from accumulator AL.

(6) If it is not zero, the processing program rsyoriJ (
Process 32.33), (7) add 1 to address V, which is the content of register SI, and (8) add 1 to address W, which is the content of register DI.

(8) Return to step (4) and loop for the number of bytes U stored in register Cx (processing 30° (10)
Same as (1), (11) Same as (2).

(12) Same as (3) (processing 35), (13)
Same as (4) (Process 36 to store the contents of the 10 accumulator AL at the address W stored in the register DI).

(15) Register S! Add 1 to addressma, which is the content of .

(18) Add 1 to address W, which is the content of register DI, and (17) return to step (1G) and loop by the number of bytes U (processing 37). ”, steps (lO) to (17) are “transfer” processing.

This indicates that U bytes are transferred from address V to address W.

[Problem that the invention seeks to solve]

However, in such a conventional example, as the number of input points increases, the number U of bytes to be transferred increases, so there is a problem that the execution time becomes longer.

An object of the present invention is to provide a circuit that solves these problems.

[Means for solving problems]

In order to solve the above problems, the present invention compares the old and new data using hardware when overwriting and updating the previous data with new data, stores the difference, and issues an interrupt if there is a change. The purpose is to enable data changes to be detected quickly by generating a request to the CPU and requesting the CPU to interrupt the transfer.

[For production]

As a result, the conventional process of "verifying" and then "transferring" can now be done by just "transferring" processing. That is, the transfer processing part of the above program [steps (lO) to (
17)], the processing speed is greatly improved.

〔Example〕

A specific embodiment of the present invention will be described below with reference to FIG.

1 is memory, 2 is EXOR gate, 3 is 3-state output D flip-flop (eg LS 374), 4 is bus buffer (eg LS 245), 5a, 5
b is a general-purpose D flip-flop (for example, LS 74);
088) The bus is set to 4 bits for simplicity.

Now, when the CPU reads the memory l, the memory select signal MS and the read signal RD become "L", and the bus buffer 4 passes the signals from left to right, and the data buses D0 to D3
Sends the contents of memory l upwards.

When writing to memory l, the data sending signal DT/R becomes "H", and the signal A that appears at the beginning of the machine cycle
LE becomes "H". Therefore, the output signal SA of the AND gate 7 becomes "H" and the output signal Qa of the D flip-flop 5a becomes "°H" for l clock time.
” Disconnect from D3.

Also, a read request is made to the sub-terminal of the memory 1 using the inverted output signal Qa of the D flip-flop 5a. The content (previous value data) read by this is compared with the current value data on data bus D, -03 by EXRO gate 2, and if there is a difference, an interrupt is sent to the CPU by the output INT of NOR gate 6 to start processing. interrupt. Note that the data of the bit with the difference ' is stored in the D flip-flop 3.

At the next clock time CP, the path buffer 4 gives the signal of the data bus Do-D3 to the memory 1, and the output C of the D flip-flop 5b becomes the WR multiplied signal to the memory 1.
CPU data is written to memory 1. The difference bit data can be read by the CPU in an "interrupt handling routine" by issuing a signal Iπ. That address is the content of the index register DI of the CPU. As a result, in the present invention, what was conventionally checked and then transferred is performed in just one transfer process, as shown in the flowchart of FIG.

〔Effect of the invention〕

As described above, according to the present invention, in a system that processes a large number of input signals, the processing speed can be greatly improved, and the software can also be shortened, which is a great effect.

[Brief explanation of the drawing]

FIG. 1 is a specific embodiment of the present invention, FIG. 2 is a flowchart of the operation of the present invention, and FIG. 3 is a flowchart of a conventional example. 1--- ME%, 2--- EXOR
Gate. 3, 5a, 5b-=D7 lipflop. 4-m-bus buffer, 6----NOR gate. 7---AND gate. Figure 3

Claims (1)

[Scope of Claims] A memory that stores data on a data bus, and after disconnecting the data bus and the memory and reading the previous value data already stored in the memory, disconnecting the data bus from the memory and then connecting the data bus and the memory again. control means that connects a memory and writes current value data on the data bus into the memory; and when the previous value data is read from the memory by the control means, the previous value data and the current value data on the data bus are written. A data change detection circuit comprising a comparison means for comparing the current value data and, if there is a difference, storing the bit and interrupting a CPU.