JPS6118175A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6118175A JPS6118175A JP59137139A JP13713984A JPS6118175A JP S6118175 A JPS6118175 A JP S6118175A JP 59137139 A JP59137139 A JP 59137139A JP 13713984 A JP13713984 A JP 13713984A JP S6118175 A JPS6118175 A JP S6118175A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- stepped portion
- width
- mask
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 230000005465 channeling Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010407 anodic oxide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having non-planar bodies, e.g. having recessed gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、Ｍ’Ｏ５型半導体装置に係り、特に超高集積
回路で必要な微細半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an M'O5 type semiconductor device, and particularly to a microscopic semiconductor device required for ultra-highly integrated circuits.
超高集積回路の発展とともに、半導体素子、配線等の微
細化への要求が増加している。ところが、それらを今の
ままで最小寸法１〜１．５ μｍ以下に微細化するには
問題が多い、ＭＯ８型素子では。With the development of ultra-highly integrated circuits, the demand for miniaturization of semiconductor elements, wiring, etc. is increasing. However, with MO8 type elements, there are many problems in miniaturizing them to a minimum dimension of 1 to 1.5 μm or less.
立体化による微細化の可能性を持つ例として、素子を７
字の溝に形成するものがあるが、自己整合ではないこと
、溝が深くないこと等の理由で飛躍的な微細化は望めな
い〔例えば原撤外３名編、超ＬＳＩプロセスデータハン
ドブック（サイエンスフォーラム）Ｐ、２８．図−２０
〕。As an example of the possibility of miniaturization through three-dimensionalization, the element is
However, dramatic miniaturization cannot be expected because the grooves are not self-aligned and the grooves are not deep. Forum) P, 28. Figure-20
].
本発明の目的は、ゲート電極幅が１μｍ以下の微細ＭＯ
８型半導体装置を提供することにある。The purpose of the present invention is to form a micro MO with a gate electrode width of 1 μm or less.
An object of the present invention is to provide an 8-type semiconductor device.
本発明は、ＭＯ８素子をＳｉ基板上に設けた段差部に形
成することにより、上記微細化を達成しようとするもの
である。即ち、段差がある下地上に金属膜を被覆性よく
堆積させ、反応性イオンエツチングで除去しようとする
と、段差部に金属膜が残るという現象を利用して、ＭＯ
Ｓの微細ゲート電極を形成するものである。以下、実施
例で更に詳細に説明する。The present invention attempts to achieve the above-mentioned miniaturization by forming an MO8 element on a stepped portion provided on a Si substrate. In other words, if a metal film is deposited with good coverage on a substrate with steps and then removed by reactive ion etching, the metal film remains on the steps.
This is to form a fine S gate electrode. Examples will be described in more detail below.
第１図に示すようにＰ型Ｓｉ基板６上に高さ０．５
ｐｍの段差を設け、厚さ２０ｎｍの５ｉ（ｂｌを熱酸化
により形成する。次に、化学蒸着法により、Ｗ（タング
ステン）を０．５ μｍ厚堆積させ、ホトレジスト等
のマスクなしの状態で、ＳＦｓを用いた反応性イオンエ
ツチングにより平坦部のＷを除去する。そうすると、段
差部に高さ０．５μｍ、底辺０．３ μｍの三角形の
断面形状を有する電極２ができる。ここでイオン打込み
で、チャネリングが起こる場合には厚さ５０ｎｍのＳｉ
ｎｇがＷ陽極酸化膜をＷ上に形成させて、チャネリング
を阻止する。As shown in FIG.
Steps of pm are provided, and 20 nm thick 5i (bl) is formed by thermal oxidation. Next, W (tungsten) is deposited to a thickness of 0.5 μm by chemical vapor deposition, and without a mask such as photoresist, The W on the flat part is removed by reactive ion etching using SFs. Then, an electrode 2 having a triangular cross-sectional shape with a height of 0.5 μm and a base of 0.3 μm is created at the stepped part. , if channeling occurs, a 50 nm thick Si
ng forms a W anodic oxide film on the W to prevent channeling.
この電極２をマスクにして、Ａ ｓ ”イオンを６０
Ｋ ｅ Ｖで、ｌＸ５０″’（！ｌ−”打込み、拡散層
３゜４．５を形成する。ここで、Ｎ“層４は、打込まれ
たイオンの濃度がＮ０層３，５より少なくなっていると
ころである（電極がＮ層４の上で薄くなっているため、
このような構造の拡散の形成が可能である）。なお、電
極形成にはスパッタで形成したＷを使うことも可能であ
るし、 Ｍ ｏ 、 Ｍｏ５ｉｚ 。Using this electrode 2 as a mask, 60 A s ” ions were
At K e V, implant 1×50″(!l−) to form a diffusion layer 3°4.5. Here, N″ layer 4 has a lower concentration of implanted ions than N0 layers 3, 5 (Because the electrode is thinner on the N layer 4,
The formation of a diffusion of such structures is possible). Note that it is also possible to use W formed by sputtering to form the electrodes, and M o , Mo5iz.
ＶＳｉｚ 、 Ｍｏ５ｉａ ／Ｐｏ１ｙＳｉ、 ＷＳ
ｉｚ ／Ｐｏ１ｙＳｉ等を使うこともできる。スパッタ
法で形成したものでよいが、被覆性のよい化学蒸着法が
望ましい。VSiz, Mo5ia/Po1ySi, WS
iz /Po1ySi etc. can also be used. Although it may be formed by a sputtering method, a chemical vapor deposition method with good coverage is preferable.
この素子の特徴は、・第１図で、以下の通りである。 The features of this device are as follows in Figure 1.
１、上から見た電極の幅ａ（ここでは０．３ μｍ）
は非常に狭いのに、実際のチャネル長すはこれよりかな
り長くなっている。これにより、チャネル長が短くなる
ために生ずる特性の変動が少ないままで微細化が達成で
きる。1. Width a of the electrode seen from above (0.3 μm here)
is very narrow, but the actual channel length is much longer than this. As a result, miniaturization can be achieved with little variation in characteristics caused by shortening the channel length.
２、一度のイオン打込みでＮ” 、Ｎ一層を同時に形成
でき、これにより素子動作時の特性の安定化を図れる。2. N'' and N layers can be formed simultaneously by one ion implantation, thereby stabilizing the characteristics during device operation.
即ち、Ｎ＋層５をソースとし、Ｎ０層３をドレインにし
て動作させると、ホットキャリアによる特性の劣化を、
Ｎ一層４があるための電界の低下により、軽減できる。That is, when operating with the N+ layer 5 as the source and the N0 layer 3 as the drain, the deterioration of characteristics due to hot carriers can be reduced.
This can be reduced due to the reduction in the electric field due to the presence of the N layer 4.
３、この電極の上に絶縁保護膜、更にその上に配線を形
成するときには、電極２があるため段差がゆるやかにな
り、上の絶縁膜の被覆性がよくなるとともに、配線の断
線も少なくできる。3. When forming an insulating protective film on this electrode and further wiring on it, the presence of the electrode 2 makes the difference in level gentler, improving the coverage of the upper insulating film and reducing disconnections in the wiring.
以上説明したように、本発明は、ＭＯ８素子の微細化を
容易にしたものであるが、それに加えて、微細化したこ
との悪影響も本発明により軽減できる。As explained above, the present invention facilitates miniaturization of MO8 elements, but in addition, the present invention can also reduce the negative effects of miniaturization.
第１図は、本発明のＭＯ８素子の断面図である。
１・・・２０ｎｍ厚のＳｉｎｇ、２−Ｗ（ａ＝０．３
ｐｍ）、３・・・Ｎ９層、４・・・Ｎ一層、５・・・
Ｎ＋、６・・・Ｐ型べ
ｚ １ 図FIG. 1 is a cross-sectional view of the MO8 element of the present invention. 1...20 nm thick Sing, 2-W (a=0.3
pm), 3...N9 layer, 4...N single layer, 5...
N+, 6...P type bez 1 Figure
Claims (1)
半導体装置。A semiconductor device having electrodes formed in a self-aligned manner along a base step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59137139A JPS6118175A (en) | 1984-07-04 | 1984-07-04 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59137139A JPS6118175A (en) | 1984-07-04 | 1984-07-04 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6118175A true JPS6118175A (en) | 1986-01-27 |
Family
ID=15191728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59137139A Pending JPS6118175A (en) | 1984-07-04 | 1984-07-04 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6118175A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02226772A (en) * | 1989-02-28 | 1990-09-10 | Shiyoudenriyoku Kosoku Tsushin Kenkyusho:Kk | Infeed type insulated gate electrostatic induction transistor and manufacture thereof |
| WO1990013918A1 (en) * | 1989-05-12 | 1990-11-15 | Oki Electric Industry Co., Ltd. | Field effect transistor |
| JP2011061094A (en) * | 2009-09-11 | 2011-03-24 | Furukawa Electric Co Ltd:The | Method of manufacturing field effect transistor |
-
1984
- 1984-07-04 JP JP59137139A patent/JPS6118175A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02226772A (en) * | 1989-02-28 | 1990-09-10 | Shiyoudenriyoku Kosoku Tsushin Kenkyusho:Kk | Infeed type insulated gate electrostatic induction transistor and manufacture thereof |
| WO1990013918A1 (en) * | 1989-05-12 | 1990-11-15 | Oki Electric Industry Co., Ltd. | Field effect transistor |
| US5281547A (en) * | 1989-05-12 | 1994-01-25 | Oki Electric Industry Co., Ltd. | Method for manufacturing a field effect transistor |
| JP2011061094A (en) * | 2009-09-11 | 2011-03-24 | Furukawa Electric Co Ltd:The | Method of manufacturing field effect transistor |
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