JPS6118144A - Semiconductor device measuring apparatus - Google Patents

Abstract

PURPOSE:To provide a semiconductor device measuring apparatus which realizes parallel wafer test for measuring a large amount of unit semiconductor devices at a time by providing an isolation means for isolating devices from the common line when a plurality of probes and a particular probes which are in contact with each electrode of each unit semiconductor device are made conductive to a wafer. CONSTITUTION:For example, when the short-circuit condition 10 exists between the N type diffused layer 2 of the unit semiconductor device 24 to which fixed probes 8a are in contact and the P type substrate 1 of wafer and thereby such unit semiconductor device 24 is judged as a defective unit semiconductor device, an isolation relay 15 is turned OFF and the common line 9 is electrically insulated from the fixed probe 8a for measurement by inserting respectively the isolation relays 12, 13, 14, 15 between the fixed probes for measurement 5a, 6a, 7a, 8a and the common line 9. Accordingly, a voltage having been applied to the common line 9 during parallel wafer test does not give any influence on the P type substrate of wafer through the fixed probe 8a for measurement, aluminum wiring layer 4, N type diffused layer 2 and the short-circuit condition 10. Thereby, the parallel wafer test can be performed normally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device measuring apparatus, and more particularly to a semiconductor device measuring apparatus capable of performing parallel wafer testing in which a large number of unit semiconductor devices are measured at one time.

[Prior art] Conventionally, there has been a device of this type as shown in FIG.

FIG. 1 is a diagram showing an example of the configuration of a parallel wafer test using a conventional semiconductor device measuring apparatus. Although the semiconductor device 20 is composed of a large number of unit semiconductor devices adjacent to each other, only four unit semiconductor devices 21, 22, 23, and 24 are shown here for convenience of explanation. Each unit semiconductor device includes a p-type substrate 1, an N-swelled diffusion layer 2a l 2b, 20, and a silicon oxide film 3 of a wafer to be measured.
a, 3b, 3c, 3d and aluminum wiring layer 4a*4b
*Constructed by laminating 40 layers in layers. Although the fixed measurement probe has a large number of pins, for convenience of explanation, a case will be described in which three pins are brought into contact with each unit semiconductor device. That is, each measurement end of a set of fixed measurement probes (5a, 5b, 5C) is connected to a set of aluminum wiring II (4814) of a unit semiconductor device 21.
b, 40'). Also, 1
The other end of each set of fixed measuring probes (5a, 5b, 5c) is connected to an external measuring device 11. Other sets of measurement fixed probes (6a, 6b, 60)
(7a l 7b.

70) The same goes for tweeting (sa, 8i 8c). At least one of the set of fixed measurement probes on each unit semiconductor device is connected to at least one corresponding one of the set of measurement fixed probes on the adjacent unit semiconductor device by at least one common line. However, for convenience of explanation, here, we will explain the case where one fixed measuring probe on each unit semiconductor device is connected to a corresponding one fixed measuring probe on an adjacent unit semiconductor device by one common line. Show about. That is, the measurement fixed probes 5a+6a and 7a*8a are connected by a common line 9, so that there is one common line 9 between the unit semiconductor devices to be measured. When measuring one unit semiconductor device, four sets of measurement fixed probes (5a
, 5b, 50), (6a, 611°60)l (78
, 7bl 7C) 1 (8a, 8b.

8c) only contacts the unit semiconductor device alone, and the common line 9 does not exist.

However, when measuring the four unit semiconductor devices 21, 22, 23, 24 of the semiconductor device 20 at the same time,
4 sets of fixed measurement probes <58.5b, 5C) 1
(68,6b,θC)1 (7al 7b,70)l
Each set of (8a18b, 80) contacts each of the unit semiconductor devices 21, 22, 23, 24 at the same time, so that one or more common lines 9 are present. When measuring a semiconductor device using a negative voltage applied to the p-type substrate 1 of the wafer, a negative voltage is applied to the p-type substrate 1 of the wafer, and a positive voltage or angle is applied to the fixed measurement probe. A voltage in the direction or a voltage at the GND level is applied. That is, when measuring one unit semiconductor device, four sets of measurement fixed probes (5a, 5b, 5
c ) l (6a, 6b, 60) 1 (7a, 7b
, 7C) 1 (8a, 8b, 8c), a positive direction voltage, a negative direction voltage, or a GND level voltage is applied individually to any one of the sets and the measurement is performed. On the other hand, when simultaneously measuring four unit semiconductor devices, four sets of measurement fixed probes (5a l 5b I 5C) l
(6a, 5b, 6C)l (7a, 7b, 70),
(8a, 8b, 80) are simultaneously connected to a positive direction voltage or a negative direction voltage or to GND.
A level voltage is applied to perform a measurement, ie, a parallel wafer test. Therefore, during a parallel wafer test, for example, if there is a short circuit 10 between the N-type diffusion 112 of the unit semiconductor device 24 and the P-type substrate of the wafer, the common line 9 will be connected to the measurement fixed probe 8a.
, aluminum wiring layer 4. N-type diffusion 1!2. Short condition [10
The three sets of Fixed probe for measurement (5a, 5b * 5c)
+ (6a, 66, 60) l (7a l 7b,
In some cases, the measurement of each unit semiconductor device in step 7C) was not carried out properly.

Parallel wafer testing using conventional semiconductor device measurement equipment is carried out in the manner described above, so that unit semiconductor devices that should be judged as "good" are sometimes marked as "defective".
There was a drawback that it could be judged as

[Summary of the Invention] This invention was made in order to eliminate the drawbacks of the conventional ones as described above.Therefore, the main purpose of this invention is to provide a parallel method that does not cause measurement errors and has low test costs.
An object of the present invention is to provide a semiconductor device measuring device capable of performing wafer testing.

To summarize the present invention, a semiconductor device includes a plurality of unit semiconductor devices, includes a plurality of probes that are contacted with each electrode of each unit semiconductor device, and at least one probe on each unit semiconductor device, The corresponding at least one probe on the adjacent unit semiconductor device is connected to the at least one common line, and the at least one probe on each unit semiconductor device is separated from the at least one common line. means is provided, and when one of the at least one probes on each unit semiconductor device is electrically connected to the wafer in testing the circuit of the wafer, the probe separating means is operated to separate the probes. The semiconductor device measuring apparatus is configured to separate the semiconductor device from the at least one common line.

The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the configuration of a parallel wafer test using a semiconductor device measuring apparatus according to an embodiment of the present invention. In the detailed description of this invention, the description of parts that overlap with the description of FIG. 1 will be omitted as appropriate.

The configuration of the parallel wafer test according to the present invention differs from the configuration of the conventional parallel wafer test shown in FIG. 1 in the following points. In order to electrically isolate the four measurement fixed probes 5al 6a, 7a+ 8a connected by the common line 9 from the common line 9, a separation relay 12 is provided between the measurement identification probe 5a and the common line 9. A separation relay 13 is installed between the measurement fixed probe 6a and the common line 9, and a separation relay 13 is connected between the measurement fixed probe 7a and the common line 91Il.
A separation relay 14 is inserted between the measurement fixed probe 8a and the common line 9, and a separation relay 15 is inserted between the measurement fixed probe 8a and the common line 9.

In this way, each measurement fixed probe 5a, 6a.

Separation relay 1 is installed between 7a, 8a and common line 9.
By inserting 2.13.14.15, for example, a short state 10 is created between the N expansion diffusion 12 of the unit semiconductor device 24 and the p-type substrate 1 of the wafer, which the fixed measuring probe 8a is in contact with. Therefore, the moment this unit semiconductor device 24 is determined to be a defective unit semiconductor device,
The separation relay 15 is turned off to electrically isolate the common line 9 and the measurement fixed probe 8a. Therefore, the voltage applied to the common line 9 during parallel wafer testing is applied to the measurement identification probe F3a, the aluminum wiring layer 4. N
Swelling diffusion layer 2. Through the short state 10, the wafer p
Since the shaped substrate 1 is no longer affected, the parallel wafer test can be performed normally.

In the above embodiment, a separation relay was inserted between the fixed measurement probe and the common line, but instead of this, an SSR
An electrical isolation device such as a solid state relay (solid state relay) or a photocoupler may be inserted.

Further, in the above embodiment, the case where the semiconductor device includes the p-type substrate 1 and the N-swelled diffusion layer 2 of the wafer was explained.
The semiconductor device may include a wafer N-type substrate and a p-swelled diffusion layer.

Furthermore, in the above embodiment, the case where four unit semiconductor devices of the semiconductor device are measured at the same time and the case where the measurement is performed using one common line 9 has been explained, but the number of unit semiconductor devices measured at the same time is two or more. The number of common lines 9 may be any number, and the number of common lines 9 may be one or more.

[Effects of the Invention] As described above, according to the present invention, a semiconductor device is made up of a plurality of unit semiconductor devices, is provided with a plurality of probes that are brought into contact with each electrode of each unit semiconductor device, and has a plurality of probes on each unit semiconductor device. at least one probe on each unit semiconductor device is connected to a corresponding at least one probe on an adjacent unit semiconductor device with at least one common line, and the at least one probe on each unit semiconductor device is connected to the at least one probe on each unit semiconductor device. A separating means is provided between each common S, and when there is one of the at least one probe on each unit semiconductor device that is electrically connected to the wafer in testing the circuit of the wafer, the separating means of this probe is separated. The probe was operated in such a way that it was isolated from the at least one common line, so a parallel connection without false measurements could be achieved.
Can perform wafer testing. Therefore, it is possible to prevent economic losses associated with incorrect measurements in which a unit semiconductor device that should be determined to be a "defective product J" is determined to be a "defective product J," and the test cost is lower than when testing each unit semiconductor device. can do.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a parallel wafer test using a conventional semiconductor device measuring apparatus. FIG. 2 is a diagram showing the configuration of a parallel wafer test using a semiconductor device measuring apparatus according to an embodiment of the present invention. In the figure, 1 is the P-type laminate of the wafer, 2 is the N-swelled diffusion layer,
3 is silicon oxide film, 4 is aluminum wiring II! . 5a+ 5b, 5c+ 5a, eb, 5c, 7a+ 7
b, 7c l 8a + 8b * 9c is a fixed probe for measurement, 9 is a common line, 10 is a short-circuit condition between the N expansion diffusion layer and the P type number plate of the wafer, 11 is an external measurement device,
12, 13, 14, and 15 are isolation relays; 20 is a semiconductor device; 21; 22, 23, and 24 are unit semiconductor devices. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] An apparatus for testing a circuit on a wafer of a semiconductor device, wherein the semiconductor device is composed of a plurality of unit semiconductor devices adjacent to each other, and each unit semiconductor device includes a wafer and a plurality of elements formed on the wafer. and a plurality of electrodes are provided on the outer surface of each unit semiconductor device, and a plurality of probes are provided in contact with each electrode of each unit semiconductor device, and each probe of the plurality of probes is provided with a plurality of electrodes. and an external measurement device that measures the circuit of the wafer by contacting each of the probes with each of the electrodes; at least one common line connecting at least one of the probes to at least one of the corresponding probes on the adjacent unit semiconductor devices; a separating means provided between one common line for separating the at least one probe on each unit semiconductor device from the at least one common line; When the at least one probe on a unit semiconductor device is electrically connected to the wafer, the separating means of the probe is operated to separate the probe from the at least one common line. Semiconductor device measurement equipment.