JPS61181000A - Dynamic rom circuit - Google Patents

Abstract

PURPOSE:To attain a high-speed reading cycle by adding four MOS transistors MOS TR and therefore lowering the level of the voltage of a line to which the drain of a bit line precharging MOS TR is connected and then the level of the precharging voltage of the bit line respectively. CONSTITUTION:The source of a MOS TR 12 is connected to a line connected to the drain of a precharging load MOS TR 5 of a bit line 3. While the drain of the TR 12 is connected to a power supply VDD. Then the gate of the TR 12 is connected to the source of a load MOS TR 26 connected to the VDD. The gate and the drain of a MOS TR 13 are connected to the source of the TR 26 with the source of the TR 13 connected to the drain and the gate of a MOS TR 14 respectively. While the source of the TR 14 is grounded. The level of the voltage of a line connected to the drain of the TR 5 is lowered. Then the bit precharging voltage is reduced to reduce the reading time of a dynamic ROM circuit which is decided by the time during which the voltage of the line 3 is reduced down to an input switching level of a MOS circuit connected to the line 3 from the precharging voltage level.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a dynamic RO of MOS) transistor configuration.
The present invention relates to a means for improving the operating speed of M circuits, specifically ROM circuits.

BACKGROUND ART FIG. 2 shows a conventional dynamic ROM circuit having an N-type and P-type MO8) transistor configuration, in which 16 is a row decoder, 16 is a word line (group), 17 is a bit line (group), 18 is an enhancement type MOS) transistor (hereinafter referred to as MOS Tr), 19 is an enhancement fiMO3Tr120 is an enhancement type MO3
Tr, 21.22, 23, 24°25 are enhancement type MOS Tr. Alt person 2 indicates a part of the word line, and Dl indicates a part of the bit line. φ1. φ2 is an input clock. FIG. 3 is a timing diagram of the circuit of FIG. A predetermined word line width of the word lines 16 based on clocks φ1° and φ2.

The timing diagram shows the change in the voltage of the bit line 2 and the voltage of one of the bit lines 17.

In FIG. 2, word line 16 of row decoder 16 is activated by clock φ1. Regarding a predetermined word line A1#'2 of the word lines 16, when the clock φ1 is "H", the states of each word line A1 and A2 change. In the timing diagram of FIG. 3, the initial state of the word line ON is °゛L''.

When the clock φ1 becomes “H”, the state of the word line width is “
Furthermore, when the cross φ1 becomes ==H for the second time, the state of word line person 1 changes from "H" to "L".Similarly, the initial state of word line A2 changes from "H" to "L". The state is "L", and when clock φ1 becomes "H", the state of word line A1 becomes "L" and does not change.Furthermore, when clock φ1 becomes "H" for the second time, the state of word line A2 changes to "L". It changes from “L” to “H”.

Also, the second enhancement type MOS Tr20
is activated by clock φ1, and all pins a17 are set to “H”.
At this time, the bit line 17 is said to be precharged by the enhancement type MOS transistor 20, and this mechanism is called a precharge mechanism.

Regarding the bit line, when the clock φ is "H", the MOS Tr 20 is not in the on state.

Precharged. In the timing diagram of FIG. 3, the initial state of the bit line is "L", and the clock φ1 is
When it goes to "H", the state of the bit line changes from "L" to "H"
Changes to Furthermore, when the clock φ1 becomes "H" for the second time, the state of the bit line changes from "L" to "H".

Next, when φ1 is activated, the bit line 16 having a current path to OV through the MO3Tr, which has already been turned on due to activation of the word line 16, is discharged. The bit line 1a, in which no transistor is arranged for the accessed word, remains in a precharged state. Looking at the signal on the bit line D1 in FIG. 3, the clock φ
1 goes to °H", A1 goes to "H", A2 goes to °L", MO3Tr21 is not on, MO8Tr22
, 24°25 are in the off state. Next, clock φ2 is “
When it becomes "H", MO3Tr19 turns off, and the bit line D1 creates a current path to Ov through MO8Tr21, which is on, and is discharged.In other words, the read data becomes "L".The clock φ becomes "H" for the second time. ", word line ON becomes "L", word line A2 becomes -H-, MO5Tr21 is turned off, MOSTr22, 24 .
26 is turned on. Next, when the clock φ2 becomes H", the MO3Tr19 is turned on, and the bit line R remains at "H" since there is no current path to Ov. That is, the read data is at "H".

Problems to be Solved by the Invention However, the above conventional dynamic ROM circuit has the following problems:
It has the following problems. That is, when the clock φ1 is active, the bit line 17 of this dynamic ROM circuit
When clock φ2 is activated in a state where all of decide. Therefore, in order to increase the operating speed of the read cycle of this dynamic ROM circuit, M
O3Tr21.22, 23, 24, 25 and MO8T
It is necessary to increase the current driving capability of the current path configured by r19. However, in practice, increasing the current drive capability of an integrated circuit requires MO3Tr19,21.2
This results in an increase in the geometric size of 2,23,24,26, which is not suitable for high density integrated circuits.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide a dynamic ROM circuit that is suitable for high-density integrated circuits and has a fast read cycle operation speed.

Means for Solving the Problems In order to solve the above problems, the present invention connects the source of the first MOS Tr to the line connected to the drain of the precharge load transistor of the pinto line, and OS
The drain of the Tr is connected to the power supply vnn, and the same MOS
The gate of 'rr is connected to the source of the second MOS transistor for load connected to the power supply VDD, and the gate and drain of the third MO5Tr are connected to the second MOS transistor for load.
Connect to the source of the transistor.

The source of the third MO8Tr is connected to the drain and gate of the fourth MO3Tr, and by grounding the source of the fourth MOS Tr, the voltage of the line connected to the drain of the precharge load transistor of the bit line can be adjusted. lower the bit line precharge voltage.

This reduces the read cycle time of the dynamic ROM circuit, which is determined by the time required for the bit line voltage to drop from the precharge voltage to the input switching level of the 108 circuits connected to the bit line.

According to the circuit of the present invention, by lowering the bit line precharge voltage, the read cycle time of a dynamic ROM can be reduced without increasing the geometric size of the MOSTr.

Example FIG. 1 shows an embodiment of the present invention.

1 is a row decoder, 2 is a word line, 3 is a bit line, 4 is an enhancement type MO3Tr, 5i1-enhancement type MO3Tr, 6 is an enhancement type MO3Tr,
7, 8, 9, 10, 11 are enhancement type MO3
Tr, 12, 13.14 are enhancement type MOS
The transistor 26 is a depression type MO3Tr. Person 1. A2 indicates a part of the word line 2, and D2 indicates a part of the bit line 3. Clock φ4. φ2 is the phase waveform shown in FIG. FIG. 3 is a timing diagram of the circuit of FIG. The timing chart shows changes in the voltage of predetermined word lines A, A2 of the word line 2 and changes of the voltage of a predetermined bit line D2 of the pit line 3 due to clocks φ1 and φ2.

The operation of the dynamic ROM circuit configured as above will be explained below.

Connect the source of MO3Tr12 to the line connected to the drain of enhancement type MOS Tr 5, and
The drain of 3Tr12 is connected to the power supply vDD, and MO8T
The gate of r12 is the load transistor 2 connected to vDD.
The gate and drain of MOSTr13 are connected to the source of the load transistor, and the gate and drain of MOSTr13 are connected to the source of the load transistor.
The source of MO3Tr14 is connected to the drain and gate of MO3Tr14, and the source of MO8Tr14 is grounded. According to the circuit diagram in Figure 5, which extracts a part of the circuit in Figure 1, MO3T
The effect of r13,14°12.28 will be explained. As shown in FIG. 5, a depletion type MOS Tr whose gate and source are connected is used as the load transistor 26, and Vl, V2 . If V is the voltage at the point shown in the figure, then M
Since the drain and gate of the OS, 2'Tr 13 and 14 are connected, they operate in the saturation region characteristics of the MOS Tr, and the MO3Tr 26 has a source-gate voltage of V. 8, the source and gate are connected, so it operates at Vo8 = OV, and the threshold voltage of the MOS Tr is set to V, r, and the threshold fluctuation due to the back gate bias effect of the MOS Tr is set to △. If VT, MOS
The operating condition of the Tr is V. Since 8≧vT, v,=vT
, v2-vT+vT+ΔvT=2vT+ΔvT.

The voltage v3 on the output side of MO8Tr12 is MO8T
The voltage applied to the gate of r12 is v2, and M O
Since the operating condition of S Tr is vas≧vT, v3=
v2-vT=vT+ΔvT and null. For example, if vDD is 6V, VT is 1.6V, and Δv1 is 1v, then v,=
1. sv, v2=4v.

vs = 2.51.

Next, in FIG. 1, word line 2 of row decoder 1 is activated by clock φ. Considering the predetermined word line input of word line 2 for 11 people 2, clock φ1 is “H”
When the same word line A1. A change in state of system 2 occurs. In the timing diagram of Figure 3, the initial state of word line ON is @
L”, and the clock φ.

When becomes “H”, the state of word line ON changes from “L” to “H”.
Further, when the clock φ1 becomes "H" for the second time, the state of the word line A1 changes from "H" to "L'." Similarly, the initial state of word line A2 is "L",
When the clock φ1 becomes "H", the state of the word line input 1 becomes "L" and remains unchanged. Furthermore, when the clock φ1 becomes "H" for the second time, the state of the word line A2 changes from "1L" to "1L".
Changes to H'.

The enhancement type MO3Trs in Fig. 1 has a clock φ
, and all bit lines 3 are set to "H". Considering the bit line D2, when the clock φ is "H", the MOS Tr 5 is turned on and precharged. In the timing diagram of FIG. 3, the initial state of the bit line D2 is "L", and when the clock φ1 becomes "H", the state of the bit line D2 changes from "L" to "H". Furthermore, when the clock φ1 becomes "H" for the second time, the state of the bit line D2 changes from "L" to "H". The voltage of the bit heddled line is vT + ΔVT″″c logi, clock ψ
If the H” level of 1 is V.D, then MOS Tr
The operating condition of s is vas≧v, there is a certain temperature, vDD−(v
If T+Δv,r)≧vT, then vT+ΔvT.

In normal processes, this condition holds true.

Next, when clock φ2 is activated, word line 2 has already been activated.
Ov through MO5Tr, which is in the on state due to the activation of
The pit line 3 having a current path to is discharged. Pit lines 3 in which transistors are not arranged for the accessed word remain in a precharged state.

Regarding the pit line D2 in FIG. 3, when the clock φ becomes "H", the word line A1 becomes *)in, the word line input 2 becomes "L", MO5Tr7 is turned on, and MO3Trs, 1o , 11 are in the t7 state. Next, when the clock φ2 becomes 1H', the MOS Tr 6 is turned on, and the pit line D2 is connected to the turned-on MOS
A current path to Ov is created through Tr6 and discharge occurs.

That is, the read data becomes "L". clock φ,
When becomes “H” for the second time, word line input 1 becomes “L”, +7
- The power line A2 becomes “H” and the MO8Tr is off.
MO5Tr8, 10, and 11 are turned on. Next, when the clock φ2 becomes @H, even if the MOS Tr 6 is on, the pit line D2 remains at "H" because there is no current path to Ov. In other words, the read data becomes "H".
"become.

One of the factors that determines the read cycle time is the pit line precharge voltage. In the circuit of FIG. 2, the bit line precharge voltage is vDD-vT, and the first
In the circuit shown, it is vT+ΔvT. Pit line 3 is M
Discharged through OS Tr 6.

The time required for the voltage to drop to a level sufficient for switching of the MO3 circuit in the next stage is short because the precharge voltage of the pit line 3 is low. If vDD is 5y and vT is 1v
, △vT is 2v, and the switching voltage of the next stage (7) M O3 circuit is 1.5v, the time it takes for the bit line precharge voltage to drop to 1.5v is a linear function of time. Approximately, the pit line precharge voltage of the conventional circuit is 4V, and the circuit of the present invention is 3V, so if the conventional circuit is \ :11, then the circuit of the present invention is 0.6. 40%
Time becomes shorter. Therefore, the operating speed of the dynamic ROM read cycle is increased by 40%.

At timing D2 in FIG. 3, T1 indicates the difference in read cycle time between the conventional circuit and the circuit of the present invention.

FIG. 4 shows the relationship between pit line voltage and time in a read cycle of a dynamic ROM.

The read cycle time of the dynamic ROM is the time required for the voltage of the pit line to drop from the precharge voltage to the input switching level of the MO3 circuit connected to the pit line, as shown in FIG. The input switching level of the MO3 circuit is constant from process to process without special design.

For example, in the case of an N-type MOS transistor operating at 5V, the voltage is approximately 1.5V. Further, the discharge curve is determined by the geometrical dimensions of the MOS transistor, and is constant if the geometrical dimensions are constant. From the above, it can be seen that the read cycle time can be shortened by lowering the precharge voltage. FIG. 4 shows the case where the person does not lower the precharge voltage, and B shows the case where the precharge voltage is lowered. It can be seen that the readout time is shorter for B than for humans by T.

The present invention uses the above-described circuit configuration to reduce the read cycle time of the dynamic ROM by reducing the bit line precharge voltage.

21.22, 23.24.25 can be reduced without increasing, and the time required for pit line precharging does not increase, making it suitable for high-density integrated circuits. Generally, when the threshold voltage vT of the MOS Tr increases, the read threshold voltage of the ROM also increases. When the circuit of the present invention is adopted, M O S T
When the threshold voltage vT of r rises, the precharge voltage also rises automatically, which has the advantage of automatically compensating for process variations.

Generally, when the threshold voltage vT of the MOS Tr increases, the read threshold voltage of the ROM also increases.

The circuit of the present invention also has the advantage of being able to compensate for variations in the voltage process of pit line precharging.

Effects of the Invention The dynamic ROM circuit of the present invention newly has four M
By providing an OS Tr, the voltage of the line connecting the drain of the bit line precharge MOS Tr can be lowered, and the bit line precharge voltage can be lowered to speed up the read cycle. In order not to increase the time required.

The increase in chip size is extremely small, making it suitable for high-density integrated circuits, and its practical effects are significant.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a conventional dynamic ROM circuit diagram, Fig. 3 is a timing diagram, Fig. 4 is a characteristic diagram of the relationship between voltage and time of a read cycle, and Fig. 5
The figure is a diagram of main parts of a circuit added in the present invention. 1... Row decoder, 2... Word line,
3...Beep) line, 4...Enhancement fiMO8Tr, 5...Enhancement line)
fiMO3Tr, 12, 13. 14...Enhancement type M OS Tr,
15... Row decoder, 16... Word line, 17... Bit line, 18... Enhancement 1M03Tr, 1s... Enhancement QMOSTr, 20...Enhancement type MO3Tr, 21.22.23. 24.26...Enhancement type MO8Tr
. 26...Depression fiMO3Tr. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] In a dynamic ROM circuit having a MOS transistor configuration, the source of the MOS transistor is connected to a line connecting the drain of a bit line precharge load transistor, the gate of the MOS transistor is connected to a voltage source, and the drain of the MOS transistor A dynamic ROM circuit characterized by being connected to a power supply.