JPS61180590A - Speed controlling method for motor - Google Patents

Abstract

PURPOSE:To eliminate the simultaneous operation of a speed comparison and a filter calculation and to accurately operate both by stopping the calculation when an FG (rotary speed detector) pulse is input if all digital process is executed by a microcomputer. CONSTITUTION:The output of an FG2 mounted in a motor 1 is input to an external interrupt terminal of a one-chip microcomputer 3. The microcomputer 3 compares a motor rotating speed by the FG signal, and calculates to filter a speed error to obtain a motor drive command. The motor drive command is output to a D/A converter 4 as an analog amount, the analog amount is input to a drive circuit 5 to drive the motor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to speed control of motors, and in particular to highly accurate speed control circuits used in recording and reproducing devices, such as head drum motors of VTRs, especially for compensation purposes. It concerns the digitization of filters.

Conventional technology FIG. 9 is a configuration diagram of a conventional speed control circuit.

A signal obtained by a rotation detector 61 (for example, a frequency generator or a rotary encoder, hereinafter abbreviated as FG) attached to the motor 60 is compared with a reference speed by a speed comparator 62 to obtain a speed error signal. This speed error signal is input to the compensation filter 53, used as a motor drive command value, and further passes through the drive circuit 54 to drive the motor 60.

Here, the compensation filter shown in FIG. 7 is often used. Such a filter has a large degree of amplification in the low frequency range, and a control system including such a filter can greatly suppress disturbances in the low frequency range.

Problems to be Solved by the Invention Conventionally, as shown in FIG. 9, a dedicated circuit was required for each motor.

That is, a dedicated speed comparison circuit and a dedicated filter were required. In particular, when a filter is constructed using an analog circuit, a resistor and a capacitor are required, making it difficult to integrate the filter into an integrated circuit. Furthermore, in most recording and reproducing apparatuses, there is more than just one motor, and for this reason, it is desirable to avoid methods that require many dedicated circuits. Additionally, recording/reproducing devices generally require a so-called sequence control circuit that controls the operating state of the device according to the operator's commands, and if the device has many types of operating states, this sequence control circuit can It is necessary to send a large amount of information to the speed control circuit mentioned above, and the number of exchanges of signal lines has increased significantly. This hinders miniaturization of the device.

Means for Solving the Problems In the present invention, in order to overcome these drawbacks of the conventional method, a microcomputer is used to control the speed of the motor in a time-sharing manner, and the filter is digitally processed. It is something.

Function In the present invention, a filter calculation is performed based on the speed error value obtained for each FG pulse edge of the motor, and the operation clock for the filter calculation is a signal having a frequency that is an integral multiple of the FG pulse and synchronized with the FG pulse. It is. By using this operating clock, which has a higher frequency than the speed error, changes in the filter output become smoother, and harmonic components of the clock frequency are greatly attenuated.

Embodiment An embodiment of the present invention will be described based on the drawings. First, the seventh
Consider digitizing the filter shown in the figure. There is a bilinear conversion method as a method for digitizing such a circuit. This is to find H(z) using the original formula A. Note that here τ is the sampling period. H(z) obtained by this conversion is as follows.

Then, the circuit diagram shown in FIG. 8 is obtained. In FIG. 8, 40 is a one sample period delay circuit, 41.degree. 42 is a multiplier, and 43.44 is an adder. The above is an outline of the digitization of the filter. If you digitize it like this,
Since it can be realized by a combination of delayed squaring and addition, it can also be realized by computer software. Furthermore, although this method is a type of approximation, the accuracy of the approximation can be improved by shortening the sampling period τ. Then, the high frequency components of the signal obtained by holding the output at zero order are reduced.

FIG. 1 is a block diagram showing an embodiment of a control system using the method of the present invention. The output of the FG 2 attached to the motor 1 is input to an external interrupt terminal of a one-chip microcomputer (hereinafter referred to as microcomputer) 3. Inside the microcomputer 3, the FG double signal simulator rotation speed is calculated and compared,
The speed error is further filtered to obtain a motor drive command. This motor drive command is outputted to the DA converter 4 as an analog value, and the analog value is inputted to the drive circuit 5.
Drive motor 1.

FIG. 6 is an internal block diagram showing an example of the microcomputer 3 used in this embodiment.
M, data RAM, ALU (Alithmetia L
It has a timer counter, an external interrupt, and a parallel input/output port, and can operate as a computer by itself. Of course, blocks other than those shown in the figure may be provided, such as a serial interface.

FIG. 2 is a timing chart showing the order of operation of each part in this embodiment. When the motor FG pulse rises, speed comparison processing is performed as shown by a. When the speed comparison process is completed, a built-in timer counter starts a timer (arrow b). Furthermore, as shown by arrow C, a filter operation is performed. When a timer interrupt occurs according to the timer set by the arrow, filter calculations are executed as shown by arrows d, e, and f. The above processing is carried out by the motor FG
Repeat each time a pulse is input. In FIG. 2, the sampling frequency of the digital filter is four times the FG frequency, and the filter is executed in synchronization with the FG pulse. In other words, the period of this timer is the sampling period τ
becomes.

3 and 4 are flowcharts showing the processing procedure in the microcomputer 3. FIG. Since the FG pulse is input to the external interrupt terminal, when the FG pulse is input, the flowchart shown in FIG. 3 is executed. First, in block 10, the value of the built-in timer counter is read and the memory T
Store in.

This corresponds to reading the time. Next, in block 11, the value T' read at the previous pulse edge is
Find the difference between this value and the value T read this time.

That is, the pulse period P is calculated. Next block 12
In this step, the difference between the period P and the reference period Pref and the period error are determined. A periodic error is a type of speed error. This speed error is taken as the input signal IN of the filter. Furthermore, in block 13, preparation for the next time is performed by transferring the currently read value T to the previous value T'. That is, by the process shown in block 10゜11.12.13,
This is a speed comparison. Next block 14
, reset the timer counter and restart. Next, in block 15, clear the register (RAfvl) indicating the number of timer interrupts. This is to determine the number of filter operations to be performed at the FG pulse interval.Next, the block enclosed by the broken line Moving on to 16. Block 16 is a filter operation. Block 16
The variables shown in, U, V.

OUT, a, and b correspond to those in FIG. First, in block 17, the input value IN is added to the previous integrated value V and the current integrated value U is obtained. This process corresponds to the process of the cyclic part in FIG. 8, especially the adder 43.

Next at block 18.

Performs a sum-of-products operation. In other words, the coefficient a is added to the current integrated value U.
The previous integrated value V multiplied by the coefficient S is subtracted from the multiplied value V, and the result is set as the filter output OUT.

This is a process corresponding to the acyclic part in FIG.

Next, in block 19, the current integrated value U is transferred to the previous integrated value V. This corresponds to block 40 of FIG.
This is the process corresponding to 1. This completes the filter calculation process. Next, in block 20, the external interrupt, that is, the currently accepted interrupt, is enabled again, and the timer interrupt is enabled, thereby completing the processing of the external interrupt.

FIG. 4 is a flowchart showing timer interrupt processing. When a timer interrupt is accepted, processing of block 30 indicated by a broken line, that is, filter calculation is performed. The content of this calculation is exactly the same as block 16 in FIG. Next, in block 34, a register (RA) indicating the number of timer interrupts is entered.
M), is +1. Then, in block 36, if the number of interrupts is 3 or more, the interrupt processing is terminated,
If the number of interrupts is less than 3, the process proceeds to block 36, where timer interrupts are re-enabled and the interrupt process ends.

The processing in blocks 34, 35, and 36 limits the number of timer interrupts to three.

FIG. 6 schematically shows the processing results by the above filter. In the speed control state, the input signal of the filter, that is, the speed error signal, becomes 0 obtained at a constant period of approximately Rref, that is, as shown in FIG. 5q. Here, the horizontal axis is time.

The vertical axis is the speed error. On the other hand, in this embodiment, the filter output changes at a quarter period τ of Rref, so a waveform as shown in Figure 5 is obtained. Here, the horizontal axis is time, the vertical axis is the filter output value, That is, it is a motor drive command value. As is clear from the fifth diagram, the shorter the sampling period, the fewer harmonic components of the signal. Therefore, the rotation of the motor can also be made smoother.

Further, in this embodiment, only the interrupt processing of the microcomputer 3 has been described, but when the interrupt processing is not being performed, other processing can be performed. Therefore, sequence control processing can be performed at this time. In this case, internal signal exchange is not necessary, especially since it is performed within the same microcomputer.

As described in detail, the present invention realizes motor rotational speed control through all digital processing using a microcomputer, and can realize control of multiple motors according to the Flood Damage Act without increasing the number of dedicated circuits. It is.

Furthermore, in the present invention, the motor FG pulse and filter calculation are synchronized, and since filter calculation is not performed when the FG pulse is input, speed comparison processing and filter calculation do not overlap, and both can be processed with high accuracy. It is.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of a control system using the method of the present invention, Fig. 2 is a timing chart showing the operation order in the embodiment, and Figs. 3 and 4 show the processing procedure in the embodiment. 6 is an input/output waveform diagram of the filter in the same embodiment, FIG. 6 is an internal configuration diagram of a one-chip microcomputer, FIG. 7 is a circuit diagram of a conventional analog filter, and FIG. 8 is a diagram of a digital filter. Circuit diagram, FIG. 9 is a block diagram of a conventional motor rotation speed control circuit. 1...Motor, 2...Rotation speed detector, 3...One-chip microcomputer, 4
...DA converter, 5... Drive circuit, 4
0... Delay circuit, 41° 42... Multiplier, 43.44... Adder 0 Name of agent Patent attorney Toshio Nakao and 1 other person Figure 1 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] A rotation detection signal is obtained by a rotation detection means attached to the motor, and a time division control means calculates a motor rotation speed from the period of the detection signal to obtain a speed error, and performs filter processing based on this speed error, When obtaining a motor drive command value, the filter calculation is performed every predetermined period of one integer of the detection signal period from the time when the detection signal is input to the time division control means and the speed error is obtained. A method for controlling the speed of a motor, characterized in that: