JPS61180485A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture easily a transistor with a high withstanding voltage, by a method in which, after ion implantation is done selectively into the drain region, the entire face of the substrate is thermal-oxidized in order to thicken the insulating oxide film lying under the polycrystalline silicon gate electrode near the drain region. CONSTITUTION:After an inactive region 13 and gate oxide film 14 are formed on a P-type semiconductor substrate 12, a polycrystalline silicon gate electrode 15 is formed. Next, a photo resist film 16 covering a source region is formed, and arsenic ions are implanted to form an N-type diffusion layer 17. After the resist film 16 is removed, the entire face of the substrate is thermally oxidized to thicken the gate oxide film near the drain region thicker than a film thickness of the channel section. Thereafter, N-type impurities are implanted into the source region to form a diffusion layer 19, and finally an inter-layer insulating film 20 and electrode 22 are formed. In this way, a MOS transistor with a high withstanding voltage can be easily manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOS type semiconductor device, and particularly to a method of manufacturing a high voltage transistor.

[Conventional technology]

As an example of a high voltage MOS transistor, a high voltage transistor having a structure in which a gate oxide film near the drain/region of the transistor is thickened is known. This is intended to increase the total breakdown voltage by weakening the electric field between the gate and drain by thickening the gate and dielectric film near the drain.

However, with conventionally known manufacturing methods, it is necessary to form a thick gate oxide film in advance near the part that will become the drain of the transistor, separate from the gate oxide film of the part that will become the channel. , this thick game)
The structure must be such that the end of the gate electrode near the drain is placed on the R film.

A conventional high-voltage MOS semiconductor device is shown in FIG. 2 (a), for example.
) to (0).

As shown in FIG. 2(a), a field oxide film 2 in an inactive region and an active region 3 are selectively formed on a Pfi semiconductor substrate l.
form.

Next, as shown in FIG. 2(b), the entire surface of the P-type semiconductor substrate 1 is thermally oxidized, a thick gate insulating oxide film 4 is formed, and a photoresist 5t is selectively applied near the drain of the transistor. Form.

Next, as shown in FIG. 2C, using the photoresist 5 formed in the previous step as a mask, selective etching is performed with a hydrogen fluoride solution to form a thick gate insulating oxide film 4t-
Nokosu. Next, after removing the photoresist 5, a gate insulating oxide film 6 in the channel portion of the transistor is formed by thermal oxidation.

Next, as shown in FIG. 1(d), a polycrystalline silicon layer is grown on the entire surface of the P-dispersed semiconductor substrate l, and the polycrystalline silicon layer is covered with a thick gate insulating oxide film 4 using an oxide resist.
A polycrystalline silicon gate electrode 7 is formed by selectively etching so that the drain end of the gate electrode is placed thereon.

Next, as shown in FIG. 1(e), so that the polycrystalline silicon gate electrode 7 and the drain region are not offset,
The impurity is implanted by selecting an implanted impurity and an implantation acceleration voltage that can penetrate through the thick gate insulating oxide film 4 and form the N+ diffusion layer 8.

Finally, as shown in FIG. 1(f), the P-type semiconductor substrate 1
After forming an interlayer insulating film 9 on the entire upper surface and opening a contact portion 10, an aluminum electrode 11t is formed to complete a high breakdown voltage MOS type semiconductor device.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional manufacturing method, two thermal oxidations are required to form gate insulating oxide films of two different thicknesses, and the drain side of the gate electrode has a thick gate. Since the structure must be placed on an insulating oxide film, it is necessary to allow for misalignment during manufacturing, making it unsuitable for reducing device dimensions.

In addition, impurity implantation when forming the drain region and N+ diffusion layer must be done at a high enough temperature to allow the impurity to penetrate through the thick gate insulating oxide film, since it is necessary to avoid an offset structure between the gate electrode and the drain region. Accelerating voltage is required.

For example, if the thickness of the thick gate insulating oxide film near the drain is 2000 KV, if phosphorus is selected as the impurity, a high acceleration voltage of 200 KV will be required. This increases the diffusion length of the diffusion layer into the channel portion, making it necessary to increase the channel length of the transistor, which is inconvenient for downsizing the transistor.

The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a manufacturing method for forming a thick gate insulating oxide film in the vicinity of the drain of a transistor in a self-aligned manner.

[Means for solving problems]

A method for manufacturing a MOS type semiconductor device according to the present invention includes a step of forming an active region on a -conductivity type semiconductor substrate.

a step of forming a polycrystalline silicon gate electrode in the active region via an insulating oxide film; a step of selectively implanting ions of an opposite conductivity type impurity only into the drain region of the transistor; thickening the insulating oxide film under the polycrystalline silicon gate electrode in the vicinity of the drain region by thermally oxidizing the drain region of the transistor; and adding impurities of opposite conductivity type to the source region of the transistor. The method includes a step of injecting.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1(a) to 1(e) are cross-sectional views shown in order of steps to explain an embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type semiconductor substrate 12
After forming an inactive region 13 and an active region thereon, a gate oxide film 14t is formed in the active region.

Next, as shown in FIG. 1 (FIG. 5), a polycrystalline silicon film is formed on the gate acetate film 14, and a polycrystalline silicon gate electrode 15 is selectively left by photoetching.

Next, as shown in Figure (C), a photoresist 16 is formed so as to cover the source region of the transistor, and then the photoresist 16 and the polycrystalline silicon gate electrode 1 are formed.
Using No. 5 as a mask, arsenic ions are implanted to form an N-type diffusion layer L7.

Next, as shown in FIG. 1(d), the photoresist 16
After removing, the entire surface of the substrate is thermally oxidized. For this,
The oxide film on the diffusion layer of the drain region into which arsenic ions have already been implanted undergoes accelerated oxidation about five times as much as the oxide film on the diffusion layer of the source region that has not yet been implanted with N-type impurities. , bite into the channel direction. As a result, the gate oxide film near the drain region is sufficiently thicker than the gate oxide film in the channel region, which has the effect of weakening the electric field applied between the gate electrode and the drain.

Next, an N-type impurity is implanted into the source region of the transistor to form a source N+ diffusion layer 19.

Finally, as shown in FIG. 1(e), after forming the interlayer insulating film 20, a contact portion 21 is opened and an aluminum electrode 22 is provided. can.

As mentioned above, by utilizing accelerated oxidation of the arsenic-injected drain diffusion layer region, it is possible to form a thick gate insulating oxide film near the drain in a self-aligned manner.
Thereby, a 9MOS type high voltage transistor can be formed.

〔Effect of the invention〕

According to the present invention, it is possible to easily form a MOS type high voltage transistor having a thick gate insulating oxide film in the vicinity of the drain in a self-aligned manner to relax the electric field between the gate electrode and the drain, so that the device size can be reduced. very advantageous.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are cross-sectional views shown in order of steps to explain an embodiment of the present invention, and FIGS. 2(a) to (f) are conventional high voltage MOS type semiconductor device manufacturing methods. FIG. 3 is a cross-sectional view shown in order of steps to explain the method. 1.12...P-type semiconductor substrate, 2.13...
...Inactive region (field oxide film), 3...
・Active region, 4...Thick gate oxide film, 5.1
6...Photoregis), 6.14...
Gate oxide film, 7.15... Polycrystalline silicon gate electrode, 8... N+ diffusion layer, 9.20...
...Interlayer insulating film, to, 21...Contact part, 11.22...Aluminum electrode, 17.
...Drain N+ diffusion layer, 18...Thick cat oxide film, 19...Source N+ diffusion layer. ￥-1ヅ

Claims (1)

[Claims] forming an active region on a semiconductor substrate of one conductivity type;
a step of forming a polycrystalline silicon gate electrode in the active region via an insulating oxide film; a step of selectively implanting impurity ions of an opposite conductivity type only into the drain region of the transistor; thickening the insulating oxide film under the polycrystalline silicon gate electrode in the vicinity of the drain region by thermally oxidizing the drain region of the transistor; and adding impurities of opposite conductivity type to the source region of the transistor. 1. A method for manufacturing a MOS type semiconductor device, comprising the step of injecting.