JPS6118032A - external memory controller - Google Patents

Abstract

PURPOSE:To attain the transfer of data at a high speed and to improve the processing efficiency of a system by means of a small-capacity buffer memory, by checking the data transfer condition at the sections among the buffer memory, a processor and an external memory device according to the contents of a buffer address store means and controlling the buffer memory. CONSTITUTION:Address registers 30 and 29 and stop address registers 32 and 31 are provided to a buffer memory BM26 of a magnetic disk controller in order to give access from a processor 100 and a magnetic disk 301 respectively. When the coincidence of contents is obtained between registers 29/30 and 31/32, i.e., when the transfer of data is through with a sector, an interruption signal is sent to a microprocessor 16 for monitor and control of the processing state of the BM26. Thus it is possible to perform the simultaneous transfer of data between the processor 100 and the magnetic disk device having different processing speeds. This attains the data transfer at a high speed and improves the system processing efficiency.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an external memory control device, and in particular, to an external memory control device that can transfer data in parallel between magnetic disk devices with different data transfer speeds and between a central processing unit. This invention relates to a microprogram-controlled magnetic disk control device.

[Background of the invention]

Conventionally, in small computer systems, as shown in FIG. 1, a common bus 400 includes a central processing unit (hereinafter abbreviated as a processing unit) 100, a main memory 200, and an external memory control device 500, such as a magnetic disk control device 300.
etc., and the processing device 100 and external memory control device share the main memory 200. For example, during a period in which data is transferred between the main memory 200 and the magnetic disk device 301 in order to write or read data to the magnetic disk device 301, the common bus 400 is occupied, so the processing device 100 is The memory 200 cannot be accessed, and processing is stopped and placed in a standby state (hold state). Therefore, the longer the data transfer time with the input/output device, the longer the hold state time of the processing device 100 becomes, and the efficiency decreases.

Conventionally, in the magnetic disk controller R, when the data transfer speeds between the processing device side and the magnetic disk device side are different, the difference is absorbed and the optimum data transfer speed is set for the processing device side or the magnetic disk device side. As a method of data transfer, a data buffer memory is used, and after the data to be transferred is stored in this buffer memory, the data is transferred from the same buffer memory to the processing device side or the magnetic disk device side, respectively. .

In the case of small-sized computers such as office computers and personal computers, the transfer speed of magnetic disk devices is faster than that of processing devices.

Buffer memory control methods for absorbing this speed difference include a method using hardware and a method using a microprogram.

With hardware control methods, processing speed can be increased, but the peripheral control circuits of the buffer memory become complex and large-scale, and the transfer speeds of the processing unit and magnetic disk unit are uniquely fixed. Therefore, it cannot be handled when replacing the magnetic disk device, for example (lack of versatility).

In addition, although the microprogram-based control method can reduce the amount of hardware required, all the data to be transferred is stored in the buffer memory before the next operation is performed, which slows down the processing time and increases the cost. In the case of a large-capacity magnetic disk device, the buffer memory capacity increases,
Moreover, the number of data that can be transferred by one command operation is limited by the buffer memory capacity.

For example, 256 bytes of data can be written in one sector of a magnetic disk, so one □ command transfers 256 bytes x n sectors of data.

As mentioned above, the data transfer speeds between the magnetic disk control unit and the processing unit and between the magnetic disk control unit and the magnetic disk unit are different, so the conventional transfer method always buffers all data once, as shown in Figure 2. - After storing data in memory, it is necessary to perform a write operation to a magnetic disk device or data transfer to a processing device. That is, FIG. 2 shows the case where data is transferred from the processing device H to the magnetic disk device, and the data is transferred from the control device's buffer B to the magnetic disk D, and from the processing device H to the buffer B. Since the processing is executed alternately, serial processing is required, which takes time and requires a large-capacity buffer B.

Then, as shown in FIG. 1, the magnetic disk controller 3
If 00 occupies the common bus 400 for a long time to perform data transfer, the hold time of the processing device fiiloo also becomes long, and the efficiency of the system decreases.

[Purpose of the invention]

The purpose of the present invention is to solve such conventional problems, to enable high-speed data transfer using a small-capacity buffer memory with simple control, and to improve system processing efficiency. The object of the present invention is to provide an external memory control device that is capable of controlling external memory.

[Summary of the invention]

To achieve the above object, the external memory control device of the present invention transfers data between the processing device and the external memory device in the row 5 external memory control device via a common buffer memory. Between processing units (first section) and between the buffer memory and external memory device (
means for respectively storing each buffer address for accessing the buffer memory during each data transfer in the second section) and each stop address for detecting a temporary stop or end of the data transfer; Depending on the contents of each buffer address storage means, there is a means for detecting the point in time when sector-by-sector data transfer is performed in the first period and the second period and generating an interrupt signal, and a microprocessor for transmitting the signal to the above-mentioned interrupt. A feature of the present invention is that it includes means for controlling the buffer memory by monitoring it by a program and checking the progress of data transfer in the first and second sections.

[Embodiments of the invention]

Hereinafter, the principle and embodiments of the present invention will be explained with reference to the drawings.

FIG. 3 is a diagram showing the principle of the buffer memory control circuit of the present invention, and FIG. 4 is an explanatory diagram showing the principle of the data transfer method of the present invention.

In the present invention, (1) write/read operations to the magnetic disk device are performed in sector units; (ii)
Data transfer with the processing unit side and data transfer with the magnetic disk device side are simultaneously executed in parallel via one buffer memory, and (lii) The time required for the magnetic disk device to process one sector is short. Since both times are several 100 μs, there are three key points: intervening microprogram control during this time.

Therefore, the following conditions are satisfied.

(a) When writing to the magnetic disk device, data transfer from the processing device always precedes data transfer to the magnetic disk device by one sector or more; (b) When reading from the magnetic disk device, Data transfer from the magnetic disk device always precedes data transfer with the processing device by at least one sector; (C) An interrupt is generated each time one sector of data from the magnetic disk device is transferred. Then, using this interrupt, the microprogram monitors the status of both transfer processes on a sector-by-sector basis and controls whether to continue or stop the process.

In order to satisfy each of these conditions, as shown in FIG. 3, the buffer memory 26 of the magnetic disk control device is provided with an address register 30 and a stop address register 32 for access from the processing device 100 side. In addition, an address register 29 and a stop address register 29 for access from the magnetic disk device 301 side are provided.
A register 31 is provided, and an interrupt signal 5 is sent to the microprocessor 16 when the contents of the address registers 29, 30 and stop address registers 31, 32 respectively match, that is, when the transfer process for one sector is completed. Send. This allows microprocessor 1
6 monitors and controls the processing status of the buffer memory 26. As a result, data transfer between the processing devices 100 having different processing speeds and data transfer between the magnetic disk devices can be performed simultaneously.

If the magnetic disk device has a faster transfer processing speed than the processing device, the time it takes to write from the magnetic disk device to the buffer memory is shorter than the time to read it to the processing device, so the data in the buffer memory runs out and is transferred to the processing device. However, when transferring data from a processing unit to a magnetic disk device, the reading time is shorter than the writing time, so there is a risk that the transferred data may be interrupted. Control becomes important. Therefore, when data is transferred from the processing device H to the disk device, as shown in FIG. When reading is performed and the reading operation catches up with the writing operation, reading from buffer B is temporarily stopped, and after writing of one sector to buffer B is completed, the reading operation is restarted. In this way, by controlling the microprogram so that the write operation precedes the read operation by one sector, writing and reading from the buffer memory can be performed simultaneously and in parallel. The fourth diagram is for explaining this operation in more detail.
It is figure (b).

For example, the buffer memory 26 stores data from “0000” to “
The address for 2 sectors (512 bytes) at address 0511"" is assigned, and an interrupt INT is generated to the microprocessor when the data transferred from the processing unit is written from address "ooooo" to address "o255". . The microprogram learns that one sector worth of data has been written, and starts from the next “0256” to “051”.
The write operation of data up to address ``0255'' is continued, and reading of data from address ``oooo'' to address ``0255'' is started and transferred to the magnetic disk device. The read operation is completed up to address ``0255''.'
7. By generating an interrupt INT to the microprocessor, the microprogram confirms that data has been written in advance from the next address "0256" to "0511" and writes the data in this range. The reading operation is continued, and if writing of data for one sector is not yet completed, the reading operation is temporarily stopped until the writing is completed.

FIG. 5 is a block diagram of a magnetic disk control device showing one embodiment of the present invention, and FIG. 6 is a detailed block diagram of the data transfer control circuit of FIG. 5.

Microaddress bus 2 and microdata bus 3K
G"j,, microprocessor 16, address latch 17, microprogram R, 0M15, program R
AM19 is connected, and data bus gate 2
0. Instruction decoder 21 and address bus gate 22
The data bus 4.degree. data buffer RAM address bus 6 is connected to the microaddress bus 2 and the microdata bus 3. A data register 23, an address register 24, and a command register 25 are provided on the processing device (HO8T) side, and a magnetic disk device format control circuit 28 is provided on the magnetic disk device side. Further, a data buffer RAM 26 is connected to the data bus, and a data transfer control circuit 27 is connected to the data buffer RAM address bus 6.

According to the contents of the microprogram ROM 18, the microprocessor 16 controls the data transfer control circuit 27 and the magnetic disk drive format control circuit 28.
to operate the magnetic disk drive.

Data from the processing unit (HO8'l') is stored in the data buffer RAM 26 via the host data bus 7, data register 23, and data bus output. The data stored in RAM 25 is transferred to data bus 4.
, magnetic disk device format control circuit 2
8, the write data 11 is written to the magnetic disk device. When data for one sector of the magnetic disk device is stored in the RAM 26 from the processing device, an interrupt signal is generated from the data transfer control circuit 27 and sent to the microprocessor 16 via the bus 5. The microprocessor 16 uses a microprogram to count the number of times an interrupt signal has been generated and check the number of data transfer sectors. Also, from RAM 26 to the magnetic disk device 1
When a sector worth of data is transferred, an interrupt signal is generated from the data transfer control circuit 27 in this case as well, and is sent to the microprocessor 16 via the bus 5. The microprocessor 16 monitors the progress of data transfer on both sides by counting the number of times an interrupt signal has been generated and checking the number of data transfers to the magnetic disk device side using a microprogram.

On the other hand, when data read from a magnetic disk device is transferred to a processing device, the read data 12
The data read in is stored in the RAM 26 via the format control circuit 28 and data bus 4. When one sector worth of data is stored, an interrupt signal is generated from the data transfer control circuit 27 and sent to the microprocessor 16 via the bus 5.

The microprocessor 16 counts the number of times an interrupt signal has been generated and checks the number of data transfers using a microprogram. Also, when data stored in the RAM 26 is transferred to the processing device via the data path, data register 23, and bus 7, an interrupt signal is sent once l sectors worth of data have been transferred to the processing device. is generated and sent to the microprocessor 16 via the bus 5. The microprocessor 16 uses a microprogram to count the number of occurrences of interrupt signals, check the number of data transfers, and monitor the progress of both data transfers.

As shown in FIG. 6, the data transfer control circuit 27 includes a read/write control 36, a channel IDMA address register 29, and a channel IDMA address register 29.
Register 30. Channel 0 stop address register 31, Channel 1 stop address register 3
2. Multiplexer 33, 34. And address comparison mouth H! Consists of 535.

7 and 8 are operational flowcharts of FIGS. 5 and 6.

When the processing device issues a startup command to the magnetic disk control device, the microprocessor 16 is started and executes processing according to the contents of the microprogram ROM 15. Since the activation command issued by the processing device is stored in the command register 25, the contents of the command register 25 are first read into the microprocessor 16, the command is analyzed, and it is checked whether it is a write operation or a read operation. (Step 45, 4ej).

In the case of a write instruction, address register 2 is sent from the processing unit.
Set the data transfer start address to 4 (step 4).
7). Next, in order to write the data from the processing device to the data buffer RAM 26, the start address of the RAM 26 is set in the channel IDMA address register 30, and in order to transfer the data stored in the RAM 26 to the magnetic disk device, the start address of the RAM 26 is set. The start address is set in the channel Q DMA address register 29 (step 48). Here, the processing device side is channel 1, and the magnetic disk device side is channel 0. Next, channel l DMA address register 30
Set the stop address (address at the end of the number of transferred data) in the stop address register 32, and also set the stop address of the channel Q DMA address register 2.
9 stop address (address at the end of transfer data for 2 sectors) is stored in the stop address register 31.
(step 49). Next, from the processing device
The data transfer mode is specified to the AM 26 and from the RAM 26 to the magnetic disk device, and a data transfer start command is executed (steps 50 and 51). As a result, when the data request signal 40 is sent from the read/write control circuit 36 to the processing device via the bus 9, the data is sent from the memory in the processing device specified by the address register 24 via the bus O. A request response signal 41 and data are transferred. When the data request response signal 41 is input to the read/write control circuit 36, the control circuit M36 sends a memory write signal 37 to the RAM 26, and data is written from the address specified by the address register 30. This operation is repeated for a specified number of sectors (one sector in this case).

Each time 1 byte of data is written to I'LAM 26, the contents of address register 30 are counted up by +1, and when 256 bytes of data have been transferred, an interrupt signal 44 is generated. Microprocessor 16 monitors interrupt signal 44 to check the progress of the data transfer and causes the transfer to continue until it equals the value in channel I DMA stop address register 32 (step 52). In other words, RA from the processing device
When data of 2 sectors or more is transferred to M26,
By notifying the read/write control circuit 36 from the comparison circuit 35 via the bus 39, the control circuit 36 activates the magnetic disk drive format control circuit 28 via the bus 13. From this K, the control circuit 28 outputs a data request signal 42 to the read/write control circuit 36 via the bus 13, and the control circuit 36
outputs a memory read signal to RAM25, and
One byte of data is read from 26 in accordance with the address specified by address register 29, transferred to the magnetic disk device via control circuit 28, and written (step 53).

Each time 1 byte of data is read from the RAM 26, the contents of the address register 29 are counted up by +1, and when 256 bytes of data are read, an interrupt signal 43 is generated and this is sent to the microprogram. Setsu? Send to 1e+.

The microprocessor 16 monitors the interrupt signal 43 to check the number of data transfers and causes transfers to occur until the number becomes equal to the value in the channel O stop address register 31. Then, the number of data transfers is checked while monitoring the interrupt signals 43 and 44 (step 54).

At this time, if the data transfer speed on the magnetic disk device side is faster than the data transfer speed on the processing device side, before updating the channel O stop address register 31,
It is possible that address register 29 and stop address register 31 will be equal. In that case, when the values of the address register 29 and the stop address register 31 become equal, data transfer to the magnetic disk device is temporarily stopped, and the data is transferred from the processing device side to the RAM 2.
Wait until the data transfer to 6 is more than 2 sectors,
Set the data transfer end address for 2 sectors in the channel 0 stop address register 31 again, start the write operation for the remaining number of sectors from the sector where the operation was temporarily stopped for the magnetic disk device, and transfer the data. Start the transfer.

Thereafter, the same operation is repeated to write data from the processing device to the magnetic disk device until the channel 1 DMA address register 30 and the channel 1 stop address register 32 become equal.

In the case of a read operation, set the final address at the end of the number of data transfers in the channel O stop address register 31, and set the address at the end of the transfer of two sectors in the channel 1 stop address register 32. In other words, the stop address is updated on channel 1.
What to do with stop address register 32;
and R, AM26. from the magnetic disk device. RAM26
This is the same as a write operation, except that the data is transferred from the source to the processing device. At this time, if the data transfer speed on the magnetic disk device side is slower than the data transfer speed on the processing device side, the address register 30 and stop address register 32 are updated before updating the channel 1 stop address register 32. The values may become equal, but in that case, once registers 30 and 32 become equal, data transfer to the processing unit is temporarily stopped, and data transfer from the magnetic disk device to RAM 26 is for two sectors or more. After waiting for this, the data transfer end address for two sectors is set in the channel 1 stop address register 32 again, and the processing device is activated to start data transfer. After that, the same operation is repeated to set the channel I DMA address register 29 and channel O.
Data read from the magnetic disk device is transferred to the processing device until the values of the stop address registers 31 become equal (steps 47 to 61).

In the embodiments shown in FIGS. 7 and 8, R
Reading from AM26 has started, but reading can also be started after waiting for the write address to become one sector or more. In that case, one sector worth of data is transferred to both stop addresses 31 and 32. Set the end address and start. It is also possible to set the initial value to be set to the stop address to be another value.

In this way, by monitoring the progress of both addresses with a microprogram, it is possible to operate the buffer memory simultaneously, and there is a difference between the data transfer speed on the magnetic disk device side and the data transfer speed on the processing device side. Also, efficient processing becomes possible.

It also wraps around the channel IDMA address, channel 1 stop address, channel ODMA address, and channel O stop address.
That is, once the data has been transferred to the final address of the buffer memory, the data can be sent and received with a small buffer memory capacity by returning to the starting address of the buffer memory and repeating the data transfer. Note that the present invention is of course applicable to other external memory control devices.

〔Effect of the invention〕

As explained above, according to the present invention, (a) data transfer on the processing device side and data transfer on the magnetic disk device side can be performed simultaneously via one buffer memory, thereby reducing processing capacity. It is possible to improve the performance and reduce the buffer memory capacity. Furthermore, (b) the buffer memory capacity is reduced and the buffer memory is controlled by a microprogram, so the control circuit is simplified and the hardware configuration can be small-scale.

Furthermore, (C) even if the data transfer speeds of the processing device and magnetic disk device are changed, this can be handled by only partially changing the microprogram, and expandability can be achieved.

Furthermore, (d) since the transfer process to the magnetic disk device is completed in a short time, the hold time of the processing device is also shortened, and the processing device can perform more of its original processing, thereby improving the efficiency of the system.

[Brief explanation of drawings]

1 and 2 show a block diagram and an operation sequence chart during data transfer to a magnetic disk device in a conventional small computer system, and FIGS. 3 and 4 show the principle of the buffer memory control method of the present invention. Block diagram and operation sequence chart, FIG. 5 is a block diagram of a magnetic disk control device showing one embodiment of the present invention, FIG. 6 is a detailed block diagram of the data transfer control circuit of FIG. 5, FIG. FIG. 8 is an operational flowchart of FIGS. 5 and 6. 15 two basic clock generators, 16: microprocessor, 17: address latch, 18: microprogram ROM, 19 nibprogram RAM. 20: Data path gate, 21: Instruction decoder, 22
Near Address Pass Game), 23: Data Register, 2
4 Near address register, 25: Command register,
26: Data buffer RAM. 27: Data transfer control circuit, 28: Magnetic disk device format control circuit, 29.30: DMA
Address register, 31. 32 Nistup address register, 33. 34: Multiplexer, 35 Near address comparison circuit, 36: Read/write control circuit.

Claims (1)

[Claims] (1) In an external memory control device that transfers data between a processing device and an external memory device via a common buffer memory, data transfer between the buffer memory and the processing device (first section) and between the buffer memory and the When transmitting and receiving transfer data between external memory devices (second section), each buffer address is used to access the buffer memory, and each stop address is used to detect a temporary stop or end of data transfer. and means for detecting, based on the contents of each of the buffer address storage means, a point in time when data transfer is performed in sector units in the first section and the second section, and generating an interrupt signal. and means for controlling the buffer memory by monitoring the interrupt signal using a microprogram and checking the progress of data transfer in the first and second sections.