JPS61179555A - Making of ic - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Industrial applications This invention relates to integrated circuits.

BACKGROUND OF THE INVENTION As integrated circuit geometries become smaller and smaller, significant economic pressures are placed on circuit placement techniques. That is, if there is a change that allows the same circuit to be arranged in a smaller size with substantially the same shape and the same processing conditions, this will improve yield in two ways.

First, if the area on each chip that is susceptible to irregular defects is reduced, the percentage of depths rejected due to irregular defects would be reduced.

Second, the reduced area allows more chips to be constructed on a single wafer. In other words, more depths can be constructed at approximately the same cost.

However, one factor that has traditionally reduced the density of placements is the shape of the metallization layer, particularly where contacts are required. FIG. 1 shows an example of the conventional drawbacks in this regard.

Figure 1 (Figures 1A and 1B) shows two metal wires 1
Figure 3 shows a sample arrangement of minimum shapes (dimensions) where o extend parallel to each other. Each metal line 10 has a width equal to the minimum shape λ. (“λ′” is a term used by circuit design engineers to refer to the smallest feature available in a particular process - 5 microns for one set of processing conditions, or 5 microns for another set of processing conditions). 1.5 microns. Circuit design engineers can simply represent all dimensions in terms of λ, and it is a matter for process engineers to improve λ as process control improves. (The specific value of λ is not very important to the circuit design engineer.) However, FIG. 1B shows what happens with the minimum geometry arrangement of FIG. An example of this is shown below. Memory cell or microprocessor or random logic circuit arrangements very often require such adjacent contacts. Because the contact hole 12 is patterned by a different patterning process (different mask level) than that which defines the pattern of the metal line 10, the position of the contact hole 12 may be misaligned with respect to the metal line 10. could be. If the minimum feature is λ, then the acceptable tolerance of alignment, i.e. the maximum amount of misalignment that can be expected between structures patterned by two such different patterning steps, is typically can be 1/4 of λ. For this reason, if an attempt is made to make the contact 12 and the metal wire 1o overlapping it in the minimum shape using the conventional method, the metal wire 10 often becomes somewhat misaligned with the contact 12.

This can have a number of undesirable effects.

For example, the actual electrical area of each contact can vary, resulting in uncontrollable contact resistance. Furthermore, when making contacts to the moat or polysilicon level, the over-etch required to avoid touching the metal filament erodes these susceptible areas. Perhaps the most important drawback is when manufacturing vias (contacts or contact windows), such as when making contacts from a second metal to a first metal or from a first metal to polysilicon. In this case, if the contacts are misaligned with the edge of the lower conductor being contacted, the etch in the contacts will cause the second
A void is dug in the insulator adjacent to the conductor. in this case,
Some of the metal deposited later is used to fill this void, so that the metal overlying this void is very thin. This can result in poor metal step coverage in these locations, which can cause devices to fail from the start due to open circuits, or to fail during use for electromigration. It may fail early. To avoid this, conventionally it has been necessary to widen the metal wire 1o by one alignment tolerance at the location where the metal wire intersects the contact point 12. This is the conventional arrangement shown in FIG. 1B.

Where no contacts are required, both the width of the metal lines and the spacing between the lines are the minimum dimension λ, so the total pitch (i.e. the spacing between the centers of the metal lines) is simply 2 of λ. It's double. As shown in Figure 1B, where contacts are required,
The space between the lines 10 is still the minimum shape λ, but
However, at the point in the stroke, both metal wires have a width of λ
．． 5 times, and therefore the center-to-center spacing of such parallel metal wires must be 2.5 times λ. For this reason, the arrangement density at the metal level is significantly reduced.

These problems occur not only at the metal-to-moat contacts, but also at the metal-to-polysilicon and metal-to-metal points (usually called ``byer'' points).
(also called) occurs. Conventionally, it has been thought that it is desirable that the edges of the metal wire do not overlap the contact points with which the metal wire comes into contact. If the metal line has to be made wider in order to prevent contact points from being dislodged, the density of the second metal layer will decrease, and the density of the first metal layer will likely decrease as well.

The above describes the shortcomings of the conventional method based on the idea that the contact pattern can be determined using the minimum dimension λ. Of course, if the minimum shape of the contact is larger than the minimum shape of the metal layer, and this possibility is great,
In that case, the degradation that previously occurred as described above becomes even worse.

For this reason, the problems described above are particularly acute in gate arrays and semi-custom logic circuit arrangements.

That is, in order to reduce the negative effects of the shape of the contacts on the metal, traditional placement methods typically use extensive manual optimization to avoid lining up the contacts side by side. It is. However, the problem is further exacerbated when designing to adapt the arrangement according to customer requirements by selectively limiting the contacts and the second metal stage to a small number of circuits each.

That is, when designing a circuit for such uses, 1. It is necessary not only to minimize the occurrence of contacts in adjacent locations, but also to prevent contacts from clustering in one location.

It is therefore clear that the placement problem would be significantly simplified if manufacturing techniques could avoid the need to widen the minimally shaped metal lines in the vicinity of the contacts.

Problem to be Solved by the Invention Accordingly, it is an object of the present invention to avoid the need for a metal wire of minimum shape (dimensions) to widen to a width greater than the width of the contact itself at the point where it intersects the contact point. Its purpose is to provide integrated circuit manufacturing technology.

Another object of the invention is to provide an integrated circuit structure in which the pitch of metal levels is no more than twice the minimum feature.

Another object of the invention is to
It is an object of the present invention to provide an integrated circuit manufacturing method that does not require determining a pattern of contact positions to a width greater than the determined width.

SUMMARY OF THE INVENTION To achieve the above and other objects, the present invention utilizes sidewalls at patterned contact locations to provide an alignment gap equal to or greater than the alignment tolerance. Teach to narrow the contact points. [lI] After defining and etching the pattern of contact holes, the filament (strip) sidewalls are used to narrow the contact holes so that misalignment will cause the contacts to close to the edge of the layer that defined the pattern that these contacts should hit. Make sure that it does not stick out. In terms of defining the pattern, this
This means that the patterned width of the contact can be made exactly equal to the minimum shape, and that the metal level that must match this contact is also patterned exactly equal to the minimum shape. In particular, the present invention allows the metal layer to be patterned everywhere to the smallest possible shape by narrowing the width of the contacts with sidewall oxides so that there is no need to widen them even where they pass over the contacts; And to avoid thinning the interlevel dielectric during etchback that leaves sidewall oxide filaments, a thin nitride layer is deposited on the surface of the interlevel dielectric to generate a distinct endpoint signal. A method for manufacturing an integrated circuit is shown. This means that no over-etching of the oxide layer is required in a similar shape to leave sidewall oxide filaments, thus minimizing erosion of the interlevel dielectric and sidewall The width control of the oxide filament width is also improved.

In this invention, a substrate having a semiconductor region for an active device near its surface is prepared, an insulating layer is provided above a predetermined portion of the active device region, and the active device defining a first metal interconnect layer interconnecting predetermined portions of the storage area, and providing an interlevel dielectric above the first metal interconnect layer, the interlevel dielectric being primarily silicon oxide. and also has a WJFfi substantially composed of silicon nitride on its surface, and etches the interlevel dielectric to etch the first metal interconnect at predetermined bi-V locations. exposing the connecting layer and depositing another layer of insulating material in a similar shape, by anisotropically etching the layer of another insulating material and removing it from the exposed flat surface; , depositing another layer of conductive material to narrow the exposed via location periphery with the remaining portion of the layer of another insulating material and to connect the via areas in a predetermined pattern; A method of manufacturing an integrated circuit is provided that includes defining a pattern.

In this invention, a substrate having a semiconductor region for an active device near its surface is prepared, an insulating layer is provided above a predetermined portion of the active device region, and the active device defining a first metal interconnect layer that interconnects predetermined portions of the bi-V region; and anisotropically etching the interlevel dielectric above the first metal interconnect layer to form predetermined bi-Vs. exposing the first metal interconnect layer at a location;
the layer of another insulating material by depositing a layer of another insulating material in a similar shape and anisotropically etching the layer of another insulating material to remove it from the exposed planar surface; depositing and patterning another layer of conductive material to narrow the perimeter of the exposed via area and interconnecting the via areas in a predetermined pattern; include.

Next, embodiments of the invention will be described with reference to the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Although the invention will be described only in terms of 2.3 main preferred embodiments, those skilled in the art will recognize that the invention can be significantly modified and used in a wide variety of ways. Let's be beaten.

Therefore, it should be clearly stated that the scope of this invention is not limited by anything other than the scope of the claims.

Although the invention is most advantageous in the manufacture of vias, it can also be applied to the manufacture of mote contacts. FIG. 2A shows a sample example in which the present invention is applied to a metal moat junction. That is, in this sample example, it is typically an extension of the n+ source/drain region within substrate 18. Metal is brought into contact with the diffusion region 1a16. Diffusion region 16, along with its associated gate oxide and polysilicon gate structure, is typically covered by a phosphosilicate glass or other interlevel oxide layer 20. Holes are drilled at locations 22 in the interlevel dielectric by anisotropic etching. In the presently preferred embodiment, the particular contact area 22 shown is etched to a minimum shape, ie, has a width λ. In this case, λ is defined in the sense of the specific method described above. In this presently preferred embodiment, the width of the contacts 22 shown is 1 micron. Although the thickness of the interlevel oxide 20 is also shown as being approximately 1 micron adjacent this particular contact area 22, those skilled in the art will appreciate that the thickness of the interlevel dielectric 20 can vary from place to place, e.g. , the interlevel oxide 2o that must be cut out when making the metal-polysilicon contact.
It will be appreciated that the thickness of the interlevel oxide 20 is less than the thickness of the interlevel oxide 20 that must be cut away when making the metal moat interface.

After cutting out the contact area 22, a conformal dielectric is deposited. In the presently preferred embodiment, this layer 2
4 consists essentially of an oxide deposited in a similar shape, for example deposited by low pressure chemical deposition.

It is currently believed to be preferred to deposit the TEO8III compound, ie, from vapor phase tetraethylorne silane. This layer 24 is deposited to a thickness greater than the tolerance for alignment between the contact level and the subsequent metal level. In the presently preferred embodiment, layer 24 is deposited to a thickness of 2.500 mm, although the tolerance for misalignment is 0.2 microns. As a result, the structure shown in FIG. 2B is obtained.

Alternatively, oxide 24 may be deposited by low pressure chemical vapor deposition (LPGVD) using other well known gas mixtures, or as a plasma oxide. That is, when plasma is used for deposition, deposition can be performed at a temperature as low as about 300° C., compared to the higher temperature (about 700° C.) that is preferred when performing LPGVD using TE01.

LPCVD oxide 24 is then etched back leaving sidewall oxide filaments 24'. The width at the bottom of such a filament is approximately equal to the initial thickness of the conformal layer and is therefore still greater than the tolerance for misalignment between the contact layer and the metal layer. As is well known, to accomplish this, dielectric layer 24 should be etched slightly more than 100%. That is, etch for a period of time sufficient to remove the dielectric from all planar surfaces, and etch somewhat longer to ensure that the bottom of contact hole 22 is free of oxide 24. As a result, the oxide filament 24
' can be done. At this time, these filaments are connected to contact hole 2.
For this reason, the contact hole 22 is reduced on all sides by one alignment tolerance, or slightly more.

This can be clearly seen in the plan view of FIG. In this plan view, the contact area 1 is patterned by metal wires 10'.
2, but in contrast to the prior art shown in FIG. 1B, the width of the line 10' is of minimal shape even where it intersects the contact area 12. This is possible because the addition of the sidewall oxide 24' means that the actual area of the electrical contact is not the same as the patterned contact area 12, but instead is reduced to a reduced contact area 12', shown in dashed lines in FIG. This is because it means that it consists only of

As mentioned above, such a reduced contact layer [12' never crosses the boundaries of the metal lines 10'. Note that such a reduced contact area 12' is actually sublithographic, ie smaller than could be directly patterned.

In the presently preferred embodiment, the conformal oxide 24 is substantially overetched, ie, etched by more than 100%, to ensure that nothing remains at the bottom of the contact area 22. (i.e., edge for twice as long as it takes to remove this oxide from a planar surface.) This overetch typically also reduces the thickness of dielectric 20 somewhat; also means that during the over-etch step, some of the silicon at the bottom of the contact hole is also etched away (since no silicon etch is infinitely selective). However, it is easy to compensate for both effects;
The impact is also small.

To avoid thinning of the interlevel dielectric and to provide better control over the width of the sidewall oxide, another embodiment of the invention is configured as follows. A thin layer of silicon nitride, for example 300 nm thick, is deposited over the interlevel dielectric prior to spin depositing the photoresist to pattern the contact holes. Cut the contact holes using an oxide etch that also cuts into the nitride. A protective layer 24, which becomes the sidewall oxide 24', is then deposited and etched to leave the filaments. However, in this embodiment, the interlevel rust electric body 20
The nitride layer 101 deposited on top of the layer 24 provides a strong endpoint signal when layer 24 is removed from the planar surface. Therefore, the degree of overetching can be controlled based on the endpoint signal generated when the etching plasma contacts the thin nitride layer 101 on the flat surface of the interlevel dielectric 20. It is unnecessary to over-etch layer 24 as much.

An important result of this invention is that the actual contact area is reduced, thereby increasing the series resistance of the contacts. For example, providing a 0.2 micron sidewall on each side of a 1 micron square contact reduces the contact area from about 1 micron square to approximately 1/3. Assuming the resistivity of the contact remains the same, the series resistance through this contact increases accordingly.

In the presently preferred embodiment of the invention, this is not a major problem. This is because the contacts do not have a significant contribution to the series resistance of the integrated circuit in which they are formed. Contact resistance is typically small compared to the series resistance caused by polysilicon or moat connections. That is, the present invention is most preferably practiced in a configuration in which the specific contact resistance is sufficiently small that the reduction in contact area is not electrically significant. For example, when applying the invention to a contact to polysilicon, the invention may be applied to, for example, 0.0
It is preferred to use a process such as silicided polysilicon, which yields a specific contact resistance as low as 4 microohms-α2. In this case, the resistance of a 1 micron square contact is 4 ohms, which is not a problem; even with 0.2 micron square sidewalls, the contact resistance is still only about 12 ohms.

However, if the specific contact resistance is relatively large, for example 1 microohm-Cm2, it is most undesirable to triple the contact resistance from 100 ohms to 300 ohms.

As seen in FIG. 2C, although the sidewall oxide 24' is rounded at the top, the profile of the contact sidewalls is still limited by the resist erosion or interlevel dielectric 24 intended to achieve sloped contact sidewalls. is much steeper than normally achieved by methods such as reflow. For this reason, it is preferred to use a stud contact process or conformal metal deposition in connection with the present invention. Such methods are widely described in the literature.

The invention thus has the major advantage that the pitch of the metal is not degraded by the arrangement of the contacts used.

A secondary advantage of this invention is that the pitch of the moat is also freed from constraints such as those imposed by contact placement. That is, not only is it desirable that the metal wire not dislodge from the contact hole, but it is also highly desirable that the contact hole not dislodge from the moat area with which it is to be in contact. For example, in FIGS. 1A and 1B, if the line representing metal level 10 represents moat level 10', the illustrated contact spacing reduces the pitch of the moat. Although the pitch of the moat is not expected to be as strongly constrained by such contact placement as the pitch of the metal, this is still another advantage of the invention that provides greater freedom for the design engineer.

In the particular embodiment of the invention shown in FIG. 4, there is no need to leave alignment tolerances between the contact mask and the edge of the field oxide. That is, in the embodiment not shown in FIG. 4, a contact area 22 is cut into the interlevel dielectric 20 and thin pad oxide 21 to make contact with the diffusion 16 of the substrate 18, but is not first cut out. The etch of the contact hole 22' also causes the field oxide 3o to have a bird's beak (i.e., a tapered end).
It will be recognized that this can be cut out. This is the contact hole 22
This is normally harmful because the metal deposited on the channel stopper diffusion 32 contacts the p+ channel stopper diffusion 32, causing a short circuit. However, with the present invention, the sidewall 24' fills the area eroded by the bird's beak, so that the metal deposited in the contact hole 22' passes through the channel stop 32 to the substrate 18. ) This short circuit path cannot be created. This is another advantage of this invention.

Another very important advantage of this invention is its effect on freeing the polysilicon pitch. That is, in many circuit designs, as shown in Figure 7A, the bias
16, it is necessary to expand the polysilicon layer 110 in the active device area (i.e., polysilicon level 11
The pitch between areas 114 where 0 intersects moat 112 is reduced due to the required spacing of metal-polysilicon contacts (vias) 116. However, if the present invention is used, even in such a case, a well-organized arrangement as shown in FIG. 7B can be obtained. That is, in this embodiment of the invention, the patterned contact area 116 is reduced by the sidewalls and
This results in an effective contact area 118. This allows the use of sidewalls to compensate for alignment tolerances even if the patterned contact area 116 is made small enough to deviate from the polysilicon layer 110' (which is not expanded at the location of the bi-V 116). respectively means that the actual effective contact point 118 does not deviate from the narrowed polysilicon line 110'.

For this reason, the pitch between the active areas 114 remains at its minimum shape)
It can be done.

Another particular advantage of the invention is particularly recognized in the multi-level process of buyer-intensive design. By way of example, FIG. 5 shows a sample section in which the metal lines 42 of the second level are connected by multiple vias to a dense array of metal lines 40 of the second level. By using this invention, the patterned buyer area 44 (particularly outlined by a thick solid line) is reduced to an actual buyer area 46 (indicated by a dashed line V), so that the metal wire 42 of the first rubel and Both second level metals 4140 can be arranged as a dense array. This is very advantageous for gate arrays as mentioned earlier, and also for the placement of many other interconnected lumped logic circuits such as dedicated signal processing parts or microprocessors in general. be.

Another advantage of the invention is that it achieves the above-mentioned advantages without significant processing complexity. That is, the only additional steps are the LPGVD oxide deposition and the anisotropic etchback to leave the filament. These processes are simple, inexpensive, and low risk.

As can be seen from the above description, the invention is most advantageous when combined with other advanced processing features at the true VLSI level. That is, the present invention is most advantageously combined with advanced features such as low sheet resistance (silicide) source/drain regions, stud contacts, and minimal feature metal pitch.

As will be apparent to those skilled in the art, the present invention can be significantly modified and practiced in connection with a wide variety of processes. It is therefore intended that the scope of the invention be limited only by the claims that follow.

[Brief explanation of the drawing]

Figures 1A and 1B show a conventional structure in which the minimum pitch that can be used for a simple straight parallel metal wire (shown in Figure 1A) is as shown in Figure 1B. , indicating that it cannot be used if the metal wire extends over adjacent contact locations. 2A to 2C are diagrams showing the successive steps of the manufacturing method of the invention used to form a moat contact, and FIG. 3 is a diagram showing the arrangement of the apparatus of the invention, the pitch of the metal being Adjacent parallel metal lines must both intersect adjacent contact locations (exactly twice the minimum shape). 4 is a side view of one particular type of embodiment of the invention in the manufacture of a moat contact; FIG. 5 is a top view of the invention in a dual level metal construction; and FIG. Figure 6B is a top view of a sample via in which misalignment occurs to the extent that the via hole overlaps the edge of the underlying conductor (with the pattern defined); Figure 6C illustrates the serious consequences of this misalignment, and Figure 7A illustrates how the present invention can be used to avoid the negative effects of such misalignment in the particular case of nested contact structures. Figure 7B shows a conventional sample structure in which the pitch between active areas is reduced due to the required pitch of the contacts to the level; FIG. 7B shows how this reduction in shape is avoided by the present invention; Explanation of main symbols 16: Diffusion part 18 Two substrates 20 Two-level dielectric 22: Contact hole 24': Sidewall oxide

Claims (9)

[Claims] (1) A substrate having a semiconductor region for an active device near its surface is prepared, an insulating layer is provided above a predetermined portion of the active device region, and a semiconductor region for the active device is provided so as to constitute a predetermined circuit function. defining a first metal interconnect layer interconnecting predetermined portions of the region, and providing an interlevel dielectric above the first metal interconnect layer, the interlevel dielectric comprising primarily silicon oxide; and a thin layer substantially of silicon nitride on a surface thereof, and anisotropically etching the interlevel dielectric to remove the first metal interconnect layer at predetermined via locations. exposing a layer of another insulating material by depositing a layer of another insulating material in a similar shape and subjecting the layer of another insulating material to anisotropic etching to remove it from the exposed planar surface; narrowing the periphery of the exposed via locations by a remaining portion of the via area, and depositing and patterning another layer of conductive material to interconnect the via areas in a predetermined pattern. How to manufacture circuits. (2) providing a substrate having a semiconductor region for an active device near its surface, the active device region constituting a field effect transistor with a gate confined within a layer of polycrystalline material containing silicon; An interlevel dielectric is provided above the gate layer, the interlevel dielectric being comprised primarily of silicon oxide and also having a thin layer substantially comprised of silicon nitride on its surface; anisotropically etching the gate layer to expose the gate layer at predetermined via locations, depositing another layer of insulating material in a similar shape, and anisotropically etching the layer of another insulating material to expose the gate layer at predetermined via locations; removing it from one side so that the remaining portion of the other layer of insulating material narrows the perimeter of the exposed via location and interconnecting the via areas in a predetermined pattern; A method of manufacturing an integrated circuit comprising depositing and patterning another layer of conductive material on a substrate. (3) providing a substrate having a semiconductor region for an active device near its surface, the active device region constituting a field effect transistor with a gate confined within a layer of polycrystalline material containing silicon; a first interlevel dielectric is provided above the gate layer, and the first interlevel dielectric is patterned to provide predetermined contact locations within the gate layer as well as predetermined contact locations within the active device region. defining a first metal interconnect layer that is exposed and interconnects the active device region and a predetermined portion of the gate layer to constitute at least a portion of a predetermined circuit function; A second interlevel dielectric is provided above the second interlevel dielectric, the second interlevel dielectric being comprised primarily of silicon oxide and also having a thin layer substantially comprised of silicon nitride at a surface thereof. anisotropically etching the second interlevel dielectric to expose the first metal interconnect layer at a predetermined second via location and etching the gate at another predetermined second via location; by also exposing the layer, depositing another layer of insulating material in a similar shape, and anisotropically etching the other layer of insulating material to remove it from the exposed planar surface.
The remaining portion of the layer of another insulating material narrows the perimeter of the exposed second via location and includes another conductive layer to interconnect the second via location in a predetermined pattern. A method of manufacturing an integrated circuit that includes depositing and patterning layers of material. (4) providing a substrate having a semiconductor region for an active device near its surface, and providing an insulating layer above a predetermined contact position of the region for an active device and above another portion of the region for an active device; The insulating layer is composed primarily of silicon oxide and also has a thin layer substantially composed of silicon nitride on its surface, and the insulating layer is anisotropically etched to form a plurality of the contacts. said another layer of insulating material by exposing the area, depositing another layer of insulating material in a similar shape, and anisotropically etching said layer of another insulating material to remove it from the exposed planar surface. depositing and patterning a layer of conductive material to narrow the perimeter of the exposed contact areas by a remaining portion of the layer of insulating material and interconnecting the contact areas in a predetermined pattern; A method of manufacturing an integrated circuit comprising: (5) providing a substrate having a semiconductor region for an active device near its surface, the active device region constituting a field effect transistor with a gate confined within a layer of polycrystalline material containing silicon; , an interlevel dielectric is provided above the gate layer, the interlevel dielectric being composed primarily of silicon oxide and also having a thin layer substantially composed of silicon nitride on its surface. , anisotropically etching the interlevel dielectric to expose the gate layer at predetermined via locations and the active device region at predetermined contact locations, and depositing another layer of insulating material in a similar configuration. and by anisotropically etching the layer of another insulating material to remove it from the exposed flat surfaces, the remaining portions of the layer of another insulating material remove exposed contact and via locations. A method of manufacturing an integrated circuit comprising: depositing and patterning another layer of conductive material to narrow the periphery of the contact areas and interconnecting the contact areas and via areas in a predetermined pattern. (6) A method according to claim 1, wherein the step of depositing the layer of another insulating material comprises low pressure chemical, reactive vapor deposition of silicon oxide. 7. The method of claim 1, wherein the step of depositing a layer of another insulating material comprises low temperature plasma assisted deposition of silicon oxide. (8) In the method described in claim 2,
The method, wherein the gate layer is made of polycrystalline silicon. (9) The method according to claim 2, wherein the gate layer is made of a metal silicide compound.