JPS61179486A - Conductor device - Google Patents
Conductor deviceInfo
- Publication number
- JPS61179486A JPS61179486A JP60019520A JP1952085A JPS61179486A JP S61179486 A JPS61179486 A JP S61179486A JP 60019520 A JP60019520 A JP 60019520A JP 1952085 A JP1952085 A JP 1952085A JP S61179486 A JPS61179486 A JP S61179486A
- Authority
- JP
- Japan
- Prior art keywords
- electrode line
- source electrode
- display device
- gate electrode
- low resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000002131 composite material Substances 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 description 16
- 239000010408 film Substances 0.000 description 13
- 239000010410 layer Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 6
- 239000012769 display material Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 210000004709 eyebrow Anatomy 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置に関し、特にマトリクス型液晶表
示装置等に用いられるTPTアレイの構造に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a TPT array used in a matrix type liquid crystal display device or the like.
第6図はTPTアレイの画素の構成を、第7図はこれを
用いたマトリクス型表示装置の構成の説明図である。FIG. 6 is an explanatory diagram of the pixel configuration of the TPT array, and FIG. 7 is an explanatory diagram of the configuration of a matrix type display device using this.
第6図及び第7図において、1はゲート電極線、2はソ
ース電極線、3はドレイン電極、4はTFT(Thin
Film Transistor)、5は画素電極、
6は液晶等の表示材料、7はTFTアレイ、8はTFT
アレイ基板、9は対向電極基板、1oは対向電極、11
はマトリクス型表示装置を示している。6 and 7, 1 is a gate electrode line, 2 is a source electrode line, 3 is a drain electrode, and 4 is a TFT (thin
Film Transistor), 5 is a pixel electrode,
6 is display material such as liquid crystal, 7 is TFT array, 8 is TFT
Array substrate, 9 is a counter electrode substrate, 1o is a counter electrode, 11
indicates a matrix type display device.
TFTアレイ7は複数のゲート電極線11及びこれらの
ゲート電極mlと交差するソース電極線2とを備え、そ
の交点に例えばTFT4等の電圧、電流特性が非線形な
特性を有する能動素子、画素電極5等が形成された画素
を集積することにより構成されたものである。又、マト
リクス型表示装置11は上記TFTアレイ7を用い、こ
れと対向する透明導電膜電極等の対向電極1oを有する
対向電極基板9、及びこの両基板8.9間に液晶等の表
示材料6を挾持することにより構成されたものである。The TFT array 7 includes a plurality of gate electrode lines 11 and a source electrode line 2 that intersects with these gate electrode lines ml, and at the intersection point there is a pixel electrode 5, an active element such as a TFT 4, which has nonlinear voltage and current characteristics. It is constructed by integrating pixels in which , etc. are formed. Further, the matrix type display device 11 uses the TFT array 7 described above, and a counter electrode substrate 9 having a counter electrode 1o such as a transparent conductive film electrode opposite thereto, and a display material 6 such as a liquid crystal between the two substrates 8 and 9. It is constructed by holding the .
第8図〜第10図は従来のこの種の装置の構成を示し、
第8図はTPTアレイ画素の平面図、第次にこの従来の
TPTアレイ7、及びマトリクス型表示装置11の構成
を第8図〜第10図及び第7図を参照して説明する。Figures 8 to 10 show the configuration of a conventional device of this type,
FIG. 8 is a plan view of a TPT array pixel. Next, the configuration of this conventional TPT array 7 and matrix type display device 11 will be explained with reference to FIGS. 8 to 10 and FIG. 7.
TPTアレイ7は例えばガラス等よりなるTFTアレイ
基板8の表面に、I T O(Indium Tin0
xide)等の透明導電膜、及び必要に応じて、例えば
リン(P)等のn型半導体不純物をドープしたアモルフ
ァスシリコン(以下a−Si (n)と称す)等を連
続的に成膜した後、写真製版法等によりこれをパターン
ニングしてドレイン電極3と一体化された画素電極5、
及びソース電極線2及びa−5i (n)層15を同
時に形成する。続いて、例えばアモルファスシリコン(
以下a−3i)等の半導体層12、及びSiN等よりな
るゲート絶縁膜13を連続的に成膜した後、これをパタ
ーンニングし、この後Al1等を成膜した後、これをパ
ターンニングしてゲート電極線1を形成し、該TPTア
レイ7が完成する。The TPT array 7 is made of ITO (Indium Tin0) on the surface of a TFT array substrate 8 made of glass or the like.
After successively forming a transparent conductive film such as xide) and, if necessary, amorphous silicon doped with an n-type semiconductor impurity such as phosphorus (P) (hereinafter referred to as a-Si (n)), etc. , a pixel electrode 5 that is integrated with the drain electrode 3 by patterning it by photolithography or the like;
Then, the source electrode line 2 and the a-5i (n) layer 15 are formed simultaneously. Next, for example, amorphous silicon (
After successively forming a semiconductor layer 12 such as a-3i below and a gate insulating film 13 made of SiN or the like, this is patterned, and then after forming a film of Al1 or the like, this is patterned. Gate electrode lines 1 are then formed, and the TPT array 7 is completed.
また、マトリクス型表示装置11は前述のTPTアレイ
7を用い、これと対向する透明導電膜よりなる対向電極
10を有する対向電極基板9との間に液晶等の表示材料
6を挟持させると完成する。Further, the matrix type display device 11 is completed by using the above-mentioned TPT array 7 and sandwiching a display material 6 such as liquid crystal between this and a counter electrode substrate 9 having a counter electrode 10 made of a transparent conductive film. .
マトリクス型表示装置11は例えば画像表示等に用いら
れる関係から、第6図又は第8図等に示した単位画素の
大きさは、例えば50μm から1mm 前後以下に制
約され、この画素の必要数は表示装置の用途、表示画面
サイズ等に依存するが、通常数千ないし数百万個が必要
である。又、前述したソース電極線2、及びゲート電極
線1の線幅はマトリクス型表示装置11の開口率等の制
約から、例えば数十μm以下に制限されると共に表示装
置の画面サイズの大きさに対応した長さが必要である。Since the matrix type display device 11 is used for displaying images, etc., the size of the unit pixel shown in FIG. 6 or 8 is limited to about 50 μm to 1 mm, for example, and the required number of pixels is Depending on the purpose of the display device, display screen size, etc., usually several thousand to several million pieces are required. Further, the line widths of the source electrode line 2 and the gate electrode line 1 described above are limited to, for example, several tens of μm or less due to constraints such as the aperture ratio of the matrix display device 11, and also due to the screen size of the display device. A corresponding length is required.
又、マトリクス型表示装置11で画像等を表示するには
、ゲート電極線l側を走査電極とし、ソース電極線2側
をビデオ信号電極として用いるが、例えば1/2インタ
一レース表示を実行するには、63.5μsecの期間
中に、ソース電極線2及びTFT4を介して画素をビデ
オ信号電位まで充電、駆動することが必要で、従ってソ
ース電極線2及びTPT4等はオン抵抗が小さいことが
要求され、大画面のマトリクス型表示装置においては、
ソース電極線2の低抵抗化が特に重要である。又、マト
リクス型表示装置11を安定に、かつ低コストに製造す
るためには、前述した写真製版法等によるパターンニン
グ回数を低減することが最も効果的である。Furthermore, in order to display images etc. on the matrix type display device 11, the gate electrode line l side is used as a scanning electrode and the source electrode line 2 side is used as a video signal electrode. For example, 1/2 interlaced display is performed. , it is necessary to charge and drive the pixel to the video signal potential via the source electrode line 2 and TFT 4 during a period of 63.5 μsec. Therefore, the on-resistance of the source electrode line 2, TPT 4, etc. must be small. In the required large screen matrix type display device,
It is particularly important to reduce the resistance of the source electrode line 2. Furthermore, in order to manufacture the matrix type display device 11 stably and at low cost, it is most effective to reduce the number of times patterning is performed by the above-mentioned photolithography method or the like.
以上の制限、及び必要条件の中で、従来のTPTアレイ
7、及びマトリクス型表示装置11はソース電極線2が
アルミ等に比し比較的高抵抗のITo等の透明導電膜よ
りなる配線で形成されており、ビデオ信号電極線となる
ソース電極線2の配線抵抗が高く、大画面のマトリクス
型表示装置11では数〜数十MΩにも達し、均一な表示
が不可能で、ビデオ信号電圧の増大が必要、多階調表示
が不可能であるなど、特に大画面のマトリクス型表示装
置において良好な表示が得られない欠点を有していた。Within the above limitations and requirements, the conventional TPT array 7 and matrix display device 11 have source electrode lines 2 made of a transparent conductive film such as ITo which has a relatively high resistance compared to aluminum etc. The wiring resistance of the source electrode line 2, which serves as the video signal electrode line, is high, reaching several to several tens of MΩ in the large-screen matrix display device 11, making it impossible to display uniformly and causing a drop in the video signal voltage. It has disadvantages such as the need to increase the size of the display and the inability to display multiple gradations, making it difficult to obtain a good display, especially in large-screen matrix-type display devices.
この発明は前述のような欠点を除去するためになされた
もので、写真製版等によるパターンニング回数を増加す
ることなく構成でき、低抵抗なソース電極線を有する半
導体装置を得ることを目的としている。This invention was made in order to eliminate the above-mentioned drawbacks, and its purpose is to obtain a semiconductor device that can be constructed without increasing the number of patterning operations such as photolithography, and has a source electrode line with low resistance. .
この発明に係る半導体装置は、ソース電極線のゲート電
極線との交差部以外の部分を、透明導電膜及び他の低抵
抗配線層よりなる複合配線層又は低抵抗配線層のみによ
り構成したものである。In the semiconductor device according to the present invention, the portion other than the intersection of the source electrode line with the gate electrode line is composed of only a composite wiring layer consisting of a transparent conductive film and another low resistance wiring layer or a low resistance wiring layer. be.
この発明においては、ソース電極線のゲート電極線との
交差部以外の部分を、透明導電膜及び他の低抵抗配線層
よりなる複合電極配線または低抵抗配線層のみにより構
成したから、ソース電極線の低抵抗化が達成される。In this invention, since the portion of the source electrode line other than the intersection with the gate electrode line is composed of only a composite electrode wiring or a low resistance wiring layer consisting of a transparent conductive film and another low resistance wiring layer, the source electrode line A low resistance is achieved.
以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図はこの発明の一実施例による半導体装置のしかも
ゲート電極線1とソース電極線2との交差部においては
ソース電極線2がITO等の透明導電膜で構成されてい
るので、ゲート電極線1とソース電極線2との眉間絶縁
特性が良好で、交差部における両者の短絡不良等が低減
できる。又TPTアレイ7の各構成要素のパターン形成
が三度の写真製版等で達成できる等、製造プロセスが簡
略化されており、少数のマスクでTPT7レイ7の製造
が可能であり、特に大型高性能なTFTアレイ7、及び
マトリクス型表示装置が高い製造歩留まりで、再現性良
く得られる効果がある。FIG. 1 shows a semiconductor device according to an embodiment of the present invention, in which the source electrode line 2 is made of a transparent conductive film such as ITO at the intersection of the gate electrode line 1 and the source electrode line 2. The line 1 and the source electrode line 2 have good insulation properties between the eyebrows, and short-circuiting and the like between the two at the intersection can be reduced. In addition, the manufacturing process is simplified, as the pattern formation of each component of the TPT array 7 can be achieved by three photolithography steps, etc., and the TPT array 7 can be manufactured with a small number of masks, making it especially suitable for large-sized, high-performance devices. The TFT array 7 and the matrix type display device have the advantage of being able to be manufactured at a high manufacturing yield and with good reproducibility.
又、第4図、第5図は本発明の他の実施例を説で、17
はコンタクトホールであり、他の同一符号は、前述の本
発明の一実施例と同一、又は相当部分を示している。In addition, FIGS. 4 and 5 illustrate other embodiments of the present invention.
denotes a contact hole, and other same reference numerals indicate the same or corresponding parts as in the embodiment of the present invention described above.
以下、この発明の他の実施例を前述の一実施例との相異
点、及びその特徴について説明する。第4図、第5図に
示す本発明の他の実施例は、ソース電極線2上の半導体
層12、及びゲート絶縁膜13よりなる眉間絶縁部14
にコンタクトホール17を設け、このコンタクトホール
17を介してその下部に形成した170等透明導電膜よ
りなるり、ビデオ信号線となるソース電極線2の低抵抗
化を達成したものである。Hereinafter, other embodiments of the present invention will be described with respect to their differences from the above-mentioned embodiment and their characteristics. Another embodiment of the present invention shown in FIG. 4 and FIG.
A contact hole 17 is provided in the contact hole 17, and a transparent conductive film such as 170 is formed under the contact hole 17 to achieve low resistance of the source electrode line 2, which becomes a video signal line.
この第4図、第5図で説明した例では1画素につき二個
のコンタクトホール17を設けた例を示したが、このコ
ンタクトホール17を例えば細分化し二個以上形成して
もよく、又このコンタクトホール17を大型化し、1画
素につき一個を設置するようにしてもよく、上記実施例
と同様の効果が得られる。又、図示していないが、17
0等透明導電膜よりなるソース電極2を層間絶縁部14
のみに形成し、この間を低抵抗配線層16のみで配線す
ることによりソース電極線を形成してもよい。In the example explained in FIGS. 4 and 5, two contact holes 17 are provided for each pixel, but the contact hole 17 may be divided into two or more contact holes 17, and two or more contact holes 17 may be formed. The contact hole 17 may be made larger and one contact hole may be provided for each pixel, and the same effect as in the above embodiment can be obtained. Also, although not shown, 17
The source electrode 2 made of a 0 grade transparent conductive film is connected to the interlayer insulating part 14.
Alternatively, the source electrode line may be formed by forming the source electrode line with only the low-resistance wiring layer 16 between them.
以上のように、この発明に係る半導体装置によれば、ソ
ース電極線のゲート電極線との交差部以外を透明導電膜
及び他の低抵抗配線層からなる複合電極配線又は低抵抗
配線層により構成したので、ソース電極線の低抵抗化を
達成できる効果がある。As described above, according to the semiconductor device according to the present invention, the portion other than the intersection of the source electrode line with the gate electrode line is formed of a composite electrode wiring or a low resistance wiring layer consisting of a transparent conductive film and another low resistance wiring layer. Therefore, it is possible to reduce the resistance of the source electrode line.
第1図は本発明の一実施例による半導体装置の平面図、
第2図は第1図のA−A’線断面図、第3図は第1図の
B−B”線断面図、第4図は零発アレイの画素の説明図
、第7図はマトリクス型液ある。
図中、1はゲート電極線、2はソース電極線、3はドレ
イン電極、4はT)’T (能動素子)、5は画素電極
、6は表示材料、7はTFTアレイ、11はマトリクス
型表示装置、12は半導体層、13はゲート絶縁膜、1
4は眉間絶縁部、I6は低抵抗配線層、17はコンタク
トホールである。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention;
Figure 2 is a cross-sectional view taken along the line AA' in Figure 1, Figure 3 is a cross-sectional view taken along the line B-B'' in Figure 1, Figure 4 is an explanatory diagram of the pixels of the zero firing array, and Figure 7 is the matrix. In the figure, 1 is a gate electrode line, 2 is a source electrode line, 3 is a drain electrode, 4 is T)'T (active element), 5 is a pixel electrode, 6 is a display material, 7 is a TFT array, 11 is a matrix type display device, 12 is a semiconductor layer, 13 is a gate insulating film, 1
4 is an insulating part between the eyebrows, I6 is a low resistance wiring layer, and 17 is a contact hole. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
るソース電極線又はドレイン電極線を有し、その各交点
に非線形特性を有する能動素子を配置して構成される半
導体装置において、上記能動素子のソース電極線のゲー
ト電極線との交差部以外の部分を、透明導電膜及び他の
低抵抗配線層よりなる複合電極配線又は低抵抗配線層の
みにより構成したことを特徴とする半導体装置。(1) In a semiconductor device configured by having a plurality of gate electrode lines and a source electrode line or a drain electrode line orthogonal to the gate electrode lines, and arranging an active element having nonlinear characteristics at each intersection point, 1. A semiconductor device characterized in that a portion other than the intersection of a source electrode line with a gate electrode line of an element is constituted by a composite electrode wiring made of a transparent conductive film and another low resistance wiring layer or only a low resistance wiring layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60019520A JPS61179486A (en) | 1985-02-04 | 1985-02-04 | Conductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60019520A JPS61179486A (en) | 1985-02-04 | 1985-02-04 | Conductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61179486A true JPS61179486A (en) | 1986-08-12 |
Family
ID=12001617
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60019520A Pending JPS61179486A (en) | 1985-02-04 | 1985-02-04 | Conductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61179486A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63216031A (en) * | 1987-03-05 | 1988-09-08 | Mitsubishi Electric Corp | Display device |
JPS63278895A (en) * | 1987-05-09 | 1988-11-16 | 株式会社 半導体エネルギ−研究所 | Card having display function and memory capacity |
JPS63278894A (en) * | 1987-05-09 | 1988-11-16 | 株式会社 半導体エネルギ−研究所 | Card having display function and memory capacity |
JPS6429821A (en) * | 1987-07-24 | 1989-01-31 | Nec Corp | Thin film field effect type transistor element array and its production |
JPS6444419A (en) * | 1987-08-11 | 1989-02-16 | Fujitsu Ltd | Liquid crystal display panel |
JPH0244318A (en) * | 1988-08-05 | 1990-02-14 | Toshiba Corp | Display device |
JPH03243925A (en) * | 1990-02-13 | 1991-10-30 | Ind Technol Res Inst | Liquid-crystal display and manufacture |
JPH06194688A (en) * | 1992-10-09 | 1994-07-15 | Fujitsu Ltd | Thin film transistor matrix device and manufacturing method thereof |
JP2004514950A (en) * | 2000-12-02 | 2004-05-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Pixelation devices such as active matrix liquid crystal displays |
JP2007500452A (en) * | 2003-05-20 | 2007-01-11 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Field effect transistor configuration and method of manufacturing field effect transistor configuration |
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JPS5742075A (en) * | 1980-08-27 | 1982-03-09 | Seiko Instr & Electronics | Liquid crystal display panel |
JPS5997178A (en) * | 1982-11-25 | 1984-06-04 | 三菱電機株式会社 | Matrix type display unit |
JPS6073666A (en) * | 1983-09-30 | 1985-04-25 | セイコーエプソン株式会社 | Drive circuit-built-in active matrix panel |
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1985
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Publication number | Priority date | Publication date | Assignee | Title |
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JPS5742075A (en) * | 1980-08-27 | 1982-03-09 | Seiko Instr & Electronics | Liquid crystal display panel |
JPS5997178A (en) * | 1982-11-25 | 1984-06-04 | 三菱電機株式会社 | Matrix type display unit |
JPS6073666A (en) * | 1983-09-30 | 1985-04-25 | セイコーエプソン株式会社 | Drive circuit-built-in active matrix panel |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63216031A (en) * | 1987-03-05 | 1988-09-08 | Mitsubishi Electric Corp | Display device |
JPS63278895A (en) * | 1987-05-09 | 1988-11-16 | 株式会社 半導体エネルギ−研究所 | Card having display function and memory capacity |
JPS63278894A (en) * | 1987-05-09 | 1988-11-16 | 株式会社 半導体エネルギ−研究所 | Card having display function and memory capacity |
JPS6429821A (en) * | 1987-07-24 | 1989-01-31 | Nec Corp | Thin film field effect type transistor element array and its production |
JPS6444419A (en) * | 1987-08-11 | 1989-02-16 | Fujitsu Ltd | Liquid crystal display panel |
JPH0244318A (en) * | 1988-08-05 | 1990-02-14 | Toshiba Corp | Display device |
JPH03243925A (en) * | 1990-02-13 | 1991-10-30 | Ind Technol Res Inst | Liquid-crystal display and manufacture |
JPH0684436U (en) * | 1990-02-13 | 1994-12-02 | インダストリアル テクノロジー リサーチ インスチチュート | Liquid crystal display |
JPH06194688A (en) * | 1992-10-09 | 1994-07-15 | Fujitsu Ltd | Thin film transistor matrix device and manufacturing method thereof |
JP2004514950A (en) * | 2000-12-02 | 2004-05-20 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Pixelation devices such as active matrix liquid crystal displays |
JP2007500452A (en) * | 2003-05-20 | 2007-01-11 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Field effect transistor configuration and method of manufacturing field effect transistor configuration |
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