JPS61174841A - spread spectrum communication system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention uses double scrambling of the hopping pattern and the signal itself to obtain a signal for capturing the hopping pattern;
The present invention relates to a spread spectrum communication system that uses the same bits as a frame synchronization signal for scrambling signals on a frame-by-frame basis.

(Prior Art) In a conventional spread spectrum communication system using frequency hopping, a phase discontinuity point occurs in the carrier because the outputs of a plurality of synthesizers are combined and switched for use as a carrier.

Therefore, it is not suitable for a receiver using a coherent detection method, and it has been particularly difficult to realize a high-speed device.

Non-coherent receivers require more complex circuits, have restrictions on channel spacing for each carrier frequency, and are less favorable than coherent receivers in terms of interference.

Furthermore, in the conventional spread spectrum method, the synchronization signal is captured by pattern matching of fffiW patterns. Pattern matching usually requires a complicated circuit called a delay lock loop, and it takes time to capture a spectrum with a long code length.

(Object of the Invention) An object of the present invention is to provide a spread spectrum communication system that can capture a spectrum without using a complicated circuit called a delay lock loop.

(Structure of the Invention) In order to achieve the above object, the spread spectrum communication system according to the present invention is a frequency hopping coherent detection type spread spectrum system, which uses double scrambling of the hopping pattern and the signal itself, The same bit is used for the hopping pattern capture signal and the frame synchronization signal for scrambling the signal in units of frames.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings and the like.

FIG. 5 shows a principle block diagram of an embodiment of the transmitting system of the spread spectrum communication system according to the present invention, and FIG. 6 shows an embodiment of the receiving system.

First, the block diagram of the transmission system, FIG. 5, will be explained.

The transmission system block is given an audio signal 3 and a data signal 4 as input signals, and a bit synchronization signal 1 and a frame synchronization signal 2 as synchronization signals.

The audio signal 3 is connected to a low-pass filter 6 via a pre-emphasis circuit 5, band-limited, and A/D converted 7.
Alternatively, it is processed by an ADM8 or the like and converted into a digital signal.

The digital signal is input to the encoder 9 together with the data signal 4 and converted into serial data.

An error correction code is added to this serial data by an error correction code adding circuit 10, interleaved by an interleave circuit 11, scrambled by a 10th order polynomial circuit, and a frame synchronization signal is also added at the same time.

On the other hand, the RF carrier is frequency-hopped using a frequency hopping pattern based on a seventh-order polynomial and a sweep signal for acquisition.

This carrier is a signal scrambled by a scrambling circuit 12, modulated by a phase modulator 14, and outputted as an RF output 15.

Next, the blocks of the receiving system will be explained with reference to FIG.

The received RF signal 16 is captured by the capture circuit 17, the PLL of the receiver is locked, and the bit synchronization signal 21. A polynomial is generated using the frame synchronization signal 22 and a hopping pattern is reproduced using the hopping pattern circuit 19.
The LL is kept locked, and at the same time, a 10th order polynomial is generated and descrambled by the descrambling circuit 20.

Thereafter, the deinterleaving circuit 23 deinterleaves the error correction circuit 24, the decoder 25 separates the audio PCM signal and the data signal 29, and the D/A converter 26 converts the audio PCM signal into an audio signal. converted, low pass filter 27, de-emphasis circuit 2
8 to the output terminal 30.

FIG. 1 shows a signal frame structure of an embodiment of the SS system according to the present invention.

One frame consists of 210 = 1024 bits,
Furthermore, one frame consists of 27=128 bits8
divided into two subframes.

The signal in one frame has a code length of 1024 bits.
The first 16 bits of the frame are a synchronization signal and are therefore removed from the scramble, forming a specific synchronization pattern.

The frequency-hopped carrier is PSK-modulated with a signal scrambled with this 10th order PN.

On the other hand, within one subframe, there are 7 bits with a code length of 128 bits.
The carrier frequency is hopped in the next series of parallel PN frequency hopping turns.

However, the first 16 of the first subframe of one frame
The bits are removed from the seventh order PN frequency hopping pattern because the carrier frequency is digitally swept as shown in FIG. 2 for receiver PLL acquisition.

In the present invention, the 16 bits for acquisition are the same as the 16 bits for frame synchronization.

In this way, the signal is 2" = 102 per frame.
4-bit PN and 27=128 per subframe
The bit PN frequency is doubly scrambled using a hopping pattern, and within one frame, the frequency hopping pattern is repeated eight times in units of subframes.

Next, details of the modulation/demodulation section of the embodiment of the spread spectrum communication system according to the present invention will be explained.

FIG. 7 is a detailed block diagram of the modulator.

First, carrier frequency hopping will be explained.

A PN generating circuit 40 generates a PN based on a seventh-order polynomial synchronized with bits and frames.

Within one 1024-bit frame, 128 bits according to this PN
It is repeated eight times in units of subframes, each cycle of which is a bit.

The frequency hopping signal for the first 16 bits of the frame is a sweep pattern signal for acquisition, and is provided by the frame synchronization control section 38.

The PN frequency hopping pattern signal or acquisition sweep pattern signal is selected by the switch 42 and sent to the D/A converter 43.

That is, for the first 16 bits of the frame, the acquisition sweep pattern from the synchronization control section 38 is provided to the D/A converter 43 with the switch 42 in the down state.

From the 17th bit to the 1024th bit, a PN frequency hopping pattern signal based on a seventh-order polynomial is supplied to the D/A converter 43 with the 'switch 42 in the up state.

In this way, when frequency hopping for one frame is completed, the switch 42 is turned down, and the same cycle is repeated.

In this way, the frequency hopping signal is applied to the D/A converter 43, and the converted signal is waveform-shaped by the hold circuit 44 and applied to the VCO 45.

The VCO 45 is frequency modulated by the frequency hopping signal from the hold circuit 44, and a frequency hopping carrier, that is, a carrier whose spectrum is spread, is generated.

Since this carrier is PSK modulated, it is divided into two systems. One side remains as it is, and the other side is set to 1 by the phase shifter 46.
The phase is changed by 80° and selected by the switch 47, and the PS
A K signal is generated.

On the other hand, the interleaved signal is scrambled with a PN signal using a 10th order polynomial synchronized with the frame. This scrambled signal and the frame synchronization pattern signal are selected by switch 41 and applied to the PSK modulator.

That is, the first 16 bits of one frame are a frame synchronization pattern signal, which is generated within the interleave circuit 37 and sent directly to the PSK modulator without being scrambled via the switch 41 in the upper state.

The 17th to 1024th bits from interleaving circuit 37 are scrambled by polynomial 39 and sent to the PSK modulator via switch 41 switched to the down state.

In the next frame, the switch 41 is in the up position and the same cycle is repeated.

Next, a detailed block diagram of the demodulator shown in FIG. 8 will be explained.

The fJ [device can be roughly divided into a digital signal processing section surrounded by a dotted line and an RF multiplied signal demodulation section. The RF signal demodulation section includes a PSK demodulation section using Costas loops 50 to 58, a capture frequency sweep signal detection section 59.61, an AFC section 60, a frequency hopping PN pattern signal offset voltage generation section 62.63, and 64. ．．
It is divided into 65 bit synchronization signal extraction sections.

The initial setting is such that the Costas loop loop filter 57 has a wide band, a high loop gain, and a wide cab chia range.

In this state, when a certain RF multiplied signal is captured, the frequency change is output from the low-pass filter 57 as a demodulated signal. When no signal is being captured, and when a frequency hopping pattern signal other than the capturing frequency sweep signal is being demodulated, noise or PN is demodulated and output from the loop filter 57.

When this noise or PN output is applied to the acquisition sweep signal matched filter 59, its output voltage or output current is limited.

However, when the capture sweep signal is similarly demodulated and output and applied to the matched filter 59, a waveform φ5S(t) that is the same as the autocorrelation function of the capture sweep signal as shown in FIG. 3 or 4 is output. be done.

The peak value of the output of φ5S(t) is due to noise or PN
Since the value is larger than the output at the time of input, it can be determined that the acquisition sweep signal has been received.

In reality, a threshold value is set slightly smaller than the maximum value of φ5S(t), and when the output of the matched filter 59 exceeds this threshold value, the reception system determines that the capture sweep signal has been received. Threshold circuit 61
sends a determination signal to the control circuit 70.

The threshold level is set to the response output level of the matched filter when the 12th and 13th bits in FIG. 4 are input.

On the other hand, in parallel with this, a PSK demodulated signal is output from the low-pass filter 56 of the Costas loop, and the differential circuit 64 outputs a PSK demodulated signal.
It is converted into a pulse through a threshold circuit 65, noise is removed by a threshold circuit 65, a descrambling circuit 77, a zero detection circuit 72, a frame synchronization signal extraction circuit 73, and a vCXO 74.
, 75.

First, a 64KHz bit clock signal is extracted by VCOX74.75. The control circuit 70 starts the zero detection circuit 72 based on the reception determination signal of the acquisition sweep signal described above.

The PSK demodulated frame synchronization signal has 1110 patterns selected for the 13th to 16th bits, so zero detection plane! i! It can be determined that the first O detected after the start of 872 is the last bit of the frame synchronization signal, that is, the 16th bit of the frame.

Since the frame synchronization signal has been extracted and determined, the zero detection circuit 72 starts the descrambling circuit 77 from the state of the 17th bit.

A signal from the frame synchronization signal extraction circuit 73 is used as a frame synchronization signal for the subsequent second frame and subsequent frames by switching the switch 76.

This switching is performed by the control circuit 70.

In this way, descrambling is started and the signal is further deinterleaved and output.

In exactly the same manner as the descrambling circuit 77 starts operating, the frequency hopping signal reproducing circuit 71 starts operating in parallel and starts generating a PN signal.
．． The voltage is sent to the offset voltage generating section 63, further added to the phase error voltage of the Costas loop by the adder 54, and then supplied to the VCO 53.

At the same time as this offset voltage is supplied, the control circuit 7
Costas loop low pass filter 55, 56 by 0
．． 57 has been made narrower and the loop gain has been lowered,
It is strong against interference, lowers the threshold level of PSK demodulation, and obtains characteristics unique to the spread spectrum method.

The narrow locking range of the Costas loop sacrificed by such constant switching can be solved by the offset voltage of the reproduced frequency hopping pattern described above.

(Effects of the Invention) As explained in detail above, the frequency hopping coherent detection spread spectrum communication system according to the present invention has a capture pattern in the hopping pattern, and the signal is processed frame by frame. There is a synchronization pattern, and both patterns are implemented using the same bits. Therefore, the frequency hopping pattern and the frame can be synchronized at the same time, simplifying the circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a signal frame structure of an embodiment of a spread spectrum communication system according to the present invention. FIG. 2 is a detailed diagram of the frame pattern. FIG. 3 is a graph showing the operation of the matched filter. FIG. 4 is a graph showing the response on the receiving side. FIG. 5 is a block diagram showing an embodiment of a transmission system of a spread spectrum communication system according to the present invention. FIG. 6 is a block diagram showing an embodiment of a receiving system of a spread spectrum communication system according to the present invention. FIG. 7 is a detailed block diagram of a modulator for a spread spectrum communication system according to the present invention. FIG. 8 is a detailed block diagram of a demodulator for a spread spectrum communication system according to the present invention. 1...Bit synchronization signal 2...Frame synchronization signal 3...Audio signal human power 4...Data signal human power 5
...Pre-emphasis circuit 6...Low pass filter 7...A/D RQ! I
s8...ADM 9...Encoder 10...Error correction code addition circuit 11...Interleave circuit 12...Scrambling circuit 13...Hopping pattern generation circuit 14...Phase modulator (PSK) ) 15.16... RF ratio output 17... Capture circuit 18
... PSK demodulator 19 ... Hopping pattern regenerator 20 ... Descramble circuit 21 ... Bit synchronization signal 22 ... Frame synchronization signal 23 ... Deinterleave circuit 24 ... Error correction circuit 25・・・Decoder 26・
・・D/ASE[H27...Low pass filter 28・
...De-emphasis circuit 29...Data signal 30...Audio output 31
．． 35...Bit synchronization signal 32.34...Frame synchronization signal 33...Bit stream 36...RAM37
...Interleave circuit 38...Frame synchronization control section 39...Polynomial circuit 40...PN generation circuit 41.42...Switch 43...D/A converter 44...Hold circuit 45.・vC046・
...Phase shifter 47...Switch 48...
RF ratio output 49...RF input 50-58...
・RF signal demodulation section 59, 61... Frequency sweep signal detection section 60 for acquisition...
- AFC section 62.63...Offcent voltage generation section for frequency hopping PN pattern signal 64.65...Bit synchronization signal extraction section 66...Control signal 67...Detection signal 68...7th order PN signal 69...PSK demodulated signal 70...Control circuit 71...Frequency hopping signal regeneration circuit 72...Zero detection circuit 73...Frame synchronization signal extraction circuit 74.75/VCXO76/X switch 77... Descramble circuit 78...RAM 79...Deinterleave circuit 80...Bit stream 81...Frame synchronization signal 82...Bit synchronization signal Patent applicant Kyocera Co., Ltd. Agent Patent attorney I) Ro 15085 Patent Application No. 15085 2, Name of the invention Spread spectrum communication system 3, Relationship with the person making the amendment Patent applicant 4, Sub-agent

Claims (1)

[Claims] This is a frequency hopping coherent detection spread spectrum system that uses double scrambling of the hopping pattern and the signal itself, and uses the same bits for the hopping pattern capture signal and the frame synchronization signal for frame-by-frame scrambling of the signal. A spread spectrum communications system configured for use.