JPS61174649A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61174649A JPS61174649A JP1520985A JP1520985A JPS61174649A JP S61174649 A JPS61174649 A JP S61174649A JP 1520985 A JP1520985 A JP 1520985A JP 1520985 A JP1520985 A JP 1520985A JP S61174649 A JPS61174649 A JP S61174649A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- photoresist
- oxide film
- semiconductor device
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は1表面絶縁層が酸化膜および窒化膜の二層構造
となっている半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device in which one surface insulating layer has a two-layer structure of an oxide film and a nitride film.
(従来技術および問題点)
半導体装置の表面絶縁層を、酸化膜および窒化膜の二層
構造にすることにより1種々の特性が向上することは良
く知られている。(Prior Art and Problems) It is well known that various characteristics can be improved by forming the surface insulating layer of a semiconductor device into a two-layer structure of an oxide film and a nitride film.
この種の半導体装置の製造方法としては、電極コンタク
ト用窓形成前の装置表面全面に窒化膜を被覆する方法と
、必要な領域上のみに窒化膜を被覆する方法とが掲げら
れるが、装置特性および製造工程数の点から前者の全面
窒化膜被覆法が多用されている。There are two methods for manufacturing this type of semiconductor device: one is to coat the entire surface of the device with a nitride film before forming the electrode contact window, and the other is to coat the nitride film only on the necessary areas. In view of the number of manufacturing steps, the former method of covering the entire surface with a nitride film is often used.
この全面窒化膜被覆法における問題点としては。The problems with this method of covering the entire surface with nitride film are as follows.
電極コンタクト用窓を開孔する際、窒化膜と酸化膜を同
時に開孔するため、第4図に示すように。When opening the electrode contact window, the nitride film and the oxide film are opened at the same time, as shown in FIG.
窒化膜aのオーバーハング状態を招き易いことである。This tends to cause an overhang state of the nitride film a.
第4図においてbは酸化膜、Cはシリコン基板である。In FIG. 4, b is an oxide film and C is a silicon substrate.
これを改善するためには種々の方法が考えられるが、一
般的には、第5図に示すように、絶縁層の上層の窒化膜
aを広く開孔し、下層の酸化膜すを窒化膜aに設けられ
た開孔部内に開孔するいわゆるステップエツチング法が
用いられる。このようにして形成された電極コンタクト
用窓に金属を蒸着して電極dを形成し、第5図に示す構
造の半導体装置を形成している。この図から分かるよう
に、従来の半導体装置では、酸化膜bの一部面eが露出
している。Various methods can be considered to improve this problem, but in general, as shown in Figure 5, the upper nitride film a of the insulating layer is opened widely, and the lower oxide film is replaced with a nitride film. A so-called step etching method is used in which holes are formed in the openings provided in a. Metal is deposited on the electrode contact window thus formed to form an electrode d, thereby forming a semiconductor device having the structure shown in FIG. 5. As can be seen from this figure, in the conventional semiconductor device, a part of the surface e of the oxide film b is exposed.
(発明の目的)
本発明の半導体装置は、上記した半導体装置にさらに改
良を加え、半導体特性を著しく向上させた半導体装置を
提供−することを目的とする。(Object of the Invention) An object of the semiconductor device of the present invention is to further improve the above-described semiconductor device and provide a semiconductor device with significantly improved semiconductor characteristics.
(発明の構成)
本発明の半導体装置は、半導体層の表面全体を絶縁する
表面絶縁層が酸化膜と窒化膜との二層によって構成され
、上層の窒化膜が下層の酸化膜より広く開孔されて電極
コンタクト用窓が形成されたものにおいて、前記酸化膜
の表面全体が前記窒化膜および電極によって被覆されて
なるものである。(Structure of the Invention) In the semiconductor device of the present invention, the surface insulating layer that insulates the entire surface of the semiconductor layer is composed of two layers of an oxide film and a nitride film, and the upper nitride film has wider pores than the lower oxide film. In this case, the entire surface of the oxide film is covered with the nitride film and the electrode.
(実施例)
第1図に本発明にかかる半導体装itAの構造を示し、
第2図(a)〜(d)にその製造工程を示している。(Example) FIG. 1 shows the structure of a semiconductor device itA according to the present invention,
The manufacturing process is shown in FIGS. 2(a) to 2(d).
本例の半導体装置AはNPN型のトランジスタであって
、P”、N”の各半導体層の拡散が行われたN型Si基
板1上に酸化膜2.窒化膜3が形成され、各電極コンタ
クト用窓8に電極9が形成されて、酸化膜2の表面全体
が窒化膜3および電極9によって被覆された構造のもの
である。The semiconductor device A of this example is an NPN type transistor, and an oxide film 2. A nitride film 3 is formed, an electrode 9 is formed in each electrode contact window 8, and the entire surface of the oxide film 2 is covered with the nitride film 3 and the electrode 9.
以下に、第2図(al〜(d)を参照して半導体装置A
の製造工程を説明する。The semiconductor device A will be described below with reference to FIGS.
The manufacturing process will be explained.
(a)Si基板1上の全面に熱酸化あるいはCVD法等
により酸化膜(Sint膜)2を形成し、続いて窒化膜
(SisNi膜)3を形成する。窒化膜3上にホトレジ
スト4を塗布し所望のパターンに形成するとともに、こ
のパターン化されたホトレジスト4をマスクとして窒化
膜3をプラズマエツチング等により処理し開孔部5を形
成する(第1図(a)参照〕。(a) An oxide film (Sint film) 2 is formed on the entire surface of the Si substrate 1 by thermal oxidation or CVD, and then a nitride film (SisNi film) 3 is formed. A photoresist 4 is applied onto the nitride film 3 and formed into a desired pattern, and the nitride film 3 is processed by plasma etching or the like using the patterned photoresist 4 as a mask to form an opening 5 (see FIG. 1). See a)].
偽) 次に、ホトレジスト4を除去した後、再度ホトレ
ジスト6を塗布し、開孔部5より十分内側に酸化膜2の
開孔部をパターニングする〔第2図山)参照〕、バター
ニングされた開孔部の寸法は1次工程のエツチングによ
るシフト等を考慮した寸法とする。(False) Next, after removing the photoresist 4, photoresist 6 is applied again, and the opening of the oxide film 2 is patterned sufficiently inside the opening 5 [see Fig. 2, mountain)]. The dimensions of the opening are determined in consideration of shifts caused by etching in the primary process.
(C) このパターニングされたホトレジスト6をマ
スクとして酸化膜2をHF系エッチャント等によりエツ
チング処理し、窒化膜3に形成した前記開孔部5の内部
に開孔部7を形成し、電極コンタクト用窓8が形成され
る〔第2図(C)参照〕。(C) Using this patterned photoresist 6 as a mask, the oxide film 2 is etched with an HF-based etchant, etc., and an opening 7 is formed inside the opening 5 formed in the nitride film 3 for use as an electrode contact. A window 8 is formed (see FIG. 2(C)).
(d) ホトレジスト6を除去し、蒸着等により電極
コンタクト用窓8に電極9(通常AI)を形成する〔第
2図(d)参照〕。(d) The photoresist 6 is removed and an electrode 9 (usually AI) is formed in the electrode contact window 8 by vapor deposition or the like [see FIG. 2(d)].
上記工程により製造された本発明にかかる半導体装置A
では、装置表面の全体が電極9および窒化膜3で被覆さ
れ、酸化膜2は表面に露出しない。Semiconductor device A according to the present invention manufactured by the above steps
In this case, the entire surface of the device is covered with the electrode 9 and the nitride film 3, and the oxide film 2 is not exposed on the surface.
酸化膜2が表面に露出しない効果は、NPN形のトラン
ジスタ特性において実験的に確認された一部3図にNP
N第N形ンジスタの電流増幅率のコレクタ電流依存性を
示す0図において、Q印は酸化膜が窒化膜に覆われて表
面に現れない構造の本発明にかかる半導体装置Aの特性
曲線、x印は酸化膜が窒化膜に覆われているが一部表面
に露出した構造6半導体装置(第5図に示すもの)の特
性曲線、Δ印は窒化膜が無く酸化膜が表面全体に露出し
た半導体装置の特性曲線である。この図から分かるよう
に、全面を窒化膜で被覆、するだけでもかなりの特性改
善が得られるが9本発明の半導体装置Aでは、コレクタ
電流の低電流領域での電流増幅率(h□)が低下せず、
トランジスタ動作特性がさらに改善される。The effect that the oxide film 2 is not exposed on the surface is due to the fact that some NPN transistor characteristics have been experimentally confirmed in Figure 3.
In Figure 0, which shows the collector current dependence of the current amplification factor of the N-th type transistor, the mark Q is the characteristic curve of the semiconductor device A according to the present invention in which the oxide film is covered with the nitride film and does not appear on the surface, x The mark is the characteristic curve of a Structure 6 semiconductor device (shown in Figure 5) in which the oxide film is covered by the nitride film but partially exposed on the surface, and the mark Δ is the characteristic curve where the oxide film is exposed on the entire surface without the nitride film. It is a characteristic curve of a semiconductor device. As can be seen from this figure, a considerable improvement in characteristics can be obtained by simply covering the entire surface with a nitride film.9 In the semiconductor device A of the present invention, the current amplification factor (h□) in the low collector current region does not decrease,
Transistor operating characteristics are further improved.
(発明の効果)
以上説明したように2本発明にかかる半導体装置によれ
ば、従来の酸化膜および窒化膜の二層構造の表面絶縁層
を形成することにより得られる特性の向上をさらに助長
することができ、より高性能なICの開発が可能となっ
た。(Effects of the Invention) As explained above, according to the semiconductor device according to the present invention, the improvement in characteristics obtained by forming a conventional surface insulating layer with a two-layer structure of an oxide film and a nitride film is further promoted. This made it possible to develop higher-performance ICs.
【図面の簡単な説明】
第1図ないし第2図(a)〜(dlは本発明にかかる半
導体装置の一実施例を示し、第1図は縦断面図。
第2図(a)〜(d)は製造工程を示す縦断面図、第3
図はコレクタ電流対電流増幅率(hyz)の特性図。
第4図はオーバーハング状態を示す縦断面図、第5図は
従来の半導体装置の縦断面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 (a) to (dl show an embodiment of a semiconductor device according to the present invention, and FIG. 1 is a longitudinal cross-sectional view. d) is a vertical cross-sectional view showing the manufacturing process;
The figure is a characteristic diagram of collector current versus current amplification factor (hyz). FIG. 4 is a vertical cross-sectional view showing an overhang state, and FIG. 5 is a vertical cross-sectional view of a conventional semiconductor device.
Claims (1)
と窒化膜との二層によって構成され、上層の窒化膜が下
層の酸化膜より広く開孔されて電極コンタクト用窓が形
成されたものにおいて、 前記酸化膜の表面全体が前記窒化膜および 電極によって被覆されてなることを特徴とする半導体装
置。[Claims] 1) The surface insulating layer that insulates the entire surface of the semiconductor layer is composed of two layers: an oxide film and a nitride film, and the upper nitride film has holes wider than the lower oxide film to form an electrode contact. 1. A semiconductor device in which a window is formed, wherein the entire surface of the oxide film is covered with the nitride film and the electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1520985A JPS61174649A (en) | 1985-01-29 | 1985-01-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1520985A JPS61174649A (en) | 1985-01-29 | 1985-01-29 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61174649A true JPS61174649A (en) | 1986-08-06 |
Family
ID=11882476
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1520985A Pending JPS61174649A (en) | 1985-01-29 | 1985-01-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61174649A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01105560A (en) * | 1987-10-17 | 1989-04-24 | Sony Corp | Semiconductor device and manufacture thereof |
-
1985
- 1985-01-29 JP JP1520985A patent/JPS61174649A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01105560A (en) * | 1987-10-17 | 1989-04-24 | Sony Corp | Semiconductor device and manufacture thereof |
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