JPS61170677A - Logical circuit tester - Google Patents

Abstract

PURPOSE:To induce easily and surely a pseudo fault and to check fault detecting capacity at a high sped by providing means for interrupting the electrical contact with a logical circuit by the instruction from a control part. CONSTITUTION:One of the input terminals 3 of the logical circuit 2 with which the pseudo fault is desired to be induced is selected by the control part 8. A control signal 14 is impressed to a tri-state output element 19 corresponding to a terminal 4 of a tester connected to said terminal. A signal line 20 is put into a high impedance state. The terminal 4 and the terminal 3 are held electrically disconnected by such state. The fault detecting capacity of the test pattern when the pseudo fault is induced is examined by carrying out a series of ordinary tests thereafter.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic circuit testing device.

[Conventional technology]

Conventionally, this type of logic circuit testing equipment applies a series of given test patterns to the input terminal of the logic circuit under test.
The quality of the logic circuit under test is determined by observing the response from the output terminal of the logic circuit under test and comparing it with a given expected value (Nikkei Electronics, 1
980. P88-P105) Whether the test pattern given at this time has the ability to truly detect a fault in the logic circuit under test.

It was necessary to actually create a pseudo fault in the logic circuit under test and investigate. As a means of causing this false failure, an insulator is manually placed between any terminal of the logic circuit under test and the terminal of the logic circuit test equipment that is in contact with it, making it impossible to apply a normal test pattern or observe the output response. By doing so, a method was used to create a situation as if a fault had occurred in the logic circuit under test.

[Problem that the invention seeks to solve]

However, with this method, as the terminals of logic circuits to be tested have become increasingly dense, multi-terminal, and miniaturized in recent years, it is no longer possible to manually sandwich the insulating material, causing false failures during testing. There was a problem in that it was not possible to examine the true pattern detection ability.

An object of the present invention is to provide a logic circuit testing device that can generate a pseudo fault in a logic circuit without manual intervention.

[Means for solving problems]

The present invention provides a means for cutting off electrical contact with any input terminal according to instructions from a control unit when marking a test pattern on an input terminal of a logic circuit, and a means for cutting off electrical contact with an arbitrary input terminal according to an instruction from a control unit when marking a test pattern on an input terminal of a logic circuit, and a means for cutting off electrical contact with an arbitrary input terminal when a test pattern is marked on an input terminal of a logic circuit. By providing means for cutting off electrical contact with any output terminal according to instructions from the controller, a pseudo fault can be automatically generated in the logic circuit without manual intervention.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a logic circuit testing device according to the present invention.

This logic circuit testing device includes a memory section 6 in which a series of test patterns and their expected values are stored, a control section 8,
The terminal group 4 in contact with the input/output terminal group 8 of the logic circuit 2 to be tested and the test pattern 10 outputted from the memory section 6 are applied to the logic circuit 2 by the control signal group 16 from the control section 8. , or the driver/receiver group 5 (terminal 8.4), a comparator 9 that compares the expected value 11 output from the memory section 6 and the output response value 12 output from the driver/receiver group 5, and the comparison result is sent to the control section. 8 to signal line 15
The display unit 7 is equipped with a display section 7 for displaying images.

FIG. 2 is a block diagram of one of the driver/receiver groups 5 of FIG.

The driver circuit z2 turns on when the control signal 16 is Ill and outputs the test pattern 10 to the signal line 18, and the receiver circuit 21 turns on when the control signal 16 is IQI and outputs the test pattern 10 to the signal line 1.
The output response value 1z on 8 is output.

The tri-state output element 19 has its output, that is, the signal line, placed in a high impedance state by the control signal 14, and electrical contact with the terminal 4 (terminal 8) is cut off.

Next, the operation of this embodiment will be explained.

+1) First, the normal test procedure will be explained.

First, the driver circuit 2z is selected by the control signal 16 from the control section 8, and the tri-state output element 19 is configured to pass the signal on the signal line 18 to the signal line 20 as is by the control signal 141C. In this state, the test pattern 10 and the expected value 11 are output from the memory section 6, and the test pattern IO is output from the driver/receiver group 5.
and is applied to the logic circuit 2 via the input/output terminal group 8 of the terminal circuit 2 of the test device. Thereafter, the receiver circuit 21 is selected this time by the control signal 16&C from the control unit 8, and the output response value 1z of the logic circuit 2 is
The signal is input to the comparator 9 via the output terminal 8, the terminal number of the test device, and the driver/receiver group 5. Then, the comparator 9 compares the expected value 11 output from the memory section 6 with the output response value 1z, and outputs the comparison result to the control section 8. The control section 8 sends the comparison results to the display section 7 via the signal line 15 as necessary, and displays them as test results. A normal test is completed by repeating the above series of operations for all test patterns.

(2) Next, the procedure for generating a pseudo failure will be explained.

Prior to the above-mentioned series of normal test procedures, the control section 8 selects one of the input or output terminals 8 of the logic circuit 20 to cause a pseudo fault, and connects the terminal 4 of the test equipment connected to that terminal. A control signal 14 is applied to the corresponding tristate output element 19, and the signal line 20 is placed in a high impedance state. In this state, the terminal 4 of the test device and the input/output terminal 8 of the logic circuit are electrically disconnected. After that, by performing the above-mentioned series of normal tests, it becomes possible to examine the fault detection ability of the test pattern when a pseudo fault occurs.

〔Effect of the invention〕

As explained above, the present invention includes means for cutting off electrical contact with the logic circuit according to an instruction from the control unit.
This method has the advantage that pseudo faults can be easily and reliably generated, and the fault detection ability of the test pattern can be confirmed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a logic circuit testing device according to the present invention, and FIG. 2 shows a first driver/receiver group 5.
01 is a block diagram showing one. 1: Logic circuit testing device. 2: Logic circuit (test target). 8: Logic circuit 20 eight power/output terminal group. 4 = terminal group of logic circuit testing device 1; 5: Driver/receiver group. 6: Memory section, 7: Display section. 8: Control unit, 9: Comparator. 10: Test pattern, 11: Expected value. lz: output response value, 14. #, 16: Control signal. 18: Signal line through which the applied test pattern/output response value passes. 19 Ni dry state output element. 2IO=test pattern applied/output response value/signal line that goes into high impedance state. 21: L/seiver circuit, 22: driver circuit.

Claims (1)

[Claims] By applying a given series of test patterns to an input terminal of a logic circuit to be tested, observing the response from an output terminal of the logic circuit, and comparing it with a given expected value. a logic circuit testing device for determining the quality of the logic circuit, comprising: means for cutting off electrical contact with any of the input terminals according to instructions from a control unit when applying the test pattern to the input terminals; and the output terminals. 1. A logic circuit testing device comprising means for cutting off electrical contact with any of the output terminals according to an instruction from a control section when observing a response of the logic circuit.