JPS61170038A - Metal mold for resin sealing - Google Patents
Metal mold for resin sealingInfo
- Publication number
- JPS61170038A JPS61170038A JP914285A JP914285A JPS61170038A JP S61170038 A JPS61170038 A JP S61170038A JP 914285 A JP914285 A JP 914285A JP 914285 A JP914285 A JP 914285A JP S61170038 A JPS61170038 A JP S61170038A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- mold
- lead
- outer lead
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 79
- 239000011347 resin Substances 0.000 title claims abstract description 79
- 238000007789 sealing Methods 0.000 title claims description 21
- 239000002184 metal Substances 0.000 title abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 238000000465 moulding Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 14
- 238000007747 plating Methods 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000005219 brazing Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000005488 sandblasting Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
- B29C45/14336—Coating a portion of the article, e.g. the edge of the article
- B29C45/14418—Sealing means between mould and article
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は樹脂封止型半導体装置の樹脂モールド部を成
形するため−の樹脂封止用金型に関するものであり、特
に、樹脂封止工程において該半導体装置のアウターリー
ドの上下両面に沿う樹脂の付着を効果的に防止すること
ができる改良された樹脂封止用金型に関するものである
。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin encapsulation mold for molding a resin mold part of a resin encapsulation type semiconductor device, and particularly relates to a resin encapsulation mold for molding a resin mold part of a resin encapsulation type semiconductor device. The present invention relates to an improved mold for resin sealing that can effectively prevent adhesion of resin along both upper and lower surfaces of an outer lead of the semiconductor device.
［発明の技術的背景］
第８図は樹脂１４止型半導体装置の製造工程において樹
脂封止工程終了直後のリードフレーム１と樹脂モールド
部２とを示した斜視図である。 エポキシ樹脂等で成形
された樹脂モールド部２内にはリードフレーム１の一部
であるチップ取付部の上に固着された半導体チップと該
チップ取付部の周囲に配置されたインナーリード部とが
密封される一方、樹脂モールド部２の外側には該インナ
ーリード部の延長部分であるアウターリード１Ａが突出
しており、該アウターリード１Ａはリードフレーム１の
外枠部１Ｂにそれぞれ連結されている。[Technical Background of the Invention] FIG. 8 is a perspective view showing the lead frame 1 and the resin mold part 2 immediately after the resin sealing process is completed in the manufacturing process of a resin molded semiconductor device. A semiconductor chip fixed on a chip mounting part, which is a part of the lead frame 1, and an inner lead part arranged around the chip mounting part are sealed in a resin mold part 2 made of epoxy resin or the like. On the other hand, outer leads 1A, which are extensions of the inner lead parts, protrude from the outside of the resin mold part 2, and the outer leads 1A are connected to the outer frame part 1B of the lead frame 1, respectively.
樹脂封止工程においては、該リードフレーム１のチップ
取付部を樹脂封止用金型のキャビティ内に収容するとと
もにインナーリード部の周囲を該金型のリード押え部で
密着把持し、該キャビティ内に溶ＦＭ１樹脂を圧入して
該樹脂モールド部２を成形するか、その場合、キャビテ
ィ内の圧力が高いため、樹脂の一部がインナーリード部
の外周面に沿って該キャビティ内から漏出するため、樹
脂封止工程終了時には第８図及び第９図に示すようにア
ウターリード１Ａの両側面に漏出樹脂層３が被着した状
態となる。In the resin encapsulation process, the chip attachment part of the lead frame 1 is housed in the cavity of the resin encapsulation mold, and the inner lead part is tightly gripped by the lead holding part of the mold, and the inside of the cavity is Molten FM1 resin is press-fitted into the resin mold part 2, or in that case, because the pressure inside the cavity is high, a part of the resin leaks from the cavity along the outer peripheral surface of the inner lead part. At the end of the resin sealing process, the leaked resin layer 3 is adhered to both sides of the outer lead 1A, as shown in FIGS. 8 and 9.
樹脂封止工程終了後、サンドブラスト加工によって樹脂
モールド部２の表面の樹脂パリやアウターリード１Ａの
両側面の漏出樹脂層３を除去し、更に第１０図に示すよ
うにアウターリード１Ａの表面を半田メッキ層４（半田
付は層のこともある）で被覆した後、リードフレーム１
の外枠部１Ｂの切断除去と各樹脂モールド部毎の分割と
を行うことにより樹脂封止型半導体装置が完成する。After the resin sealing process is completed, the resin paris on the surface of the resin mold part 2 and the leaked resin layer 3 on both sides of the outer lead 1A are removed by sandblasting, and the surface of the outer lead 1A is soldered as shown in FIG. After coating with plating layer 4 (sometimes soldering layer), lead frame 1
A resin-sealed semiconductor device is completed by cutting and removing the outer frame portion 1B and dividing each resin mold portion.
この樹脂封止型半導体装置を用いて電子回路を構成する
場合、樹脂封止型半導体装置を回路基板上に装着し、第
１１図に示すように該回路基板５上に盛り上げたろう材
６の中にアウターリード１Ａを埋設して該アウターリー
ド１Ａを固定接続する。 この場合、アウターリード１
Ａの表面が完全に半田メッキ層４で被覆されていないと
、ろう材６がアウターリード１Ａの表面に良好に這い上
らず、接続不良となりやすいため、アウターリード１Ａ
の表面が完全に半田メッキ層４で被覆されていることが
必要である。When constructing an electronic circuit using this resin-sealed semiconductor device, the resin-sealed semiconductor device is mounted on a circuit board, and as shown in FIG. The outer lead 1A is embedded in the outer lead 1A, and the outer lead 1A is fixedly connected to the outer lead 1A. In this case, outer lead 1
If the surface of the outer lead 1A is not completely covered with the solder plating layer 4, the brazing material 6 will not creep up onto the surface of the outer lead 1A, resulting in a poor connection.
It is necessary that the surface of the solder plating layer 4 be completely covered with the solder plating layer 4.
［背景技術の問題点］
しかしながら、リードフレーム１がプレス打法きで製作
されたものである場合には、リードフレームのｔ４造に
使用されるプレス機械のポンチやダイか摩耗してくると
、リードフレームのリード部の上面及び下面にカエリや
浅い溝が生じやすくなり、す・−ドフレーム表面には傷
や溝として残されていることが多い。 このようにリー
ド部の上面及び下面に傷や溝が残されているリードフレ
ームを使用して樹脂封止を行うと、キャビティ内から漏
出した樹脂がこの傷もしくは溝に流れ込み、その結果樹
脂封止工程終了後のアウタリード１Ａの上面には第１２
図に示すように該溝１ａの中に樹脂３ａが充填された状
態となる。 このようにリード部上面に形成された溝内
に樹脂が充填された状態になると、その侵、サンドブラ
スト加工を行っても該溝１８内から樹脂３ａを除去する
ことができぬうえ、該樹脂３ａの表面には半田メッキが
付着しないため、アウターリード１Ａに対する半田メッ
キ加工を終了した時点では第１３図に示すように該溝内
の樹脂３ａが露出し、該樹脂３ａの表面には半田メッキ
層４が形成されていない状態となる。 そして、このよ
うにアウターリード１Ａに対する半田メッキが不完全な
樹脂封止型半導体装置を前記のように電子回路装置の回
路基板上に搭載すると、第１４図に示すようにアウター
リード１Ａの上面の半田メッキされていない部分（すな
わち該溝１ａに樹脂３ａが充填されている部分）によっ
てろう材６のリード部上面への這い上りが阻止され、従
って、アウターリード１Ａの接続が不十分となる。[Problems in the Background Art] However, when the lead frame 1 is manufactured by a press method, when the punches and dies of the press machine used for making the lead frame T4 wear out, Burrs and shallow grooves are likely to occur on the upper and lower surfaces of the lead portion of the lead frame, and scratches and grooves are often left on the surface of the lead frame. When resin sealing is performed using a lead frame that has scratches or grooves left on the top and bottom surfaces of the lead part, resin leaking from inside the cavity flows into these scratches or grooves, resulting in the resin sealing. After the process is completed, the top surface of the outer lead 1A has a 12th
As shown in the figure, the groove 1a is filled with resin 3a. When the grooves formed on the upper surface of the lead portion are filled with resin, the resin 3a cannot be removed from the grooves 18 even if sandblasting is performed. Since solder plating does not adhere to the surface of the outer lead 1A, when the solder plating process for the outer lead 1A is completed, the resin 3a in the groove is exposed as shown in FIG. 4 is not formed. When a resin-sealed semiconductor device with incomplete solder plating on the outer leads 1A is mounted on the circuit board of an electronic circuit device as described above, the upper surface of the outer leads 1A will be damaged as shown in FIG. The portions that are not solder-plated (that is, the portions in which the grooves 1a are filled with the resin 3a) prevent the brazing material 6 from creeping up onto the upper surface of the lead portion, resulting in insufficient connection of the outer leads 1A.
このように、回路基板への装着時にアウターリードの接
続不良が起こらぬようにするためには、リード部に溝が
つかぬようにリードフレームを製作するか、もしくはリ
ード部の溝に樹脂が充填されぬように樹脂封止を行うこ
とが必要であった。In this way, in order to prevent connection failures of the outer leads when attached to the circuit board, it is necessary to manufacture the lead frame so that there are no grooves in the lead parts, or to fill the grooves in the lead parts with resin. It was necessary to perform resin sealing to prevent this from happening.
［発明の目的］
この発明の目的は、リード部の傷や溝に樹脂が充填され
ぬように樹脂封止を行うことのできる樹脂封止用金型を
提供することである。[Object of the Invention] An object of the present invention is to provide a mold for resin sealing that can perform resin sealing so that the scratches and grooves of the lead portion are not filled with resin.
［発明の概要］
この発明による樹脂封止用金型は、キャビティの外側に
近接した位置に樹脂封止型半導体装置のアウターリード
の上下両面に食い込む突条（もしくは突部）を上下両金
型に形成したことを特徴とするものである。 この発明
の樹脂封止用金型によれば、樹脂封止工程においてキャ
ビティからリード部の上下両面を伝って漏出する樹脂が
該突条によって阻止されるため、該突条より外側のアウ
ターリードの上下両面に前記溝があっても該溝に漏出樹
脂が被着することがない。 その結果、本発明の樹脂封
止用金型を用いて製造した樹脂封止型半導体装置は回路
基板上に装着する際に、アウターリードの一部がろう材
から露出して接続不良を起こすことなく、装着すること
ができる。[Summary of the Invention] The mold for resin sealing according to the present invention has protrusions (or protrusions) that bite into both the upper and lower surfaces of the outer lead of the resin molded semiconductor device at a position close to the outside of the cavity in both the upper and lower molds. It is characterized by being formed. According to the mold for resin sealing of the present invention, since the resin leaking from the cavity along the upper and lower surfaces of the lead part during the resin sealing process is blocked by the protrusion, the outer lead outside the protrusion is blocked. Even if the grooves are provided on both the upper and lower surfaces, leaked resin will not adhere to the grooves. As a result, when a resin-sealed semiconductor device manufactured using the resin-sealed mold of the present invention is mounted on a circuit board, a portion of the outer lead may be exposed from the brazing material, causing a connection failure. It can be installed without any problem.
［発明の実施例］ 第１図は本発明の金型７の要部断面図である。[Embodiments of the invention] FIG. 1 is a sectional view of a main part of a mold 7 of the present invention.
本発明の金型では、その上型７１と下型７２とにキャビ
ティＣの外側の位置においてアウターリード１Ａの上下
両面に食い込み且つ該アウターリードを横切る方向の低
い突条７１ａ、７２ａが設けられていることを特徴とす
る。 このため、樹脂封止工程においてキャビティＣ内
からアウターリード１Ａの上下両面に沿って漏出する樹
脂はこの突条７１ａ、７２ａによってそれよりも外側へ
の流出を阻止されることになる。In the mold of the present invention, the upper mold 71 and the lower mold 72 are provided with low protrusions 71a and 72a that cut into both the upper and lower surfaces of the outer lead 1A at positions outside the cavity C and extend in a direction that crosses the outer lead. It is characterized by the presence of Therefore, in the resin sealing process, the resin leaking from the inside of the cavity C along both the upper and lower surfaces of the outer lead 1A is prevented from flowing outward beyond the ridges 71a and 72a.
第２図は本発明の金型を用いて樹脂封止された半導体装
置の斜視図であり、第３図は第２図の■−■線における
要部断面図である。FIG. 2 is a perspective view of a semiconductor device resin-sealed using the mold of the present invention, and FIG. 3 is a cross-sectional view of a main part taken along the line ■--■ in FIG.
第１図乃至第３図において、１Ｃはリードフレーム１の
チップ取付部、１Ｄはリードフレーム１のインナーリー
ド部、１Ａはアウターリード、８は半導体チップ、９は
ボンディングワイヤ、２は樹脂モールド部、１Ｂはリー
ドフレーム１の外枠部である。In FIGS. 1 to 3, 1C is the chip attachment part of the lead frame 1, 1D is the inner lead part of the lead frame 1, 1A is the outer lead, 8 is the semiconductor chip, 9 is the bonding wire, 2 is the resin mold part, 1B is an outer frame portion of the lead frame 1.
第２図及び第３図に示すように、本発明の金型を用いて
樹脂封止された半導体装置のアウターリード１Ａの上下
両面には樹脂モールド部２の外周部に近接した位置に該
金型の突条７１ａ 、７２ａによって形成された浅いく
ぼみ１ｂが残っている。As shown in FIGS. 2 and 3, on both upper and lower surfaces of the outer lead 1A of the semiconductor device resin-sealed using the mold of the present invention, metal molding is provided at a position close to the outer periphery of the resin mold part 2. A shallow depression 1b formed by the protrusions 71a and 72a of the mold remains.
第４図は第２図のＩＶ −ＩＶ矢視断面図であり、この
位置におけるアウターリード１Ａの上面にはリードフレ
ーム製作時に形成された満１８があり、この溝１１内に
は樹脂３ａが充填されており、且つアウターリード１Ａ
の両側面には漏出樹脂層３が付着している。 すなわら
、この位置■は樹脂封止工程で金型の突条７１ａ、７２
ａがアウターリード１Ａに接触している位置よりも内側
にあるため、アウターリード上面の前記溝１８内にも漏
出樹脂が流れ込んでいる。FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. and outer lead 1A
A leaked resin layer 3 is attached to both side surfaces of. In other words, at this position (2), the protrusions 71a, 72 of the mold are formed during the resin sealing process.
Since the point a is located inside the position where the outer lead 1A is in contact with the outer lead 1A, the leaked resin also flows into the groove 18 on the upper surface of the outer lead.
第５図は第２図のＶ−Ｖ線におけるアウターリード１Ａ
の横断面図である。 第５図から明らかなように、この
位置では、アウターリード１Ａの上面の溝１８には漏出
樹脂が充填されておらず、キャビティＣからの漏出樹脂
はアウターリード１Ａの両側面に漏出樹脂層３として付
着している。Figure 5 shows the outer lead 1A along the V-V line in Figure 2.
FIG. As is clear from FIG. 5, in this position, the groove 18 on the upper surface of the outer lead 1A is not filled with leaked resin, and the leaked resin from the cavity C is deposited on both sides of the outer lead 1A in the leaked resin layer 3. It is attached as.
すなわち、この位置Ｖは樹脂封止工程におりて金型の突
条７１ａ 、７２ａと接触する位置よりも外側にあるた
め、キャピテイＣからの漏出樹脂が該突条７１ａ、７２
ａによってそこから外側への流出が阻止されている。That is, since this position V is outside the position where it contacts the protrusions 71a and 72a of the mold during the resin sealing process, the resin leaking from the cavity C is absorbed into the protrusions 71a and 72a.
A prevents it from flowing outward from there.
従って、本発明の金型を用いて樹脂封止された半導体装
置においては、そのアウターリードの上下面のほとんど
に漏出樹脂が付着していないので、この半導体装置のア
ウターリードに前記のごとき加工（すなわち、サンドブ
ラストによって漏出樹脂層３を除去した後、アウターリ
ード１Ａの表面に半田メッキや半田付けを施す）を施す
と、アウターリード上面に樹脂が付着していないためア
ウターリード上面を第６図に示すように完全に半田メッ
キ１４で被覆することができる。 その結果、該半導体
装置を回路基板上に実装する場合、第１１図に示すよう
にアウターリード１Ａをろう材６の中に完全に埋設する
ことができる。Therefore, in a semiconductor device resin-sealed using the mold of the present invention, most of the upper and lower surfaces of the outer leads are free of leaked resin, so the outer leads of the semiconductor device are processed as described above. That is, when the leaked resin layer 3 is removed by sandblasting and then solder plating or soldering is applied to the surface of the outer lead 1A, the upper surface of the outer lead becomes as shown in FIG. 6 because no resin is attached to the upper surface of the outer lead. As shown, it can be completely covered with solder plating 14. As a result, when the semiconductor device is mounted on a circuit board, the outer leads 1A can be completely buried in the brazing material 6 as shown in FIG.
なお、第１図乃至第３図では金型の突条７１ａ、７２ａ
がキャビティＣ及び樹脂モールド部２よりもかなり外側
にあるように描かれているが、この突条は実際にはキャ
ビティＣに極めて近接した位置に設けられている。In addition, in FIGS. 1 to 3, the protrusions 71a and 72a of the mold are
Although it is depicted as being located far outside of the cavity C and the resin mold part 2, this protrusion is actually provided at a position extremely close to the cavity C.
第７図は、本発明の金型を用いて製造した半導体装置と
従来の金型を用いて製造した半導体装置とについてそれ
ぞれの不良発生率を比較表示したものである。 第７図
において、横軸は頻度すなわちロット数、縦軸は不良発
生率（％）、領域Ａは本発明の金型を使用して製造され
た半導体装置の不良発生率、領域Ｂは従来の金型を使用
して製造された半導体装置の不良発生率を示している。FIG. 7 compares and displays the defect incidence rates of semiconductor devices manufactured using the mold of the present invention and semiconductor devices manufactured using a conventional mold. In FIG. 7, the horizontal axis is the frequency, that is, the number of lots, the vertical axis is the defective rate (%), area A is the defective rate of semiconductor devices manufactured using the mold of the present invention, and area B is the defective rate of the semiconductor devices manufactured using the mold of the present invention. It shows the failure rate of semiconductor devices manufactured using molds.
この図から明らかなように、従来の金型を使用したロッ
トの不良発生率は１０〜３０％であったが、本発明の金
型を使用したロットの不良発生率はほぼ０％になった。As is clear from this figure, the defect rate for lots using the conventional mold was 10-30%, but the defect rate for lots using the mold of the present invention was almost 0%. .
［発明の効果］
以上に説明したように、この発明によれば、アウターリ
ードの上下両面に傷や溝がある場合でもアウターリード
の上下両面に樹脂付着をさせる恐れのない嗣脂封止用金
型が提供され、従って、この発明の嗣脂封市用金型によ
れば、回路基板に実装する時にアウターリードをろう材
中に完全に埋設させることができるような無欠陥の樹脂
封止型半導体装置を製造することができる。[Effects of the Invention] As explained above, according to the present invention, there is provided a sealing metal that does not cause resin to adhere to both the upper and lower surfaces of the outer lead even if there are scratches or grooves on both the upper and lower surfaces of the outer lead. Accordingly, the resin-sealed commercial mold of the present invention provides a defect-free resin-sealed mold that allows the outer lead to be completely embedded in the brazing material when mounted on a circuit board. Semiconductor devices can be manufactured.
第１図は本発明の一実施例の金型の要部断面図、第２図
は本発明の金型で製造された半導体装置の樹脂封止工程
直後の要部斜視図、第３図は第２図のＩＩＩ−ＩＩＩ矢
視要部断面図、第４図は第２図のＩＶ −■矢視断面図
、第５図は第２図のｖ−ｖ矢視断面図、第６図は第５図
に示した部分を半田メッキ処即した状態を示す断面図、
第７図は従来の金型で製造された半導体装置と本発明の
金型で製造された半導体装置の不良発生率を比較表示し
たグラフ、第８図は本発明に関連する樹脂封止型半導体
装置の樹脂封止工程終了直後の状態を示す斜視図、第９
図は第８図のｒＸ−ＩＸ矢視断面図、第１０図は第９図
に示した部分の半田メッキ終了後の状態の断面図、第１
１図は第１０図のごとき状態のアウターリードを有する
半導体装置を回路基板上に実装した時のアウターリード
の状態を示した図、第１２図はアウターリードの上面に
傷もしくは溝が形成されている場合の樹脂封止後の状態
を示す断面図、第１３図は第１２図の状態のアウターリ
ードに対して半田メッキを施した後の状態を示す断面図
、第１４図は第１３図の状態の７ウターリードを有する
半導体装置を回路基板上に実装した時のアウターリード
の状態を示す図である。
１・・・リードフレーム、 １Ａ・・・アウターリー
ド、１Ｂ・・・外枠部、 １Ｃ・・・チップ取付部、
１Ｄ・・・インナーリード部、 １ａ・・・傷もしくは
溝、１ｂ・・・くぼみ、 ２・・・樹脂モールド部、
３・・・漏出樹脂層、 ３ａ・・・樹脂、 ４・・・半
田メッキ層、５・・・回路基板、 ６・・・ろう材、
７・・・金型、７１・・・上型、 ７２・・・下型、
７１ａ、 ７２ａ・・・突条、 ８・・・半導体チッ
プ、 ９・・・ボンディングワイヤ、 Ｃ・・・キャビ
ティ。
特許出願人 株式会社 東 芝
第１ 図
第２図
第３図
第４Ｗ１
第８図
第１０図
１Δ
第１１ ＩＩ
第１２図 第１３図
第１４図FIG. 1 is a sectional view of the main parts of a mold according to an embodiment of the present invention, FIG. 2 is a perspective view of the main parts of a semiconductor device manufactured using the mold of the present invention immediately after the resin sealing process, and FIG. FIG. 2 is a sectional view of the main part taken along arrows III-III in FIG. 2, FIG. 4 is a sectional view taken along IV-■ arrow in FIG. A cross-sectional view showing the part shown in FIG. 5 after being subjected to solder plating,
FIG. 7 is a graph comparing the failure rate of semiconductor devices manufactured with conventional molds and semiconductor devices manufactured with the mold of the present invention, and FIG. 8 is a graph of resin-sealed semiconductors related to the present invention. A perspective view showing the state of the apparatus immediately after the resin sealing process, No. 9
The figure is a sectional view taken along the rX-IX arrow in Fig. 8, Fig. 10 is a sectional view of the part shown in Fig. 9 after solder plating,
Figure 1 shows the state of the outer leads when a semiconductor device having the outer leads as shown in Figure 10 is mounted on a circuit board, and Figure 12 shows the state of the outer leads when scratches or grooves are formed on the top surface of the outer leads. 13 is a sectional view showing the state after solder plating is applied to the outer lead in the state shown in FIG. 12, and FIG. 14 is a sectional view showing the state after resin sealing when FIG. 7 is a diagram showing the state of the outer leads when the semiconductor device having seven outer leads is mounted on a circuit board. 1...Lead frame, 1A...Outer lead, 1B...Outer frame part, 1C...Chip mounting part,
1D... Inner lead part, 1a... Scratch or groove, 1b... Hollow, 2... Resin mold part,
3... Leakage resin layer, 3a... Resin, 4... Solder plating layer, 5... Circuit board, 6... Brazing material,
7...Mold, 71...Upper die, 72...Lower die,
71a, 72a... Projection, 8... Semiconductor chip, 9... Bonding wire, C... Cavity. Patent applicant Toshiba Corporation Figure 1 Figure 2 Figure 3 Figure 4W1 Figure 8 Figure 10 1Δ 11 II Figure 12 Figure 13 Figure 14
Claims (1)
ための樹脂封止用金型において、 該樹脂モールド部を形成するキャビティの外側に近接し
た位置において該樹脂封止型半導体装置のアウターリー
ドの上下両面に食い込み且つ該アウターリードを横切る
方向の低い突条が、上下両金型のリード押え部に形成さ
れていることを特徴とする樹脂封止用金型。[Scope of Claims] 1. In a resin molding mold for molding a resin mold part of a resin molded semiconductor device, the resin mold part is placed close to the outside of a cavity in which the resin mold part is formed. A mold for resin sealing, characterized in that a low protrusion that bites into both upper and lower surfaces of an outer lead of a semiconductor device and extends in a direction across the outer lead is formed on the lead holding part of both the upper and lower molds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP914285A JPS61170038A (en) | 1985-01-23 | 1985-01-23 | Metal mold for resin sealing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP914285A JPS61170038A (en) | 1985-01-23 | 1985-01-23 | Metal mold for resin sealing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61170038A true JPS61170038A (en) | 1986-07-31 |
Family
ID=11712375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP914285A Pending JPS61170038A (en) | 1985-01-23 | 1985-01-23 | Metal mold for resin sealing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61170038A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5252052A (en) * | 1990-12-28 | 1993-10-12 | Sgs-Thomson Microelectronics S.R.L. | Mold for manufacturing plastic integrated circuits incorporating a heat sink |
| CN102756456A (en) * | 2011-04-27 | 2012-10-31 | 无锡华润安盛科技有限公司 | Die for pre-plastic package of a lead frame and encapsulation structure |
-
1985
- 1985-01-23 JP JP914285A patent/JPS61170038A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5252052A (en) * | 1990-12-28 | 1993-10-12 | Sgs-Thomson Microelectronics S.R.L. | Mold for manufacturing plastic integrated circuits incorporating a heat sink |
| CN102756456A (en) * | 2011-04-27 | 2012-10-31 | 无锡华润安盛科技有限公司 | Die for pre-plastic package of a lead frame and encapsulation structure |
| WO2012145879A1 (en) * | 2011-04-27 | 2012-11-01 | 无锡华润安盛科技有限公司 | Mold for pre-plastic-sealing lead frames, process for pre-plastic-sealing and packaging structure |
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