JPS6116987B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When three or more potential levels are required, such as in a dynamic type (dynamic or scanning type) liquid crystal drive circuit, the present invention provides a method for controlling the potential between the highest potential and the lowest potential. This relates to a voltage divider circuit for obtaining

In recent years, in various digital electronic devices such as electronic desktop calculators, electronic circuits have been integrated with so-called complementary circuit configurations formed using both P-type and N-channel MOS transistors, and have also been integrated as display devices. Liquid crystal (abbreviated as Liquid Crystal)
There is a strong demand for lower power consumption and smaller sets by using LC). For example, electronic wristwatches that do not require battery replacement for 1 to 2 years have been commercialized, and even calculators have a usage time of 1,000 years.
A device that does not require battery replacement for about an hour has been developed.

On the other hand, due to the chemical properties of this LC, which has excellent low power consumption, it is important to apply alternating voltage and reduce the integrated voltage component to zero in order to extend its life. By the way, one electrode of a plurality of LC segments is made common (for example, for each display digit), and the other electrode of the segment is made common among different segment groups in which the one electrode is made common, and that one electrode is In a dynamic drive method that selectively scans each group of shared segments in a time-division manner, the response speed of the LC is extremely slow compared to other display devices, so when dynamically driving the LC, three or more voltages are normally required. A drive signal with a level is required. For this reason, this driving signal is obtained from outside the integrated circuit, but this circuit consumes a large amount of power, making it impossible to take full advantage of the excellent low power consumption characteristics of the LC display device.

The present invention has been made in view of the above circumstances, and aims to provide a voltage dividing circuit suitable for reducing power consumption, integrating circuits, and improving display quality.

Embodiments of the present invention will be described below with reference to the drawings. Figure 1a shows an example of wiring the LC display section using the 1/2 duty, 1/2 prebias method, which is the simplest of the LC dynamic drive methods. A case is shown in which one digit consists of 8 segments (7 segments arranged in a Japanese character arrangement and 1 segment for a decimal point). 1st
Figure b is an equivalent circuit diagram of the liquid crystal segment shown in figure a. Figure 2 a and b show display data in bit serial and digit serial format.
FIG. 4 is a diagram of various timing waveforms when processing is performed.

In FIG. 2a, _φ2 is a clock pulse that separates bits when one-digit data is bit serial, and is usually a read pulse. φ ₁ is generated in a pair with pulse φ ₂ and is a data read pulse for flip-flops, shift registers, etc.
T ₁ , T ₂ , T ₄ , and T ₈ are bit pulses that specify bit positions when 1-digit data consists of 4 bits, d ₁
~dn is a digital pulse that specifies the digit position when the calculation cycle is n digits. Figure 2b is LC
The scanning signals H ₁ and H ₂ and the signals used to generate these signals are shown. di is a digital pulse of a certain digit, φ _LA is a pulse indicating one display period, and its period is about 0.2 to 10 msec. Therefore, the pulse di is φ
When corresponding to _LA , di can be set to φ _LA . The pulse di specifying a certain calculation digit is frequency-divided to a predetermined frequency to generate a polarity switching signal for the AC drive and a scan specifying signal for specifying a display section for dynamic display. In this example, 1/
Since the duty is 2, the frequency between these two signals has a 1/2 frequency division relationship, and if E ₁ is the scan designation signal, E ₂ and E ₃ , which are divided by 1/2, become polarity switching signals. . That is, _E2 is for switching the polarity of the drive data signal of the LC segment, and _E3 is for switching the polarity of the scanning signal. Scanning signals H ₁ and H ₂ each require three levels. In other words, when the central part of the calculator (CPU) operates between two potential levels of voltage 0 [V] and -3 [V], and the maximum voltage amplitude of LC drive is 3.0 [V], the signals H ₁ , H The three levels of ₂ are usually 0
[V], -1.5 [V], and -0.3 [V] are used. In this case, the level at both ends of the signals H ₁ and H ₂ is 0.
[V] and -3 [V] scan the part that becomes the display timing, but this position is specified by signal E ₁ , and scanning signal H ₁ is -3.0 [V] (low level) of signal E ₁ , scanning The signal _H2 is specified by the signal _E1 at 0 [V] (high level). Then, the level polarity of the scanning signals H ₁ and H ₂ is switched by the signal E ₃ . During the period when the display timing is not designated, the levels of the signals H ₁ and H ₂ are at an intermediate level of -1.5 [V]. A ₁ is the segment drive data signal, and this signal is the signal
Whether or not liquid crystal display is possible is determined by 0 [V] or -3 [V] corresponding to H ₁ and H ₂ . Figure 3b is Figure 1a
The rightmost segment SE ₁ of the first digit is in a displayable state, and the fifth segment from the right, SE ₅ , is not displayed. Note that the frequency of the data side polarity switching signal _E2 is approximately 20Hz to 1kHz.

FIG. 3 is a block diagram showing the configuration of a display voltage supply section that controls the voltage applied to both ends of each liquid crystal shown in FIG. 1a in accordance with the content to be displayed. In the following explanation, we will correspond to the waveforms in Figures 1 and 2, and will refer to the low level (-3.0V level) as logic "1", or set, and the high level (0V level) as logic "0", or set. Use negative logic to reset. Third
In the figure, 11 is an integrated circuit part, 12 and 13 are terminals for supplying power to this integrated circuit from a DC power supply (3 [V]) 14, 10 is a power switch;
Reference numerals 5 and 16 are input terminals for supplying data input or function commands to the arithmetic circuit (not shown) of the calculator formed in the integrated circuit 11. Means for inputting input to these input terminals 15 and 16 are as follows. There are two methods: one is to use a switch placed between each input terminal and the ground or -3 [V] terminal, and the other is to supply digital pulses or bit pulses through a switch placed at the input terminal. Identification of input signals to input terminals 15 and 16 is performed, for example, by resistors 17 and 18. Note that the resistance is 17,1
8 may be replaced by an equivalent resistance using a FET, or by making the FET conductive at a constant cycle to dynamically set the level when there is no input signal.
Reference numeral 19 is a register that holds display data, where n digits constitute one cycle, and 1 digit is bit "1".
When BCD codes of "2", "4", and "8" operate serially, a pair of clock pulses φ ₁ and φ ₂ generated for each bit are used as shift pulses.
×n pieces are connected in cascade, and the output of the final stage is fed back to the input of the first stage. 20 is the data that is shifted bit by bit in the shift register 19, 1 for each digit.
This is a storage circuit for latching the serial data of "1", "2", "4", and "8" and outputting it as a parallel signal. 21 is a decoder which inputs the four data signals output from this circuit 20 and derives a signal indicating whether each segment is displayed or not displayed for each digit; in this case, the decoder shown in FIG.
Since each digit of the LC display section has eight segments with the same content, there are a total of eight outputs corresponding to these segments SE ₁ to SE ₈ , respectively. It is assumed that a low level signal is derived as this output when display is desired. If this decoder 21 introduces an inverted signal of the signal F that is set only during execution of a series of logical operations and disables the decoder function, changes in data in the shift register 19 during execution of operations will not appear on the LC display section. , all digits can be hidden. 22 is segmented by scanning designation signal _E1 to dynamically display the LC display section.
This circuit scans SE ₁ and SE ₅ , and when the signal E ₁ is at a low level, the output for the segment SE ₅ is switched, and when the signal E ₁ is at a high level, the output for the segment SE ₁ is switched and derived. Although not shown in this case, SE ₂
and E ₆ , SE ₃ and SE ₇ , and SE ₄ and SE ₈ can be considered in the same way. 23 is a lighting state switching circuit for the LC display section, and 24 is a circuit for alternating the voltage applied to both ends of the LC segment. This alternating current (AC driving) circuit takes the exclusive OR of the polarity switching signal E ₂ and the signals derived from the circuits 22 and 23, and when the signal E ₂ is at a low level, the signal to be displayed is set to a high level. When the signal _E2 is at a high level, the signal to be displayed is output as a low level signal. 25 is a shift register that shifts the output from the circuit 24 digit by _digit ;
T ₈ φ ₁ to shift clock pulse, or ₈
This is a cascade-connected circuit of seven shift registers using ₁ , , T ₈ φ ₁ as a clock pulse. Reference numeral 26 consists of eight memory circuits whose input ends are connected to the input ends or output ends of each register of this circuit 25, and each output is connected to the corresponding terminal in FIG. 1a. Each memory circuit of the circuit 26 stores the state outputted from the circuit 25 during the display cycle, for example, the final state of the period α ₁ , α ₂ , β ₁ , β ₂ in FIG. maintain the same level
This is to drive the LC, and the LC from the circuit 26
The drive timing and the operating state of the circuits before circuit 26 or 25 differ by one display cycle period.

27 is a digital pulse di that specifies the digit of calculation.
28 is a circuit for obtaining, for example, a clock pulse φ _LA which is generated once every display cycle. 29 is a frequency dividing circuit that receives a signal having the same period as the display cycle, such as the output of the circuit 27, and outputs a scanning designation signal _E1 ; 30 is a frequency dividing circuit that receives this signal _E1 and outputs a switching signal _E2 ; 31 is a delay circuit which uses signals such as T ₈ φ ₁ and φ _LA as clock pulses to delay this signal E ₂ by one display cycle, and this circuit 31 outputs a polarity switching signal E ₃ . 32 is a circuit that receives the signal E ₁ and also receives E ₃ at an OR circuit 47 to generate a scanning signal H ₁ having three potential levels. The scanning signal H ₂ also has ₁ as a scanning designation signal and can be obtained from a circuit corresponding to the circuit 32. Voltages corresponding to three levels of the scanning signal _H1 are supplied to the circuit 32, among which the highest potential 0 [V] and the lowest potential -3 [V] are applied to the FET 3.
4 ₂ , 33 and 34 ₁ , 35 , and an intermediate potential of -1.5 [V] is given from a voltage divider circuit 36 and output via FETs 37 and 38 . The voltage divider circuit 36 includes a series circuit of resistors R ₁ and R ₂ (R ₁ = R ₂ ) and a FET (switching element) 39 inserted in series between the -3.0 [V] power supply and ground. The connection point between resistors R ₁ and R ₂ is the output terminal. Here, since the FET 39 was placed between the output end and the ground, the FET was configured as a P channel type. This FET3
When the FET 9 is placed between the -3 [V] power supply and the output terminal, it is preferable that the FET is an N-channel type. As a result of the above, conventionally it was normal to obtain a voltage of -1.5 [V] from outside the integrated circuit via a voltage converter, but with this circuit it is possible to obtain a signal with three levels within the integrated circuit. I understand.

40 is a timing circuit for reducing power consumption in the circuit 36, and is set to the set state for a set time after an input signal is introduced from the input terminal 15 or 16, or after a series of logical operations are completed by the input signal. becomes. Methods for this purpose include (a) sequentially dividing a certain pulse using a frequency divider circuit to obtain a pulse with the set time width, or (b) using a memory circuit connected in cascade with shift registers and a full adder or full adder. There are methods of measuring time by adding or subtracting data at regular intervals by combining subtractors and changing the contents of the memory circuit, but in Fig. 3, it is 1/2 as shown in Fig. 4. 1/2048 with 11 stages of frequency divider circuits connected in cascade
A frequency dividing circuit 41 for frequency division was used. The input to this circuit 41 is the switching signal _E2 , which has the longest cycle in the logic operation section of the calculator and the LC drive circuit.
This signal was used for convenience. The period of this E ₂ is 1~
Generally, it is about 50 msec, but here it is set to 20 msec. Moreover, the setting time of the above-mentioned clock circuit 40 is as follows.
It is sufficient that the time is sufficient for a person to read or write down the data displayed on the LC display unit after executing the logical operation, and is set to about 20 seconds, for example. 42
is a circuit that generates a signal that instructs the clock circuit 41 to start timing, and when an input signal is introduced from the input terminal 15 or 16, it may generate an output in response to the input signal, but it may also generate an output in response to the input signal. It may also be a circuit that outputs a constant pulse later. That is, the circuit 42 sets all stages of the frequency divider 41 of 1/2048 frequency division. The signal E ₂ is supplied to the input of the circuit 41 via the input prohibition circuit 43 when the output of the circuit 41 is in the set state. This signal E ₂ is 20msec
Since the output timing of the circuit 42 is unstable within one cycle of the signal _E2 , the counting circuit 41
The output of E2 will reset within 1024 periods of signal _E2 after being set by the output of circuit 42, as shown in FIG. That is, the input terminal 15,
When the input signal is input to 16, the output of circuit 41 is
Set for 20.46-20.48 seconds. Then, unless a new input is given to the input terminals 15, 16 again, the inhibition circuit 43 prohibits the frequency division input, so that the reset state is maintained until a new input signal is given to the terminals 15, 16. 44 is a clock circuit 41
This is a circuit that delays the set state of _T8 for one display period.
It consists of a shift register using φ ₁ and φ _LA as clock pulses.

The output of the clock circuit 40 is inverted by an inverter 45, ORed with the output of the switching circuit 22, and introduced into the exclusive OR circuit 24. Therefore, when the output of the clock circuit 40 is reset, the input of the circuit 24 becomes a display state, that is, a low level, regardless of the output of the decoder 21 or the data content in the shift register 19, so all of the LC drive signals _A1 to _A8 are clocked. circuit 4
When 0 is reset, it becomes the same as the polarity switching signal _E3 within the 1 display period, that is, within 5 ms.

The output of the delay circuit 44 is supplied to the switching element 39 of the voltage dividing circuit 36, and when the element 39 is turned on, a -1.5 [V] signal is derived at the output section of the circuit 36. The on period of this element 39 is
This coincides with the period in which the segment drive data signals are respectively derived from the storage circuit 26, and the results of the arithmetic processing are output to the LC display section during this period. On the other hand, when the output of the delay circuit 44 is reset, the switching element 39 is turned off, so the dividing circuit 36 is cut off and its output becomes -3 [V] via the resistor _R1 . At this time, the designated signal E ₁ for the scanning signal H ₁ is the inverted output of the circuit 44 and the OR circuit 1.
22, the scanning signal H ₁
The waveform is output as an inverted pulse of signal _E3 . Therefore, when the clock circuit 40 is reset, the scanning signal _H1 is an inverted signal of the signal _E3 , and the scanning signals _A1 to _A8 are the same as the signal _E3 , and all the signals driven by this signal _A1 to _A8 are The LC segment is in the display state. The remaining LC segments can be considered similarly. Of course, at this time, since the polarity of the voltage applied to each LC segment is alternating, no matter how long the reset time of the clock circuit is, there will be no problem with the LC life.

The values of resistors R ₁ and R ₂ need to be set to large values in order to minimize the current consumption when FET 39 is on, but considering the parasitic capacitance of several 10 to 1000 PF that the LC display device has, 10~200KΩ
It is set to a certain degree. By operating the voltage dividing circuit 36 only when it is desired to display an image on the LC display device in this manner, the power consumption in this portion can be greatly reduced.
In addition, since the alternating voltage can be properly applied to all segments during periods other than the LC display period, there is no problem with the LC lifespan. Furthermore, since the voltage divider circuit 36 is formed within the integrated circuit 11, it is also possible to reduce the number of individual components used outside the circuit.
In addition, this circuit configuration reduces power consumption in the circuit due to forgetting to turn off the power switch 10 by using the voltage dividing circuit 36.
It is possible to limit the power consumption to other than the power consumption, and also to stop the operation of the equipment except when necessary, and to perform the same effect as turning off the power switch.
It is effective for the purpose of omitting the above and improving the reliability of devices such as calculators.

Also, as mentioned above, segments SE ₂ and SE ₆ ,
If the segment drive signals of GE ₃ and SE ₇ and SE ₄ and SE ₈ are configured in the same manner as for segments SE ₁ and SE ₅ , all segments of the display section in FIG. It can be left visible. On the other hand, the segment display control circuit 23
As shown in FIG. 5a, if the clock circuit 40 is replaced with a circuit that transmits the output of the circuit 22 to the circuit 24 only when it is set, and prohibits signal transmission at other times,
After resetting the clock circuit 40, all LCDs display the maximum -
Only a voltage of 1.5 [V] is applied, and therefore all liquid crystal segments can be put into a non-display state. Furthermore, as shown in FIG. 5b, when the circuit 40 is reset, the signal transmission from the circuit 22 to the circuit 24 is prohibited, and if, for example, the signal di is transmitted to the circuit 24 only in a specific segment, then after the circuit 40 is reset, the signal di can be transmitted to the circuit 24. Only segments, for example segments SE ₁ and SE ₅ , can be made visible. It is convenient to display all segments or only a specific segment after resetting the clock circuit 40 as described above, since it can be identified that power is being supplied to a device such as a calculator.

In addition, if you want to stop the operation of only the LC display device and make all segments invisible, use circuit 3 in Figure 3.
The output of the circuit 31 supplied to the delay circuit 44
By setting in the reset state of the output of
The alternation of the LC drive signals is stopped and fixed to, for example, the ground level, and the segment signals A ₁ to A ₈ , B ₁ to
B ₈ , C ₁ -C ₈ , D ₁ -D ₈ can be obtained by resetting the memory circuit 26 in the reset state of the delay circuit 44, or by resetting the output of the memory circuit 25 in the reset state of the circuit 44. is applied to the circuit 26 to obtain each segment signal, these signals also stop alternating and become, for example, ground level, and all LC
Segments can be hidden. Further, as a method for this purpose, as shown in FIG. 6, if the output of the display control circuit 24 is inhibited by an AND circuit 51 during the reset period of the circuit 40, the segment drive signal can be easily fixed at the ground level. Furthermore, the alternation of the scanning signals H ₁ and H ₂ can be stopped by the OR circuit 52, and can be fixed at the ground level.

In addition, if a certain period of time elapses after a keystroke is made on a calculator, etc., the device will stop sequential arithmetic operations in part or all of the device until a new keystroke is made, or cut off the power supply to reduce power consumption. If you do so, stop alternating the LC drive signals and
Making the potential difference between both ends of the segment zero is
This is advantageous in terms of LC lifespan and low power consumption. In this case, the time measurement circuit 40 may be used as a time measurement circuit for obtaining a certain period of time after the key input. Then, in order to reset the clock circuit and stop the sequential operation in the circuit of FIG. 3 or 6, the shift clock pulse may be fixed at one level or the power supply to the device may be stopped. However, if the memory element to which this shift clock pulse is supplied is of a dynamic type, a reset signal is sent from the clock circuit 40 to the switch element 54 in order to fix the potential of the memory element 53, as shown in FIG. 7a or b. supplying information, circuit 19,
When a large number _of the _above -mentioned storage elements are connected as shown in _FIG . It may be given as a shift clock pulse. on the other hand,
If the power supply to the equipment is to be stopped by resetting the clock circuit 40, the power supply to the circuits 26, 32, 32', etc. may be stopped.

In the above explanation of FIG. 3, we have used an example of displaying data after the execution of calculations on a calculator, etc. However, if you simply want to display the data of the shift register 19 without executing calculations, you can use the input terminal An input terminal similar to 15 or 16 may be provided to set the clock circuit 40 via the circuit 42 with a future input signal, or alternatively, as shown in FIG.
A specific timing pulse, for example di, may be applied from the input signal, and the AND circuit 46 may inhibit only the timing of di among the signals introduced into the arithmetic circuit.

FIG. 8 shows an application example of the voltage divider circuit 36 in which switch elements 61 and 62 are connected in series with resistors R ₁ and R ₂ . The output of the circuit 44 is applied to the gate of the element 62, and its inverted output is applied to the element 61. Therefore, only when the circuit 44 is set, the elements 61 and 62 are turned on and send out an output of -1.5 [V], and the circuit 44 is turned on. At the time of reset, the -1.5 [V] output becomes undefined. However, at the time of the above reset, the output potential of the circuit 44 is not used in the circuit 32, so there is no problem.

FIG. 9 is an application example of FIG. 8, in which an AND circuit 63 calculates the logic between the output of the circuit 44 and a clock pulse of a constant period, for example, _T1 . Therefore, a -1.5 [V] output is sent out only when these logics are established. Even if the pulse T ₁ is not established and the elements 61 and 62 are turned off, the LC connected through the circuit 32 is capacitive and its leak resistance is 1 to 200 MΩ or more, so the output is not output when T ₁ is established. -1.5 [V] of the output of the circuit 32 is dynamically held in the output capacitor, LC capacitor, of this circuit. With this circuit, power consumption is further reduced than in the case of FIG.

FIG. 10 shows an embodiment of the present invention, in which switch elements 64 and 65 and resistors R ₃ and R ₄ are added to FIG. 8. That is, the elements 61 and 62 are turned on only when the circuit 44 is set, and the elements 64 and 65 are turned on for a certain period of time at the beginning of the LC display cycle (for example, when the pulse
Turns on only when di or φ _LA or di・T ₁・circuit 29 output is established). Also, the values of resistors R ₃ and R ₄ are
This value is set as large as possible to replenish the leakage component of the LC. In this way, low power consumption is possible due to the high resistances R ₃ and R ₄ , and the voltage divider circuit becomes low impedance for a certain period of time at the start of each display period via the low resistances R ₁ and R ₂ . Therefore, each display level is stabilized in a short time, the response speed is excellent, and crosstalk (display leakage) is eliminated. FIG. 11 shows a modification of the above-mentioned FIG.
This is an example where power consumption in R ₃ and R ₄ is further reduced.

FIG. 12 shows a modified example of a voltage divider circuit in which the voltage divider circuit is not controlled by the output of the delay circuit 44 of the clock circuit 40, but is controlled by a bit pulse generated at a constant period, for example, _T1 , and the circuit is controlled by the clock circuit 40. It is designed so that it can also be used in equipment that does not require this function. That is, a switching element 71 consisting of a resistor _R1 and an N-channel FET is directly connected between the -3.0 [V] power supply and the output terminal O, and the switching element 71 consisting of a resistor R1 and an N-channel FET is connected directly between the ground and the output terminal O.
In between, a resistor _R2 and a switching element 72 consisting of a P-channel FET are connected in series, and the gate of element 72 is supplied with a bit signal _T1 , and the gate of element 71 is supplied with an inverted signal of signal _T1 . Resistors R ₁ and R ₂ have approximately the same resistance value, and the on-resistance of elements 71 and 72 is
It is one order of magnitude smaller than R ₁ and R ₂ . If the pulse _T1 is now at a low level, the elements 71 and 72 are turned on, and an output of -1.5 [V] is obtained at the output terminal O. Next, when the pulse T ₁ becomes high level, the elements 71 and 72 are turned off, but the output potential of -1.5 [V] is held in the output capacitor 73. Therefore, since the LC of the display section is capacitive, when T ₁ is at a high level, the scanning pulse H ₁
Alternatively, if the switch of H ₂ to -1.5 [V] is completed, the level of -1.5 [V] required for H ₁ and H ₂ can be obtained satisfactorily.

FIG. 13 shows a modification of FIG. 12. In this case, pulse T ₁ in FIG. 12 is replaced with pulse φ _LA . This pulse width may be a period sufficient to switch the scanning pulses H ₁ and H ₂ to -1.5 [V]. And between the -3.0 [V] power supply and the output terminal O, there is a leak replenishing resistor _R3 between the ground power supply and the output terminal O.
A leak replenishment resistor _R4 is connected between them. These resistors have the relationship R ₃ =R ₄ and are selected to have extremely large values compared to the resistors R ₁ and R ₂ . FIG. 14 is a modification of FIG. 13, in which a resistor R ₃ is arranged in parallel with the switching element 71 and a resistor R ₄ is arranged in parallel with the switching element 72. FIG. 15 is a modification of FIG. 13, in which a switching element 75 is inserted in series with the resistor R ₃ and a switching element 76 is inserted in series with the resistor R ₄ , and a pulse T ₁ is applied to the gates of these elements 75 and 76. , which aims to further reduce power consumption.

Figure 16 uses the voltage divider circuit of Figure 13,
An example of a circuit that supplies LC scanning signals H ₁ and H ₂ having three levels to the common terminal of an LC display device is shown.
The H ₁ generation circuit 32 includes P channel type FETs 33, 3
4 Apply 0 [V] at the timing when ₂ turns on, FET
-1.5 [V] at the timing when 37 and 38 turn on
-3.0 [V] is supplied to the common terminal of the LC display device at the timing when FETs 34 ₁ and 35 are turned on. The configuration of the H ₂ generating circuit 32' corresponds to that of the H ₁ generating circuit 32. However, _H2 generation circuit 3
Since an inverter 74 is provided at the input section to 2', when the H ₁ generating circuit 32 is outputting -1.5 [V], the H ₂ generating circuit 32' outputs 0 [V] or -3.0 [V]. V] is output. Above scanning pulse
The waveforms of H ₁ and H ₂ are similar to those shown in FIG.

In Fig. 17, an output of -1.0 [V] is obtained by setting R ₁ /R ₂ = 2 in Fig. 12, and R' ₁ /R' ₂ = 1/2.
As a result, an output of -2.0 [V] is obtained, and FET75, 76
By switching, either -1.0 [V] or -2.0 [V] output can be obtained.

The above FIGS. 8, 9, 12, and 17 are
This is not an example of the present invention and does not fall within the technical scope of the claims of the present invention.

Note that in each of the above embodiments, a case has been described in which the voltage dividing circuit is used in an LC display device, but the application is not limited to this only. Furthermore, the values of the resistors R ₁ and R ₂ are not limited to those in the embodiment, and by appropriately setting the ratio of these resistance values, the present invention can be applied in various ways, such as obtaining a voltage different from that in the embodiment. .

As explained above, according to the present invention, the switching means is inserted in series with the resistor series circuit provided between the power supply terminals, and the switching means can be turned on and off, thereby reducing power consumption. Furthermore, since each of the resistors and switching means can be incorporated into an integrated circuit together with other circuits, the device can be easily miniaturized and integrated into an integrated circuit, and a voltage dividing circuit with improved display quality can be provided. It is.

[Brief explanation of the drawing]

Fig. 1a is a circuit diagram of the LC display section, Fig. 1b is an equivalent circuit diagram of the same part, Fig. 2a and b are timing signal waveform diagrams, Fig. 3 is a circuit diagram of the LC display voltage supply section, and Fig. 3 is a circuit diagram of the LC display voltage supply section. Figure 4 is a timing signal waveform diagram, Figures 5 to 7 are circuit diagrams showing application examples of the configuration in Figure 3,
8 and 9 are voltage dividing circuit diagrams other than the present invention,
10 and 11 are circuit diagrams of embodiments of the present invention,
FIG. 12 is a voltage division circuit diagram other than the present invention, and FIG.
16 through 16 are circuit diagrams of other embodiments of the present invention, and FIG. 17 is a voltage division circuit diagram other than the present invention. R ₁ , R ₂ , R ₃ , R ₄ ... Resistor, 36 ... Voltage divider circuit, 39, 71, 72 ... Switching element,
40... Timing circuit, 44... Delay circuit, T ₁ , φ _L
A ...Clock signal.

Claims (1)

[Claims] 1. A first resistor inserted in a conductive path between one voltage supply end and the output end, and a first resistor inserted in a conductive path between the other voltage supply end and the output end. a second resistor inserted into the first conductive path and turned on periodically; and a first switching means inserted into the second conductive path and turned on synchronously with the first switching means. a second switching means for turning on the first switching means;
a series circuit of the resistor and the first switching means, or a third resistor connected in parallel to the first switching means and having a higher resistance value than the first and second resistors; a fourth resistor connected in parallel to the series circuit of the switching means or the second switching means and having a higher resistance value than the first and second resistors, and a divided potential between the first to fourth resistors; A voltage dividing circuit characterized in that the voltage is applied to a plurality of display drive circuits. 2 In the above claim 1, the first and second
1. A voltage dividing circuit characterized in that a clock circuit is connected to the switching means, and each of the switching means is controlled to be turned on and off over time based on the clock signal. 3. The voltage divider circuit according to claim 1, characterized in that a third switching means is inserted in series with the third resistor, and a fourth switching means is inserted in series with the fourth resistor.