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JPS61168227A - Substrate for exposure of minute pattern and apparatus for exposing minute pattern - Google Patents

Substrate for exposure of minute pattern and apparatus for exposing minute pattern

Info

Publication number
JPS61168227A
JPS61168227A JP60009485A JP948585A JPS61168227A JP S61168227 A JPS61168227 A JP S61168227A JP 60009485 A JP60009485 A JP 60009485A JP 948585 A JP948585 A JP 948585A JP S61168227 A JPS61168227 A JP S61168227A
Authority
JP
Japan
Prior art keywords
reticle
substrate
fine pattern
patterns
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60009485A
Other languages
Japanese (ja)
Inventor
Masayuki Nakajima
真之 中島
Teruhiko Yamazaki
山崎 照彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60009485A priority Critical patent/JPS61168227A/en
Publication of JPS61168227A publication Critical patent/JPS61168227A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To enable the comparative inspection of patterns of any chip size, by drawing a plurality of minute patterns in the same form on the main body of a substrate, and by providing alignment marks for each minute pattern. CONSTITUTION:A reticle 11 is formed to be twice as large as an area wherein exposure can be made, and minute patterns 2c in the same form are drawn in two places on this reticle, while reticle alignment marks 3 are prepared also in two places. Moreover, a substrate driving device having a reticle edge guide 12 which can be driven vertically is provided near a platen of a reduced projection exposure device so as to select a desired pattern 2c with ease and without fail. Even when any defect such as the presence of an alien substance is detected on either one of chips by the comparative inspection of the patterns 2c, the other chip can be mounted on the platen without elimination of said defect, and thus a pattern free from any defect can be transferred efficiently on a wafer 10.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、写真製版技術により半導体集積回路装置等
を製造する場合に使用される光透過性基板(以下レティ
クルと記す)及び該レティクルを用いた微細バクーン露
光装置の改良に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a light-transmitting substrate (hereinafter referred to as a reticle) used when manufacturing semiconductor integrated circuit devices, etc. by photolithography, and a method using the reticle. This paper relates to the improvement of the fine Bakun exposure device.

〔従来の技術〕[Conventional technology]

従来、この種のレティクルとしては第2図(a)。 A conventional reticle of this type is shown in FIG. 2(a).

第3図ia)に示すものがあった。There was one shown in Figure 3 ia).

図において、1はレティクル、2a、2bはこのレティ
クル1上に描画された微細パターン、3は上記レティク
ル1と縮小投影露光装置とをアライメント(位置合せ)
するためのレティクル1上に設けられたアライメントマ
ークである。
In the figure, 1 is a reticle, 2a and 2b are fine patterns drawn on this reticle 1, and 3 is an alignment between the reticle 1 and a reduction projection exposure device.
This is an alignment mark provided on the reticle 1 for the purpose of

また上記レティクル1を使用して微細パターン2b、2
cを半導体シリコンウェハ上に転写するための縮小投影
露光装置としては、第2図(C)、第3図(C)に示す
ものがあった。図において1〜3は前述の通りであり、
6a、5bはアライメントマーク検出手段であるフォト
カプラ、7は上記レティクル1を載置保持するためのプ
ラテン、8はこのプラテン7に設けられ、上記アライメ
ントマーク3とでレティクル1の位置合せをするための
フィデューシャルマーク、9は縮小レンズ、10は上記
微細パターン2a、2bが転写される半導体シリコンウ
ェハである。
Also, using the reticle 1, fine patterns 2b, 2
There are reduction projection exposure apparatuses for transferring the image 3.c on a semiconductor silicon wafer as shown in FIG. 2(C) and FIG. 3(C). In the figure, 1 to 3 are as described above,
6a and 5b are photocouplers serving as alignment mark detection means; 7 is a platen for mounting and holding the reticle 1; and 8 is provided on the platen 7 for aligning the reticle 1 with the alignment mark 3. , 9 is a reduction lens, and 10 is a semiconductor silicon wafer onto which the fine patterns 2a and 2b are transferred.

次に、上記従来の縮小投影露光装置によりレティクル1
上の微細パターン2a、2bをウェハ10上に転写する
場合について説明する。
Next, the reticle 1 is
The case where the above fine patterns 2a and 2b are transferred onto the wafer 10 will be described.

まず上記レティクル1を露光装置のプラテン7上の、該
レティクル1を固定するべき個所にマウントし、該露光
装置のアライメントマーク検出器(フォトカプラ)6a
+  5bにより、プラテン7上に形成されているフィ
デューシャルマーク8と、レティクル1上のアライメン
トマーク3とを位置合せし、この状態で上記レティクル
1をプラテン7上に固定すると、これにより、レティク
ル1がアライメントされ、しかる後ウェハ10上に上記
微細パターン2a又は2bを転写する。
First, the reticle 1 is mounted on the platen 7 of the exposure device at a location where the reticle 1 is to be fixed, and the alignment mark detector (photocoupler) 6a of the exposure device is mounted.
+ 5b, align the fiducial mark 8 formed on the platen 7 and the alignment mark 3 on the reticle 1, and fix the reticle 1 on the platen 7 in this state. 1 is aligned, and then the fine pattern 2a or 2b is transferred onto the wafer 10.

ところで、従来用いられている上記微細パターン2a、
2bの欠陥検査法としては、 ■ レティクル1上に繰り返し形成された微細パターン
2aを相互に比較する比較検査方式(第2図(t+1参
照) ■ レティクル1上のパターン2bと設計データ5とを
比較するデータ参照検査方式(第3図中)参照) がある。ここで検査状態を示す第2図山)、第3図(b
lにおいて、4は検査装置の対物顕微鏡を示す。
By the way, the conventionally used fine pattern 2a,
The defect inspection method for 2b is as follows: ■ A comparative inspection method in which the fine patterns 2a repeatedly formed on the reticle 1 are compared with each other (see Figure 2 (t+1)) ■ The pattern 2b on the reticle 1 is compared with the design data 5. There is a data reference inspection method (see Figure 3). Here, the inspection status is shown in Figure 2 (mountain) and Figure 3 (b).
1, 4 indicates an objective microscope of the inspection device.

上記2つの検査方式の使い分けは、縮小投影露光装置に
よる露光可能な領域、つまり有効エリア(一般に用いら
れている縮小投影露光装置では15m m 口または2
0mmφ)内に複数の微細パターンが形成し得るか否か
によって決定づけられる。
The use of the above two inspection methods is based on the area that can be exposed by the reduction projection exposure device, that is, the effective area (15 mm or 2 mm in the commonly used reduction projection exposure device).
It is determined by whether a plurality of fine patterns can be formed within a diameter of 0 mmφ.

即ち、第2図(a)の様に微細パターン2aが有効エリ
ア内に2つ納まる大きさ、例えば7.5X 1.5 m
mのチップの場合は、上記第2図fclに示す様な露光
装置が用いられるとともに、このレティクル1上の微細
パターン2aの欠陥検査は第2図山)に示すような比較
検査方式により行なわれる。
That is, as shown in FIG. 2(a), the size is such that two fine patterns 2a can fit within the effective area, for example, 7.5 x 1.5 m.
In the case of the chip No. m, an exposure device as shown in FIG. .

しかし第3図(alに示す様に、微細パターン2bが有
効エリア内に2つは納まらない大きさ、例えば8X15
mmの場合は、第2図山)の比較検査方式は不可能であ
り、第3図(b)のデータ参照検査方式を採用せざるを
得ない。
However, as shown in FIG.
In the case of mm, the comparative inspection method shown in Fig. 2(b) is not possible, and the data reference inspection method shown in Fig. 3(b) must be adopted.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第3図+alに示すような、微細パターン2bが有効エ
リア内に1つしか入らない大きさのレティクル1におい
て欠陥検査を行なう場合、上述のとおりデータ参照検査
方式を採用せざるを得す、設計データとの比較を必要と
することから、検査時間を長く要し、また設計データを
保存しておく必要があることから、データメモリの容量
を多く必要とする欠点があった。
When performing defect inspection on a reticle 1 whose size allows only one fine pattern 2b to fit within the effective area, as shown in FIG. Since it requires comparison with data, it requires a long inspection time, and because it is necessary to store design data, it has the drawback of requiring a large capacity of data memory.

一方、微細パターンが大きい場合にも比較検査ができる
ように有効エリアを大きくすることも考えられるが、縮
小投影露光装置は解像力の向上に伴って転写可能な有効
エリアは小さくなる方向に進む傾向にあることから、上
記大きくすることは望ましくない。
On the other hand, it may be possible to increase the effective area so that comparative inspection can be performed even when the fine pattern is large, but as the resolution of reduction projection exposure equipment improves, the effective area that can be transferred tends to become smaller. For some reasons, it is not desirable to increase the size as described above.

本発明は、かかる従来の問題点に鑑みてなされたもので
、微細パターンが有効エリア内に1つしか描画できない
大きさの場合であっても、上記比較検査法により微細パ
ターンの欠陥検査を行なうことができ、検査時間の短縮
化及び検査用設計データの削減をすることのできる微細
パターン露光用基板、及び露光可能領域は従来のものと
同じで、かつ上記露光用基板を用いて所望の微細パター
ンの転写ができる微細パターン露光装置を提供すること
を目的としている。
The present invention has been made in view of such conventional problems, and even if the size of the fine pattern is such that only one fine pattern can be drawn within the effective area, defect inspection of the fine pattern is performed using the comparative inspection method described above. A fine pattern exposure substrate that can shorten inspection time and reduce inspection design data, and the exposed area is the same as conventional ones, and the above exposure substrate can be used to create the desired fine pattern. The object of the present invention is to provide a fine pattern exposure apparatus that can transfer patterns.

〔問題点を解決するための手段〕 本発明は、微細パターン露光用基板において、光透過性
の基板本体に複数の同一形状の微細パターンと、各微細
パターンの位置合せのためのアライメントマークとを描
いたものであり、また微細パターン露光装置において、
所望の微細パターンを露光可能領域内に位置せしめるた
めの基板駆動手段を設けたものである。
[Means for Solving the Problems] The present invention provides a fine pattern exposure substrate in which a plurality of fine patterns having the same shape and an alignment mark for positioning each fine pattern are provided on a light-transmitting substrate body. In addition, in fine pattern exposure equipment,
A substrate driving means is provided for positioning a desired fine pattern within the exposure area.

〔作用〕[Effect]

本発明の微細パターン露光用基板では、微細パターンの
欠陥検査を行なう場合は微細パターンが露光可能領域内
に1つしか入らない大きさであっても比較検査法を用い
ることができ、かつ、従来と同じ大きさの露光可能領域
内に所望の微細パターンを位置させることができる。
With the fine pattern exposure substrate of the present invention, when inspecting fine patterns for defects, a comparative inspection method can be used even if the fine pattern is large enough to fit only one within the exposure area, and A desired fine pattern can be positioned within an exposureable area of the same size.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図fal〜(C1は本発明の一実施例を説明するた
めのもので、その露光用基板を示す第1図(alにおい
て、従来用いられていたレティクルのサイズは露光可能
領域(有効エリア)に対応したサイズ、例えば5II 
x 5″であったのに対し、本実施例のレティクル11
は上記露光可能領域の2倍の大きさに対応する、例えば
5“×10“あるいはそれ以上の大きさを有するもので
あり、またこの基板本体には同一形状の微細パターン2
Cが2カ所に描画されている。またレティクルアライメ
ントマーク3も同様に各微細パターン2Cの両脇に2組
作成されている。
Figure 1 fal ~ (C1 is for explaining one embodiment of the present invention, and in Figure 1 (al) showing the exposure substrate, the size of the conventionally used reticle is shown in the exposure possible area (effective area). ), for example, 5II
x 5″, whereas the reticle 11 of this example
corresponds to twice the size of the above-mentioned exposed area, for example, 5" x 10" or more, and this substrate body has a fine pattern 2 of the same shape.
C is drawn in two places. Similarly, two sets of reticle alignment marks 3 are formed on both sides of each fine pattern 2C.

第3図(blに示す様な有効エリア内に1つしか描画で
きない大きさの微細パターンを描画したレティクルの場
合は、従来、設計データとしか比較できなかったが、本
実施例のレティクル11では第1図(b)に示す様に、
レティクル11を大型化し、これに2つの微細パターン
2Cを繰り返して描画したので、この2つの微細パター
ン2Cを比較検査することができ、その結果検査時間を
短縮化できるとともに、検査用設計データを不要にでき
る。
In the case of a reticle with a fine pattern drawn in a size that allows only one drawing within the effective area, as shown in FIG. As shown in Figure 1(b),
Since the reticle 11 is enlarged and two fine patterns 2C are repeatedly drawn on it, it is possible to compare and inspect these two fine patterns 2C.As a result, inspection time can be shortened and design data for inspection is not required. Can be done.

今後、パターンの微細化により、より高集積化されたメ
モリ等の集積回路が必要とされるにつれ、チップサイズ
は増大する方向に進む。一方、縮小投影露光装置は解像
力の向上に伴って転写可能な有効エリアは小さくなる方
向に進む傾向にあるから本実施例レティクルの必要性は
増大すると予想される。
In the future, as patterns become finer and more highly integrated integrated circuits such as memories are required, chip sizes will continue to increase. On the other hand, as the resolution of reduction projection exposure apparatuses improves, the effective transferable area tends to become smaller, so it is expected that the need for the reticle of this embodiment will increase.

次に本発明の一実施例による微細パターン露光装置を示
す第1図[C1において、12はプラテン7の近傍に設
けられた基板駆動装置のレティクルエツジガイド(位置
決めストッパー)であり、この基板駆動装置は、上記2
つのmsパターン2Cのうち所望のパターンが有効エリ
ア内に位置するよう基板11を移動させるためのもので
ある。
Next, in FIG. 1 [C1] showing a fine pattern exposure apparatus according to an embodiment of the present invention, 12 is a reticle edge guide (positioning stopper) of a substrate driving device provided near the platen 7; is the above 2
This is for moving the substrate 11 so that a desired pattern among the two ms patterns 2C is located within the effective area.

本実施例装置により、例えば図示左側の微細パターン2
Cをウェハ10上に転写するには、まずこの左側微細パ
ターン2Cを有効エリア内に位置合せするわけであるが
、そのために、まず、左側。
With the device of this embodiment, for example, the fine pattern 2 on the left side of the figure
In order to transfer C onto the wafer 10, the left fine pattern 2C must first be aligned within the effective area.

及び中央のレティクルエツジガイド12を下降させ、こ
の状態でレティクル11を右側のレティクルエツジガイ
ド12に当接するまで移動させる。
Then, the center reticle edge guide 12 is lowered, and in this state, the reticle 11 is moved until it comes into contact with the right reticle edge guide 12.

そしてさらにこの左側の微細パターン2C用アライメン
トマーク3をプラテン7上のフィデューシャル8上に位
置させれば、これにより上記左側微細パターン2cが位
置合せされ、この状態でこの微細パターン2Cをウェハ
10上に転写することとなる。
Further, if the alignment mark 3 for the left fine pattern 2C is positioned on the fiducial 8 on the platen 7, the left fine pattern 2c is aligned, and in this state, the fine pattern 2C is placed on the wafer 10. It will be transferred onto the top.

上記第1図(alに示す様な大型のレティクル11の場
合、第2図(C)、第3図(01に示す様な従来タイプ
の縮小投影露光装置では従来タイプの5#×5“のレテ
ィクルしかマウントできないことから転写できないこと
となるが、本実施例装置では、従来の縮小投影露光装置
のプラテン近傍に上下駆動可能なレティクルエツジガイ
ド12を有する基板駆動装置を設けたので、所望の微細
パターン2cを容易確実に選択できる。そのため第1図
(blに示す様なパターン2Cの比較検査をしていずれ
か一方のチップ上に異物等の欠陥を検出した場合でも、
この欠陥を除去することなく、もう一方のチップをプラ
テン上にマウントすることができ、これにより無欠陥の
パターンをウェハ上に効率よく転写することができる。
In the case of a large-sized reticle 11 as shown in FIG. 1 (al), a conventional type reduction projection exposure apparatus as shown in FIG. Since only the reticle can be mounted, transfer is not possible, but in this example apparatus, a substrate drive device having a reticle edge guide 12 that can be moved vertically is installed near the platen of a conventional reduction projection exposure device, so that the desired fineness can be achieved. Pattern 2c can be selected easily and reliably. Therefore, even if a defect such as a foreign object is detected on one of the chips by a comparative inspection of pattern 2C as shown in FIG.
The other chip can be mounted on the platen without removing this defect, thereby efficiently transferring a defect-free pattern onto the wafer.

なお、上記実施例では、1枚のレティクル上に2つのチ
ップを設けた例を示したが、3チップ以上を設けてもよ
い。
In the above embodiment, two chips are provided on one reticle, but three or more chips may be provided.

〔発明の効果〕〔Effect of the invention〕

以上の様に、この発明によれば、基板本体上に、複数の
同一形状の微細パターンを描くとともに、各微細パター
ン用のアライメントマークを設けたので、いかなるチッ
プサイズのパターンでも比較検査が可能となり、検査時
間を短縮できるとともに、従来記憶しておく必要のあっ
た膨大な容量の検査用設計データを不要にできる効果が
あり、また所望の微細パターンを露光可能領域に位置さ
せるための基板駆動手段を設けたので、露光可能領域に
1つしか描画できない大きさの微細パターンを複数描画
した露光用基板を用いて所望の微細パターンを転写でき
る効果がある。
As described above, according to the present invention, a plurality of fine patterns of the same shape are drawn on the substrate body, and alignment marks are provided for each fine pattern, making it possible to perform comparative inspection of patterns of any chip size. This has the effect of shortening the inspection time and eliminating the need for the huge amount of inspection design data that was conventionally required to be stored.Also, it is a substrate driving means for positioning the desired fine pattern in the exposure area. Since this is provided, there is an effect that a desired fine pattern can be transferred using an exposure substrate on which a plurality of fine patterns of a size that only one can be drawn in an exposure possible area are drawn.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の一実施例による微細パターン露
光用基板の平面図、第1図fb)はその検査方法を説明
するための構成図、第1図(C)は本発明の一実施例に
よる微細パターン露光装置の構成図、第2図fa)及び
第3図fa)は従来の微細パターン露光用基板の平面図
、第2図(ト))及び第3図中)はその検査方法を説明
するための構成図、第2図fQ)及び第3図fclは従
来の微細パターン露光装置の構成図である。 2c・・・微細パターン、3・・・アライメントマーク
、6a、6b、8・・・検出手段、12・・・基板駆動
手段(レティクルエツジガイド)。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1(a) is a plan view of a fine pattern exposure substrate according to an embodiment of the present invention, FIG. 1(fb) is a configuration diagram for explaining the inspection method, and FIG. A configuration diagram of a fine pattern exposure apparatus according to an embodiment, FIGS. 2(a) and 3(a) are plan views of a conventional substrate for fine pattern exposure, and FIGS. FIG. 2 fQ) and FIG. 3 fcl, which are block diagrams for explaining the inspection method, are block diagrams of a conventional fine pattern exposure apparatus. 2c... Fine pattern, 3... Alignment mark, 6a, 6b, 8... Detection means, 12... Substrate drive means (reticle edge guide). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)光透過性の基板本体の一主面に、複数の同一形状
の微細パターンと、該各微細パターンとこれをウェハ上
に転写するための露光装置とを位置合せするためのアラ
イメントマークとを描いてなることを特徴とする微細パ
ターン露光用基板。(2)光透過性の基板本体の一主面
に、複数の同一形状の微細パターンと、該各微細パター
ンの位置合せのためのアライメントマークとを描いてな
る基板を用いて上記いずれかの微細パターンをウェハ上
に転写する微細パターン露光装置であって、上記アライ
メントマークを検出するための検出手段と、上記所望の
微細パターンが露光可能領域内に位置するよう該所望の
微細パターン用のアライメントマークが検出されるまで
上記基板を移動させる基板駆動手段とを備えたことを特
徴とする微細パターン露光装置。
(1) A plurality of fine patterns having the same shape, and an alignment mark for aligning each fine pattern with an exposure device for transferring the fine patterns onto a wafer, on one main surface of a light-transmitting substrate body. A substrate for fine pattern exposure, which is characterized by being drawn with. (2) Any of the above-mentioned fine patterns can be produced by using a substrate on which a plurality of fine patterns of the same shape and alignment marks for positioning the fine patterns are drawn on one main surface of a light-transmitting substrate body. A fine pattern exposure apparatus for transferring a pattern onto a wafer, the apparatus comprising a detection means for detecting the alignment mark, and an alignment mark for the desired fine pattern so that the desired fine pattern is located within an exposure possible area. A fine pattern exposure apparatus comprising: substrate driving means for moving the substrate until the substrate is detected.
JP60009485A 1985-01-21 1985-01-21 Substrate for exposure of minute pattern and apparatus for exposing minute pattern Pending JPS61168227A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60009485A JPS61168227A (en) 1985-01-21 1985-01-21 Substrate for exposure of minute pattern and apparatus for exposing minute pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60009485A JPS61168227A (en) 1985-01-21 1985-01-21 Substrate for exposure of minute pattern and apparatus for exposing minute pattern

Publications (1)

Publication Number Publication Date
JPS61168227A true JPS61168227A (en) 1986-07-29

Family

ID=11721537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60009485A Pending JPS61168227A (en) 1985-01-21 1985-01-21 Substrate for exposure of minute pattern and apparatus for exposing minute pattern

Country Status (1)

Country Link
JP (1) JPS61168227A (en)

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US6638671B2 (en) 2001-10-15 2003-10-28 International Business Machines Corporation Combined layer-to-layer and within-layer overlay control system
US7439001B2 (en) 2005-08-18 2008-10-21 International Business Machines Corporation Focus blur measurement and control method
US7455939B2 (en) 2006-07-31 2008-11-25 International Business Machines Corporation Method of improving grating test pattern for lithography monitoring and controlling
US7474401B2 (en) 2005-09-13 2009-01-06 International Business Machines Corporation Multi-layer alignment and overlay target and measurement method
US7473502B1 (en) 2007-08-03 2009-01-06 International Business Machines Corporation Imaging tool calibration artifact and method
US7626702B2 (en) 2003-11-19 2009-12-01 International Business Machines Corporation Overlay target and measurement method using reference and sub-grids
US7879515B2 (en) 2008-01-21 2011-02-01 International Business Machines Corporation Method to control semiconductor device overlay using post etch image metrology
US9097989B2 (en) 2009-01-27 2015-08-04 International Business Machines Corporation Target and method for mask-to-wafer CD, pattern placement and overlay measurement and control
US9927718B2 (en) 2010-08-03 2018-03-27 Kla-Tencor Corporation Multi-layer overlay metrology target and complimentary overlay metrology measurement systems
US10890436B2 (en) 2011-07-19 2021-01-12 Kla Corporation Overlay targets with orthogonal underlayer dummyfill

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55140839A (en) * 1979-04-23 1980-11-04 Hitachi Ltd Mask and its preparation
JPS59125733A (en) * 1983-01-04 1984-07-20 Nec Kyushu Ltd Photomask
JPS59161033A (en) * 1984-02-17 1984-09-11 Hitachi Ltd Photo mask

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55140839A (en) * 1979-04-23 1980-11-04 Hitachi Ltd Mask and its preparation
JPS59125733A (en) * 1983-01-04 1984-07-20 Nec Kyushu Ltd Photomask
JPS59161033A (en) * 1984-02-17 1984-09-11 Hitachi Ltd Photo mask

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6638671B2 (en) 2001-10-15 2003-10-28 International Business Machines Corporation Combined layer-to-layer and within-layer overlay control system
US7626702B2 (en) 2003-11-19 2009-12-01 International Business Machines Corporation Overlay target and measurement method using reference and sub-grids
US7439001B2 (en) 2005-08-18 2008-10-21 International Business Machines Corporation Focus blur measurement and control method
US7474401B2 (en) 2005-09-13 2009-01-06 International Business Machines Corporation Multi-layer alignment and overlay target and measurement method
US7876439B2 (en) 2005-09-13 2011-01-25 International Business Machines Corporation Multi layer alignment and overlay target and measurement method
US8107079B2 (en) 2005-09-13 2012-01-31 International Business Machines Corporation Multi layer alignment and overlay target and measurement method
US8339605B2 (en) 2005-09-13 2012-12-25 International Business Machines Corporation Multilayer alignment and overlay target and measurement method
US7585601B2 (en) 2006-07-31 2009-09-08 International Business Machines Corporation Method to optimize grating test pattern for lithography monitoring and control
US7455939B2 (en) 2006-07-31 2008-11-25 International Business Machines Corporation Method of improving grating test pattern for lithography monitoring and controlling
US7473502B1 (en) 2007-08-03 2009-01-06 International Business Machines Corporation Imaging tool calibration artifact and method
US7879515B2 (en) 2008-01-21 2011-02-01 International Business Machines Corporation Method to control semiconductor device overlay using post etch image metrology
US9097989B2 (en) 2009-01-27 2015-08-04 International Business Machines Corporation Target and method for mask-to-wafer CD, pattern placement and overlay measurement and control
US9927718B2 (en) 2010-08-03 2018-03-27 Kla-Tencor Corporation Multi-layer overlay metrology target and complimentary overlay metrology measurement systems
US10527954B2 (en) 2010-08-03 2020-01-07 Kla-Tencor Corporation Multi-layer overlay metrology target and complimentary overlay metrology measurement systems
US10890436B2 (en) 2011-07-19 2021-01-12 Kla Corporation Overlay targets with orthogonal underlayer dummyfill

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