JPS61166633A - State signal input circuit containing self-diagnosis function - Google Patents

Abstract

PURPOSE:To specify a fault area and to simplify a fault detecting job of an internal circuit by detecting automatically the fault area by a state signal input circuit containing a self-diagnosis function. CONSTITUTION:The check data generating circuits CD1, CD2... supply the contact signal as the check data to the input of a data reading circuit including contacts SW1, SW2... with the signals Sbn applied from a data processor PROC in a prescribed cycle. A transistor switch SWX is connected between a common line CPM and the circuits CD1, CD2... respectively. Then the SWX is driven by the signal SC1 given from the processor PROC. At the same time, a switch state reading circuit RC1 reads the state of the SWX and the signal Sd1 is applied to the PROC. Then a fault area is detected automatically by an input circuit and specifies it. Thus a fault detecting job is simplified for an internal circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a status signal input circuit used in a data processing system using a computer.

<Prior Art> FIG. 3 is a circuit diagram showing a conventional example of a data reading circuit that reads multi-point status signals. In the figure, TI.

T2. T3... is a transformer that DC-insulates the input side and the output side. SWI is a contact as a status signal generating means connected between the signal line W1 on the primary side of the transformer T1 and the common line COM, SW2. SW3... is a contact point similarly connected to the signal lines W2, W3... and the common line COM.

C1 is a capacitor connected between the signal line W1 and the common line COM for smoothing chattering components caused by the contact SW1. C2°C3... are also signal lines W2. These are chattering component smoothing capacitors connected between W3... and COMO 294200M, respectively.

Dl is a diode switch connected in the signal line W1, and a pulse excitation voltage ep is applied to this diode from a diode De. D2, D3... are also signal lines W2. W3... is a diode switch connected inside, and a pulse excitation voltage ep is applied from the diode [)e.

C1' is a rectifier diode connected in the signal line W1' on the secondary side of the transformer T1. D2'.

C3'...are also signal lines W2', W3'
...This is a rectifier diode connected inside.

R1 and C1' are a resistor and a capacitor connected between the signal line W1' and a reference potential and forming a smoothing circuit.

R2, C2', R3, C3', . . . are resistors and capacitors that constitute a smoothing circuit, respectively connected between the signal lines W2’, W3’, . . . and a reference potential.

Bl, 82. B3... amplifies the voltage of the smoothing circuit and sends a signal 3a to a data processing device PROC such as a computer.
This is an inverter that outputs n.

With such a configuration, contact SW1. SW2゜SW3...
When B1. B2. It is inverted at B3... and given to the data processing device fPROc as an O11 output.

On the other hand, contact SW1. SW2. When SW3... is on, the negative side is connected to the diodes D1, 02... A short circuit occurs through D3..., and there is almost no copying of the signal to the secondary side, but this status signal is transmitted to the inverter B1, 82, 83...
is inverted, outputs the 111 II ratio and sends it to the data processing device P.
Given to ROC.

In this way, the contacts SW1. SW2. SW3...state 1□16°
(□゛□By the way, in such a status signal input circuit, the part A surrounded by the one-dot chain line is usually modularized. When checking whether the internal circuit is normal or abnormal, the contacts SW1, SW2, SW3, etc. Checks were carried out by manually turning on and off the input terminals to which the system was connected.As a result, the task of detecting failures in the internal circuits was extremely troublesome, and the problem was that it took time to find the failure location.

<Problems to be Solved by the Invention> The technical problems to be solved by the present invention are such that in an input circuit that handles a plurality of status signals, failure points can be easily and quickly discovered, and failure points can be clearly identified. The purpose is to do so.

<Means for Solving the Problems> The configuration of the present invention includes a plurality of status signal generation means connected between a signal line and a common line, and a plurality of status signal generation means for reading status signals from these status signal generation means. a data reading circuit;
A data processing device to which read data from these data reading circuits is given, a switch provided between the navigation status signal generation means and the common line, and a check data generator that provides check data to the input of the data reading circuit. and a switch state reading circuit for checking the state of the switch.

<Operation> The above technical means operates as follows. That is, the switch and the check data generation circuit are turned off based on a signal given from the data processing device at a predetermined period, and after confirming the off state of these elements, the check data generation circuit generates a check signal. Data is applied to the inputs of the data reading circuits, the states of these data reading circuits are checked, and an abnormality message is generated for defective data reading circuits.

<Example> The present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In the figure, the same elements as those in FIG. 3 are given the same reference numerals, and explanations thereof will be omitted.

CD1. CD2. CD3... is data processing yJ! Signal sbn+, given at a predetermined period from device PROC:
Based on the switch SW1. This is a check data generation circuit that provides a contact signal as check data to the input of a data reading circuit including SW2, SW3, and so on.

SWx is a transistor switch connected between the contacts SW1.8W2.3W3 --- and the 5-mon line COM. oCl is a transistor switch SWX based on a signal SC1 given from the data processing bag fifPROC.
This is a switch output circuit that provides a drive signal to. PCI is a switch-like B reading circuit that checks the state of the switch SWX, and the signal Sdl from here is sent to the data processing device PRO.
It is given to C.

The operation of such an apparatus will be explained according to the flowchart shown in FIG. Steps (1) to (4) are check preparation work, and in step (1), switch S
WX is the signal S given by the data processing device PROC.
Based on C1, it is turned off. When checking this,
Contact SW1゜SW2. SW3... may be on, so disconnect it from the common line COM,
These contacts are always turned off.

In step (2), check data generation circuit C
D1. CD2. CO3... is turned off based on the signal 3bn given at a predetermined period, and step (3
), the status signal Sd1 of the switch SWX is read. Based on this signal, in step (4), switch SW
The off state of X is determined.

If it is determined that the switch SWX is off, step (5)
), and if it is determined that the switch SWx is on, the process advances to step (6), where a message indicating that the switch SWX is defective is issued.

Steps (5) to (12) are performed on transformer T1. T2゜T3・
. . , inverters B1, 82, 83, . . . , and inverters B1, 82, 83, and so on, respectively.

In step (5), the state of each data reading circuit is
Reading 1t''・2?77 (7) I, :13°゛1・hus'
The off state of the data reading circuit No. 1 is determined.

When it is determined that the data reading circuit is in the off state, that is, inverters B1, 82 . If all the outputs of B3... are in the "O°" state, the process proceeds to step (8), and if it is determined that the data reading circuit is in the on state, that is, the inverter B1
,82. The output of one of B3... is °゛1'°1'
If the data reading circuit is in the short-circuited state, the process proceeds to step (9) and sends a message that the data reading circuit is in the short-circuited state.

In step (8), check data output circuit C
D1. CD2. CD3... are all turned on, and in step (10), the state of each data reading circuit at that time is read. In step (11), if it is determined that the data reading circuit is in the on state, that is, the inverter 8
1. If all the outputs of B2゜B3, . . .
If any output of B3... is in the "0" state,
Proceeding to step (12), a message indicating that the data reading circuit is defective is sent.

Next, steps (13) to (20) are preparatory work for reading contact signals from the outside. In step (13), check data output circuit CD1. CD2. CD
3... is the signal Sbn from the data processing device PROC.
Based on this, it is turned off. In step (14), the state signal 3'an of each data reading circuit is read, and in step (15), the off state of each data reading circuit is determined.

If it is confirmed that all the data reading circuits are in the off state, proceed to step (16) and turn on the switch SWX, and if any of the data reading circuits is determined to be in the on state,
Proceeding to step (17), a message indicating that the data reading circuit is defective is sent.

In step (18), the state of switch SWX is read, and in step (19), the on state of switch SWX is determined.

If it is determined that the switch SWX is off, step (2)
0) and sends a message indicating that the switch SWX is defective.

If it is determined that the switch SWX is on, step (2)
Moving on to step 1), regular data is read.

Such checking work is performed at predetermined intervals based on a signal given from the data processing device PROC.

<Effects of the Invention> According to the present invention, in a data reading circuit that handles a plurality of status signals, a fault location is automatically detected and the fault location is clearly indicated, which greatly simplifies the task of detecting a fault in an internal circuit. Become.

[Brief explanation of drawings]

FIG. M1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a flowchart for explaining the operation of the embodiment of the present invention shown in FIG. 1, and FIG. 3 is a circuit diagram of a conventional device. SWI, SW2. SW3...Contact, Wl, W2゜W3
...Signal line, COM...Common line, TI. T2. T3...Transformer, Dl, D2. D3...Switching diode, De...Diode that provides pulse excitation voltage, PROC...Data processing device, SW
X...Transistor switch, CDI.

Claims (1)

[Claims] A plurality of status signal generating means connected to the line between the signal line and the common line, a plurality of data reading circuits reading the status signals from these status signal generating means, and read data from these data reading circuits are provided. a data processing device;
A switch provided between the status signal generation means and a common line, a check data generation circuit that supplies check data to the input of the data reading circuit, and a switch status reading circuit that checks the status of the switch,
The switch and the check data generation circuit are turned off based on a signal given from the data processing device at a predetermined period, and after confirming the off state of these elements,
A self-diagnosis function is provided which applies check data from the check data generation circuit to the input of the data reading circuit, checks the status of these data reading circuits, and generates an abnormal message for a defective data reading circuit. Status signal input circuit.