JPS61166279A - Two-screen television receiver - Google Patents

Abstract

PURPOSE:To improve the picture quality of a slave screen and to reduce the entire system cost by inputting a synthesis video signal input to a 1 frame memory possible for read/write at each picture element and outputting the signal as a video signal synthesized into a video signal to be synthesized via two sets of buffer memories for horizontal period possible for read/write at each horizontal period. CONSTITUTION:A slave video signal is inputted from a terminal 2 and inputted to a read/write frame memory 101 at each picture element. The write on buffer memories 102, 103 is executed by using the 2nd clock 111 and the read is controlled by using the 3rd clock 112. A read end detection circuit section 109 of buffer memory counts the 3rd clock 112 and when the end of read of the buffer memory is detected, an output 113 is generated. A buffer memory input switching section 104 switches the data flow to a buffer memory A102 or B103 and a buffer memory output switch circuit section 105 outputs data from the buffer memory A102 or the B103 alternately as a synthesis video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a two-screen television receiver capable of inserting another video screen into a part of the video on the screen.

Conventional technology First, FIG. 3 shows a conceptual diagram of a two-screen television.

This is an example in which a child screen 302 is combined with a main screen 301.

The two main basic functions of a two-screen TV are as follows.0 (2L) The synchronization of the composite video and the composite video is unrelated to each other, that is, the phase and frequency are different, so the synchronization of the composite video is the same as the composite video. synchronization (deflection synchronization signal for CRT)
A function to adjust the time axis to match.

(b) A function to reduce the composite screen from its original size during screen composition.

There is a conventional example in which such a function is implemented using a buffer memory and one field memory.

To explain this example, first, the relationship between the two-screen television circuit section and the peripheral circuits will be explained with reference to FIG.

The input video switching circuit section 201 selects and switches between the parent (to be combined) video and the child (combined) video.

Its input is, for example, a plurality of tuner/VIP circuits 2
02, 203, and other video equipment 204 (for example, VCR,
disc, camera, etc.), one of which is sent to the parent video processing circuit 205 and the parent synchronization separation circuit 20.
6, and another one is supplied to the child video processing circuit section 207 and the child synchronization separation circuit section 208.

In the two-screen television circuit section 1, the video signal 2 from the child video processing circuit 207 is basically written once into the memory with the synchronization signal 3 from the child synchronization separation circuit section 208, and then the synchronization signal from the parent synchronization separation circuit section 206 is written. By reading the video signal 5 from the memory in step 4, a video signal 5 for synthesis is output. This video signal 5 is combined with the parent video from the parent video processing circuit 205 by the output signal switching unit 209 and output to the CRT 210 which is deflected by the synchronization signal from the parent synchronization separation circuit 206 .

FIG. 6 is a block diagram of a conventional example of the two-screen television circuit section 1, focusing on the flow of signals. 2 and 5
correspond to FIG. 2, and are a child video signal input and a video signal output for synthesis, respectively.

401 is a buffer memory for horizontal scanning, and 402 is a 1-field memory that can be read and written in every horizontal period (hereinafter abbreviated as H).

As mentioned above, the main basic function 2 of a two-screen TV is
In terms of circuit design, it is not possible to write and read from memory at exactly the same time when aligning the time axes of the parent and child, so the key is how to organize the time relationships.

A case where the child screen 302 is smaller both vertically and horizontally with respect to the main screen 301 will be described with reference to the timing diagram of FIG. First, as shown in FIG. 7a, the buffer memory 4
Write data to 01 in accordance with the child H signal. However, it is sufficient to write only 1H in 3H to make it rare in the vertical direction. Since the backup memory 401 has a capacity of only 1H, the field memory 401, which is the main memory
02 (i.e. buffer memory 401
(read from the field memory 402 and write it to the field memory 402). As for the timing, Buffer Memo IJ
This is a period in which the field memory 401 is not performing a write operation and the field memory 402 is not performing a read operation.

As shown in FIG. 5C, the field memory 402 is read every H period in accordance with the parent H signal during the period when the child screen 302 is output on the screen. However, in order to compress the field memory 4026I\- in the horizontal direction, it is read out at approximately three times the speed of writing to the field memory 4026I\-. Sub screen 3
Field memo during the period when 02 is output! J402
However, if the buffer memory 40 in Fig. 7a
If the write period of 1 is set to less than % between the child's H period and , the read period of the field memory 402 in FIG.
As described above, there is a margin of about %H between readings of the field memory 402 due to the %H off period. You can use this time to send the data in the sofa memory 401 to the field memory 402.

Problems to be Solved by the Invention However, the above conventional example has the following two problems.

(1) There is a problem that information around the 5th screen cannot be displayed on the child screen 302. Ideally, the main screen 301 and child screen 3
I want to make the information display area of 02 the same.

Considering the sample period within H of the necessary child screen information at that time, the period during which the information exists on the solid line in the horizontal period is 0.
．． It is about 835 H period. If 90% of that is displayed on the screen due to the characteristics of the TV receiver, then 0.
835HX0.9-〇, 75H. Even with the conventional method,
If the absolute values of the H periods of the parent and child are the same, there is no problem because the data of the percentage of the H period of the child can be handled. However, in reality, depending on the operation of the video equipment 204 that is the video signal source for the sub-screen, the normal H period t,b may be approximately 63.5 μS.
QC may deviate from the QC, so even when the H period of the child is longer than the H period of the parent, the child screen must be The sample period within H of information is 0.75H
We have to design it for a fairly short period of time. As a result, information on the left and right sides of the screen is cut off, which is particularly inconvenient when there is text information in the cut-off area.

(2) The field memory 402, which is the main memory, is required to have a fast read speed.

This is because compression in the H direction is performed at the stage of reading from the main memory, as shown in FIG. 7C.

High-speed main memory is expensive, so in order to reduce its capacity, it is difficult to store one frame of data, and the memory is half that amount, one field. However, this results in significant image quality deterioration when the child screen 302 is a still image. In other words, when shooting a moving image, the contents of the main memory are always updated, so there is no problem, but when shooting a still image, data writing to the main memory is stopped and the contents of the field memory 402 are changed. When reading , the contents of the even and odd fields are equal, so the vertical resolution is halved.

There is an inconvenience that if you try to write down certain text information as a still image, it will be unreadable.

Means for Solving the Problems In the two-screen television receiver of the present invention, a video signal for synthesis is first input into a one-frame memory that can be read and written pixel by pixel, and then read and written in each horizontal period. The video signal is outputted as a video signal to be combined with the video signal to be combined via two sets of buffer memories corresponding to the non-writable horizontal period.

Effect Regarding problem (1) mentioned above, since the two sets of buffer memories are read and written alternately, all the data within the H period of the sub-screen can be taken in in principle, and the peripheral information of the screen is cut off. Never.

Regarding problem (2), data compression in the H direction is not performed in the 1-frame memory, which is the main memory, but is performed in the subsequent buffer memory, so that the operating speed of the main memory can be reduced.

In other words, an inexpensive main memory can be used. Buffer memory has a simple operation and a small capacity, so its proportion in cost is small.

In the end, even if the main memory capacity is increased to one frame, which is twice the capacity of one field, the cost of the entire system can be lower than that of the conventional method. Furthermore, since the main memory has enough space for one frame, there is no deterioration in image quality when a still image is taken.

Example 211 of an example of the present invention! The ¥1-page television receiver 10 will be explained with reference to FIG. This figure shows the second
This corresponds to the two-screen television circuit section 1 shown in the figure.

The child video signal is input from 2 and is input to the frame memory 101 in a readable and writable manner for each pixel.

The output is transmitted via a buffer memory input switching circuit section 104 to a buffer memory IJ A 102 or a buffer memory B 103, which can be read and written every horizontal period. The buffer memory output is provided by the buffer memory output switching circuit section 10.
5 and output as a composite video signal.

Writing to the frame memory 101 is controlled by a clock generation circuit section (1) 106, and reading is controlled by a clock generation circuit section (2) 107.

The former control output is referred to as a first clock 110, and the latter control output is referred to as a second clock 111. Buffer memory 10
The writing of 2,103 is performed by the second clock 111, and the reading is controlled by the third clock 112 which is the output of the clock generation circuit section (3) 108. The buffer memory continuous reading end detection circuit section 109 counts the third clock 112 and generates an output 113 when it detects the end of reading from the buffer memory. The buffer memory input switching unit 104 alternately switches the flow of data to the buffer memory IJ A 102 or the buffer memory B 103 each time this read end detection output 113 is input. The buffer memory output switching circuit section 105 alternately outputs data from the buffer memory IJA 102 or the buffer memory B 103 as a video signal for synthesis using the parent H signal input 4.

Next, the operation when the size of the child screen 302 is IA both vertically and horizontally with respect to the main screen 301 is shown in FIGS.
This will be explained with reference to the drawings.

FIG. 6a is an output timing diagram of the first clock 110. This indicates that writing to the frame memory 101 is being performed within the range of the child H signal. The reason why it is written only once in the 3H period is because it is thinned out to make the vertical direction oak.

Since the first clock 110 samples the child video signal 2, it is required to be synchronized with the child H signal 3. A clock having a period corresponding to the number of samples is output during the period shown in FIG. 4a.

On the other hand, the third clock 112 that controls reading of the buffer memories 102 and 103 must be synchronized with the parent H signal 4 and output within the range of the parent H signal 4. If the child screen 302 is output at the left end of the screen, the third clock 112 is output at the left end of the parent H signal 4 as shown in FIG. 4f. The output period is compressed to the writing period of the frame memory 101 by the first clock 111. In principle, the period of the third clock 1120, which is the read clock, is false compared to the first clock 11.0, which is the write clock.

The continuation end detection circuit section 109 outputs an output 113 as shown in FIG. 6g. This is input to the clock generation circuit section [2] 107 at the same time as controlling the buffer memory input switching section 104 as described above, and starts outputting the second clock 111. The output period is shown in FIG.

The relationship between the first clock 110 and the second clock 11113 will be explained with reference to FIGS. 5g and 5h, which are enlarged views of periods P in FIGS. 4a and 4b. As shown in the figure, the periods of the first clock 110 and the second clock 111 are equal to Q, and the phases differ by 180 degrees.

It is assumed that the write operation of the frame memory 101 is performed in the first half of the period Q, and the read operation is performed in the second half. That is, since reading and writing to and from the frame memory 101 are performed alternately, there is no problem even if the output period of the first clock 110 and the output period of the second clock 111 overlap as shown in FIGS. 4a and 4b. 1H worth of data is read from the time when the successive end detection output 113 of e is received.

The read data is alternately written into buffer memories 102 and 103. This state is shown in FIG. 4C9d. The read period of the buffer memories 102 and 103 is limited to f. The basic idea is to rewrite the data in the buffer memory that has been read. Therefore, writing continues to the same buffer memory that was being read before the successive end detection output 113 is output.
4 pages. As for the switching timing of the buffer memory output switching circuit unit 105, since the read period of the buffer memory always falls within the parent H signal, switching is performed using the parent H signal 4. As for the switching timing of the buffer memory input switching circuit unit IQ4, if the read detection output is set to 113, the margin is maximized when the period of the parent H signal 4 becomes relatively small with respect to the child H signal 3. can.

Effects of the Invention According to the two-screen television receiver of the present invention, since a frame memory that can be read and written for each pixel is used, when looking at each H signal, writing is performed on the child's H signal, and reading is performed on the parent's H signal. , each can be combined.

In the post buffer memory, synchronization at the pixel level and H
The data output period in the direction is compressed. The effects will be described in relation to the two problems mentioned in the section of problems to be solved by the invention.

(1) Regarding the peripheral cutoff of child screen information.

In the circuit of the present invention, the limitation on the write period 15, of the small screen signal occurs when the read periods of adjacent H periods of the frame memory overlap. If the child's H period and the parent's H period are equal, it is possible to write all the data in the H period. As the cycle of the parent's H period becomes smaller relative to the child's H period, the writeable period becomes shorter, but if the write period is po, 75H according to the calculation above, then per 1H period. There is a margin of relative error of 25 degrees, which is sufficient. Therefore, peripheral cut-off of the child screen information does not occur. Note that according to this circuit, the reading period of the child screen information can be varied up to the point where 1=1 with the writing period.

Therefore, the size of the child screen can be arbitrarily set up to the maximum size of the parent screen, and is not limited to Tateaki x YokoAkira, which was explained in the explanation.

((2) Regarding the problem of main memory read/write speed.

A comparison will be made between the conventional example and the present invention. The output period in the H direction of the sub screen is Th, and the number of pixels (number of samples) per 1H is n.
It is also assumed that the read and write cycles of the memory are equal, Tc. In the conventional example, the highest speed is when n pieces of data are read from the field memory during Th 0, and Tc=Th/n.

In the present invention, the speed is highest when the read and write periods of the frame memory overlap, and the speed is 3
Since n pieces of data are read and n pieces of data are written during the period, Tc=(3xTh)/(n
X2 )=(1,5×'rh )/n.

In other words, the main memory of the present invention is 1.5 times larger than the conventional example.
You can use something twice as slow. Here, by substituting specific numerical values, Th is the write period of sub-screen data of 0.
If it is 75H, it is Akira. Although n is a pixel, it is not considered as an actual pixel on the screen, but as a unit of data input/output to the memory.

When storing color video signals in memory, it is common to separate them into luminance and color difference signals to reduce memory capacity, and the sampling speed of each is set to 4:
It is normal to set it to 1.

Therefore, in order to match the speed of luminance and color difference data,
Perform data synthesis before putting it into memory.

17 Desired - The number of unit data of H adashi at this point is considered to be n. It is advisable to select 2 to the nth power from the viewpoint of memory configuration, and in consideration of image quality, it is selected to be n-64.

In this way, the Tc of the conventional example becomes 248 n5eC.
Tc of the present invention is 372 Hsec.

The reason why this difference has a large effect on cost is due to the following circumstances. There are two general types of digital RAM: static RAM and dynamic RAM. The operating speed is high for the former and slow for the latter, and the boundary between them is about 250 nSeC with current technology. Considering the operating speed required for the conventional main memory, considering the design margin, it is necessary to use static RAM. On the other hand, since the present invention may be 1.5 times slower than the conventional example, the dynamic RAM can be fully used as the main memory.

Comparing the memory cost per unit capacity, dynamic RAM has a simple storage method and the circuit scale within the memory is much smaller than that of static RAM.

Even if the main memory capacity is doubled to 17 x 18 vapor and the image quality of still images is improved, the price of the entire system can be kept lower than the conventional model, making it practical. Above all, it is extremely advantageous.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of a two-screen television receiver in an embodiment of the present invention, FIG. 2 is a block diagram of the entire two-screen television receiver, and FIG. 3 is a conceptual diagram of the two-screen television receiver. 4 and 5 are operation timing diagrams of a two-screen television receiver according to an embodiment of the present invention, FIG. 6 is a block diagram of the main parts of a conventional two-screen television receiver, and FIG. 7 is a diagram of the conventional two-screen television receiver. FIG. 3 is an operation timing diagram of the screen television receiver. 1...Two side TV circuit section, 2...Composition side video signal input terminal, 3...Composition side video horizontal synchronization signal input terminal, 4...・Horizontal synchronization signal input terminal for video to be synthesized, 5... Video signal output terminal for synthesis, 101... Frame memory, 102, 1
03...Buffer memory, 104...Buffer memory input switching circuit section, 105...Buffer memory output switching circuit section, 19/106...Clock generation circuit section ( 1), 107・
...Clock generation circuit section (2), 108...
... Clock generation circuit section (3), 109 ... Read end detection circuit section, 110 ... First clock,
111... Second clock, 112...
- Third clock, 113... Read end detection output. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 71 Tomokarirobuki 4-move style 471 Ni-kyo -00

Claims (2)

[Claims] (1) One frame memory that can be read and written for each pixel, two sets of buffer memories for the horizontal period that can be read and written for each horizontal period, and a first clock that is synchronized with the horizontal synchronization signal of the composite side video. and a second clock whose phase is 180 degrees different from this first clock,
A circuit that generates a third clock synchronized with the horizontal synchronization signal of the video to be synthesized, and a circuit that writes to the frame memory using the first clock in synchronization with the horizontal synchronization signal of the video to be synthesized; is read out using the second clock in accordance with the horizontal synchronization of the image to be synthesized,
The reading and writing of the two sets of buffer memories are alternately switched in accordance with the horizontal synchronization of the video to be synthesized, and the clock control means is configured to perform writing using a second clock and reading using a third clock. Features a 2-screen TV receiver. (2) It has a means for detecting the end of reading from the buffer memory, and the detection output switches which of the two buffer memories data is input to, and which one to read from is switched by the horizontal synchronization signal of the video to be synthesized. 2. The two-screen television receiver according to claim 1, wherein writing is subsequently started in the same buffer memory that was being read before the detection output.