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JPS61166147A - Multilayer hybrid integrated circuit device - Google Patents

Multilayer hybrid integrated circuit device

Info

Publication number
JPS61166147A
JPS61166147A JP60007815A JP781585A JPS61166147A JP S61166147 A JPS61166147 A JP S61166147A JP 60007815 A JP60007815 A JP 60007815A JP 781585 A JP781585 A JP 781585A JP S61166147 A JPS61166147 A JP S61166147A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
shield
circuit board
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60007815A
Other languages
Japanese (ja)
Inventor
Yoshio Miura
三浦　敬男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP60007815A priority Critical patent/JPS61166147A/en
Publication of JPS61166147A publication Critical patent/JPS61166147A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To reduce the number of manufacturing processes and to lower the manufacturing cost by a method wherein a first and second hybrid integrated circuit substrates are piled one upon the other by using a framework so that a first and second external leads may be arranged on different sides. CONSTITUTION:A framework 27 is composed of such insulating material as synthetic resin. Along the sides opposed to the sides of a first, second hybrid intetgrated circuit substrate 20, 30 not provided with leads 26, 26', a shield 31 is installed to expose outward the leads 26, 26'. On both back and upper surfaces wherein the first, second hybrid integrated circuits fit, the surface of a step 29 and that of the shield 31 are in the same plane, and the step 29 and shield 31 keep a distance 28 between the two substrates 20, 30. An adhesive sheet is placed on the surfaces of the step 29 and shield 31. The sides provided with the lead 26 of the first substrate 20 are caused to coincide with the shield 31 and are put into the framework 27 and, further, the sides provided with the lead 26' of the substrate 30 are caused to coincide with the shield 31, also inserted, with their internal main surfaces facing each other, to be subjected to adhesion by an adhesive layer 23 with the intermediary of the framework 27.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明は混成集積回路基板が積層されてなる多層混成集
積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a multilayer hybrid integrated circuit device formed by stacking hybrid integrated circuit boards.

（ロ）従来の技術 第６図は、従来の混成集積回路装置を示す断面図である
（特公昭４６−６２３５号公報参照）。(B) Prior Art FIG. 6 is a sectional view showing a conventional hybrid integrated circuit device (see Japanese Patent Publication No. 46-6235).

従来による複合集積回路は第Ｃ図に断面図にて示す如く
金属基板（１）上に設けられた第１の混成集積回路（２
）と、絶縁物基板１３１１に設けられた第２の混成集積
回路（４）とが、固着層（５）によって積層一体化して
構成される。A conventional composite integrated circuit consists of a first hybrid integrated circuit (2) provided on a metal substrate (1), as shown in the cross-sectional view in Figure C.
) and a second hybrid integrated circuit (4) provided on an insulating substrate 1311 are laminated and integrated by a fixing layer (5).

第１の混成集積回路（２）は、金属基板（１）例えばア
ルミニウム上に設けられてなる。金属基板（１）は、そ
の表面に絶縁物層（６）によって基板（１）の全面に粘
着し後に選択的に残して形成された第１の内部リード部
（７）を有し、その上部にはトランジスタ（９）、抵抗
（Ｉｆｆ）等の成子部品が固着形成される。また金属基
板（１）の外周縁部を枠状に連続し銅箔層が残され第１
の固着部（８）を形成する。The first hybrid integrated circuit (2) is provided on a metal substrate (1), for example aluminum. The metal substrate (1) has a first internal lead portion (7) formed on its surface by an insulating layer (6) that adheres to the entire surface of the substrate (1) and is selectively left behind. Components such as a transistor (9) and a resistor (Iff) are fixedly formed on the substrate. In addition, a copper foil layer is left on the outer peripheral edge of the metal substrate (1) in a continuous frame shape.
A fixed portion (8) is formed.

第２の混成集積回路（４）は、絶縁性接着材（１１）で
銅箔を固着した後に所望形状を有する様に残された第２
の内部リード（１２）を有する。また、第１の混成集積
回路（２）の第１の固着部（８）に対応せしめて、第２
の混成集積回路（４）の絶縁物基板（３）の外周縁部を
枠状に連続して、金属箔層が残され第２の固着部（１３
）が形成される。The second hybrid integrated circuit (4) consists of a second hybrid integrated circuit (4) that is left in a desired shape after the copper foil is fixed with an insulating adhesive (11).
It has an internal lead (12). Further, a second fixed part (8) of the first hybrid integrated circuit (2) is provided.
A metal foil layer is left on the outer periphery of the insulator substrate (3) of the hybrid integrated circuit (4) in a continuous frame shape, and a second fixed part (13) is formed.
) is formed.

両者は、半田合金層側、スペーサー（１５ｉ、半１１］
合金層（１６）の３層から成る固着層（５）によって強
固に［４〜つ電気的に結合して固着積層される。Both have a spacer (15i, half 11) on the solder alloy layer side.
A fixing layer (5) consisting of three alloy layers (16) is used to firmly electrically bond and stack the alloy layers (16).

ｅ→　発明が解決しようとする問題点 上述した従来の混成集積回路技術では、夕１部から絶縁
物基板（３）を介して到達するノイズが回路に影響を与
える。また、外部リードを取出す為にスルーホールを絶
縁物基板（３）に設げノ、【げればな、らない。従って
第１の混成集積回路（２）と、第２の混成集積回路（４
）は、それぞれ異なる製造工程によって製造されるので
工程数の増加によりコスト高になる。e→ Problems to be Solved by the Invention In the above-described conventional hybrid integrated circuit technology, noise arriving from the first part through the insulating substrate (3) affects the circuit. In addition, through holes are provided in the insulating substrate (3) to take out external leads. Therefore, the first hybrid integrated circuit (2) and the second hybrid integrated circuit (4)
) are manufactured by different manufacturing processes, so the cost increases due to the increase in the number of processes.

に）問題点を解決するための手段 本発明は、上述した点に鑑ろて為されたものであり、第
１の混成集積回路基板と第２の混成集積回路基板の（■
対する一主面に設けられプこ回路素子と、前記第１基板
の少なくとも一辺に設けた膜数の電極バンドから導出さ
れた第１の外部リードと第１の外部リードが設けられた
辺と異なる辺に対応する第２の混成集積回路基板の少な
くとも一辺から導出された第２の外部リードを備え、第
１、第２の外部リードが異なる辺に配列するように枠体
を用いて第１及び第２混成集積回路基板を積層するもの
である。The present invention has been made in view of the above-mentioned problems, and includes a first hybrid integrated circuit board and a second hybrid integrated circuit board.
A circuit element provided on one main surface of the first substrate, a first external lead derived from the electrode band of the number of films provided on at least one side of the first substrate, and a side different from the side on which the first external lead is provided. a second external lead led out from at least one side of the second hybrid integrated circuit board corresponding to the side; A second hybrid integrated circuit board is laminated thereon.

（ホ）作用 第１及び第２混成集積回路基板を積層することによって
高集積化が可能となり、さらに外部ＩＪ−ドの本数を増
加できるので、例えば記憶装置などに使用した場合取扱
う情報量が大きくなる。(e) Effect By stacking the first and second hybrid integrated circuit boards, high integration becomes possible, and the number of external IJ cards can also be increased, so when used in a storage device, for example, the amount of information handled is large. Become.

（へ）実施例 第１図は本発明の実施例を示す断面図であり、四及び例
は混成集積回路基板、（２υ（２１）は金属基板、体、
（２唱ま離間部、０叫′よ段部、ＣＨＩ）は衝立て部、
（３２）はガイド部である。(f) Example FIG. 1 is a sectional view showing an example of the present invention.
(2 parts, 0 parts, CHI) is the screen part,
(32) is a guide portion.

第１の混成集積回路基板（２０）において、金属基板（
２υとしてはアルミニウムが用いられ、その表面は陽極
酸化によって絶縁層（２２）が形成され、さらに銅箔を
所定のパターンにエツチングするごとによって導電路（
２優が形成される。In the first hybrid integrated circuit board (20), the metal substrate (
Aluminum is used as 2υ, and an insulating layer (22) is formed on its surface by anodizing, and a conductive path (22) is formed by etching the copper foil into a predetermined pattern.
2nd place is formed.

この導電路（２侶ま金属基板（２１）の対向する側辺に
延在され、その端部は電極パッドとなる。そして電極パ
ッドには、各々のリード（２６）が半田により接続固着
され、リード（２６）は混成集積回路基板（２（１１の
回路形成面と反対方向に曲折される。This conductive path (two sides) extends to opposite sides of the metal substrate (21), and its ends serve as electrode pads. Each lead (26) is connected and fixed to the electrode pad by solder. The leads (26) are bent in a direction opposite to the circuit forming surface of the hybrid integrated circuit board (2 (11).

第２の混成集積回路基板００）は、第１の混成集積回路
基板（２０）とほぼ同様に形成されるが、導電路（２４
）は第１の混成集積回路基板（２０）のリード（２６）
の固着された側辺と異なる側辺に延在され、その電極パ
ッド上にはリード１３［ｉ）が接続固着され回路形成面
方向に曲折される。The second hybrid integrated circuit board (00) is formed in substantially the same manner as the first hybrid integrated circuit board (20), except that the conductive paths (24)
) are the leads (26) of the first hybrid integrated circuit board (20).
A lead 13[i] is connected and fixed onto the electrode pad and bent toward the circuit forming surface.

メモリーチップ（２５＋（２５）は、金属基板（２１）
０υ上に配置することにより放熱性がセラミック基板よ
り優れ、基板当り８〜１０コのメモリーチップ（２５）
（２５＋が高密度に実装できる。メモリーチップ（２５
）（２阻ま所定の導電路Ｃ４）（２ａ上に固着する。Memory chip (25+(25) is a metal substrate (21)
Heat dissipation is superior to ceramic substrates due to placement on 0υ, allowing 8 to 10 memory chips per substrate (25)
(25+ can be mounted with high density.Memory chip (25+)
) (2 blocked predetermined conductive path C4) (fixed on 2a).

第３図は、第１、第２混成集積回路（２０１Ｇｌｌ＋を
積層するために用いる枠体（２７）の平面図であり、第
４図、第５図は、第３図のＡ−Ａ断面、Ｂ〜Ｂ断面であ
る。FIG. 3 is a plan view of the frame (27) used for stacking the first and second hybrid integrated circuits (201Gll+), and FIGS. 4 and 5 are cross sections taken along line A-A in FIG. This is a cross section from B to B.

枠体（２７）は合成樹脂等の絶縁物で形成され、ガイド
部（３２）、段部（２９）及び、衝立て部（３１）を有
する。第１、第２混成集積回路基板（２０＋　（３０１
のリード（２６）（２６）が設けられてない側辺に対応
する部分には、リード（２Ｆｉ）（２６）を外側に露出
するような衝立て部（３１）が設けられる。The frame (27) is made of an insulating material such as synthetic resin, and has a guide portion (32), a step portion (29), and a screen portion (31). First and second hybrid integrated circuit boards (20+ (301
A screen portion (31) that exposes the leads (2Fi) (26) to the outside is provided in a portion corresponding to the side where the leads (26) (26) are not provided.

第１、第２混成集積回路基板が、はめ込まれる背面及び
上面のそれぞれにおいて段部（２９）及び衝立て部Ｃ３
１）の表面は同一面となり、この段部及び衝立て部（３
１）は第１混成集積回路基板ｔ２（ｊと第２混成集積回
路基板（３０）との離間部（２８）を保っている。ガイ
ド部（３２１は第１混成集積回路基板（２０）及び第２
混成集積回路基板■をはめ込む際の位置規制をするもの
である。A stepped portion (29) and a screen portion C3 are provided on the back and top surfaces into which the first and second hybrid integrated circuit boards are fitted, respectively.
1) will be the same surface, and this stepped part and screen part (3) will be on the same surface.
1) maintains a separation part (28) between the first hybrid integrated circuit board t2(j and the second hybrid integrated circuit board (30). A guide part (321) maintains a separation part (28) between the first hybrid integrated circuit board (20) and the second hybrid integrated circuit board (30). 2
This is to regulate the position when fitting the hybrid integrated circuit board (■).

枠体（２７）の段部斡及び衝立て部（３１）の表面に接
着シートを張り、第１混成集積回路基板（２０ｊのリー
ド（２６）が設けられた側辺と、枠体（潤の衝立て部（
３１）とを一致させ枠体（２７）に挿入する。さらに第
２混成集積回路基板（３＋ｙのリード（２６）の設けら
れた側辺と枠体（２力の衝立て部（３１）を一致させ、
それぞれ内側主面が対向するように挿入し枠体（２７）
を介して接着層（２３＋により接着される。An adhesive sheet is pasted on the surface of the stepped part and the screen part (31) of the frame (27), and the side where the leads (26) of the first hybrid integrated circuit board (20j) are provided and the side of the frame (20j) Screen section (
31) and insert it into the frame (27). Further, align the side of the second hybrid integrated circuit board (3+y leads (26)) with the frame (2-force screen portion (31)),
Insert the frames so that their inner main surfaces face each other (27)
It is adhered by an adhesive layer (23+) through the adhesive layer (23+).

第２図は第１図に示された多層混成集積回路装置の平面
図である。FIG. 2 is a plan view of the multilayer hybrid integrated circuit device shown in FIG.

第１図の如く構成されるように枠体（２７）に固着され
た第１混成集積回路基板（２０）のリード（２［ｉ）＋
’；Ｉ、対向する一対の側辺から導出され、又第２混成
集積回路基板Ｃ３０）のリード（２６）は他の対向する
一対の側辺から導出される。従って第１、第２混成集積
回路基板（２０１（３０＋の電気信号が独立して多数外
部に取り出すことができる。Leads (2[i) +
';I, are led out from a pair of opposing sides, and the leads (26) of the second hybrid integrated circuit board C30) are led out from another pair of opposing sides. Therefore, a large number of electrical signals from the first and second hybrid integrated circuit boards (201 (30+) can be independently taken out to the outside.

（ト）発明の効果 以上の詳述した如く本発明に依れば、混成集積回路基板
は同一工程で製造可能で有り、工数を減Ｓハ すことができ、従来より容易に製造できる。(g) Effects of the Invention As detailed above, according to the present invention, a hybrid integrated circuit board can be manufactured in the same process, the number of man-hours can be reduced, and manufacturing is easier than in the past.

また、基板が金属基板なのでセラミック基板に比べ放熱
性が優れているので高密度の実装ができ、小型で大容量
の混成集積回路装置ができる。さらに第１、第２混成集
積回路基板に固着されたメモリーチップは金属基板及び
枠体によって密封されるので側温性が向上し信頼性がよ
（なる。最後に他の基板に装着した場合、リードと基板
の配線が行ないやすい６．Furthermore, since the substrate is a metal substrate, it has better heat dissipation than a ceramic substrate, allowing for high-density packaging, making it possible to create a compact, large-capacity hybrid integrated circuit device. Furthermore, since the memory chip fixed to the first and second hybrid integrated circuit boards is sealed by the metal board and the frame, side temperature properties are improved and reliability is improved.Finally, when mounted on another board, Easy wiring between leads and board 6.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例を示す断面図、第２図は第１図
に示された実施例を示す平面図、第３図は本実施例の枠
体の平面図、第４図、第５図は第３図のＡ−Ａ断面図、
Ｂ−Ｂ断面図、第６図は従来例を示ず断面図である。 （２（１）Ｃ（０）・・・混成集積回路基板、　（２１
ｊｃ２＋＋・・・金属基板、（２７）・・・枠体、　（
２８）・・・離間部、　（２９）・・段部、　（３１）
・・・衝立て部、　（３２）・・・カイト部。 出願人　三洋電機株式会社　外１名 代理人　弁理士　　佐　野　静　夫 第３図　　　　　３１ ．３１ 第４図　　　　　　第５図 八−Ａ漣ｑ面払人目　　　　　８−８吋面鉱尺。 第６図FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a plan view showing the embodiment shown in FIG. 1, FIG. 3 is a plan view of the frame of this embodiment, and FIG. Figure 5 is a sectional view taken along line A-A in Figure 3;
The BB sectional view and FIG. 6 are sectional views that do not show the conventional example. (2(1)C(0)...hybrid integrated circuit board, (21
jc2++...metal substrate, (27)...frame body, (
28)...Separated part, (29)...Stepped part, (31)
... Screen section, (32) ... Kite section. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuo Sano Figure 3 31. 31 Figure 4 Figure 5 8-A Renq surface payer 8-8 inch scale. Figure 6

Claims (1)

【特許請求の範囲】[Claims] １．　第１、第２の混成集積回路基板と、該第１、第２
の混成集積回路基板の相対する一主面に設けられた回路
素子と、前記第１の混成集積回路基板の少なくとも一辺
に設けた複数の電極パッドから導出した第１の外部リー
ドと、該第１の外部リードが設けられた辺と異なる辺に
対応する前記第２混成集積回路基板の少なくとも一辺に
設けた複数の電極パッドから導出する第２の外部リード
と、前記第１及び第２の混成集積回路基板を離間して配
置する枠体とを備え、第１及び第２の外部リードが、そ
れぞれ異なる辺に配列されることを特徴とする多層混成
集積回路装置。1. first and second hybrid integrated circuit boards;
a circuit element provided on one opposing main surface of a hybrid integrated circuit board; a first external lead led out from a plurality of electrode pads provided on at least one side of the first hybrid integrated circuit board; a second external lead led out from a plurality of electrode pads provided on at least one side of the second hybrid integrated circuit board corresponding to a side different from the side on which the external lead is provided; and the first and second hybrid integrated circuit board. 1. A multilayer hybrid integrated circuit device, comprising: a frame for arranging a circuit board at a distance, and wherein first and second external leads are arranged on different sides.
JP60007815A 1985-01-18 1985-01-18 Multilayer hybrid integrated circuit device Pending JPS61166147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60007815A JPS61166147A (en) 1985-01-18 1985-01-18 Multilayer hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60007815A JPS61166147A (en) 1985-01-18 1985-01-18 Multilayer hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS61166147A true JPS61166147A (en) 1986-07-26

Family

ID=11676089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60007815A Pending JPS61166147A (en) 1985-01-18 1985-01-18 Multilayer hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS61166147A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816896A (en) * 1988-02-01 1989-03-28 Motorola Inc. Compliant standoff for semiconductor packages
US5811877A (en) * 1994-08-30 1998-09-22 Hitachi, Ltd. Semiconductor device structure
JP2008187146A (en) * 2007-01-31 2008-08-14 Sanyo Electric Co Ltd Circuit equipment
WO2019012679A1 (en) * 2017-07-14 2019-01-17 新電元工業株式会社 Electronic module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816896A (en) * 1988-02-01 1989-03-28 Motorola Inc. Compliant standoff for semiconductor packages
US5811877A (en) * 1994-08-30 1998-09-22 Hitachi, Ltd. Semiconductor device structure
JP2008187146A (en) * 2007-01-31 2008-08-14 Sanyo Electric Co Ltd Circuit equipment
WO2019012679A1 (en) * 2017-07-14 2019-01-17 新電元工業株式会社 Electronic module
JP6523567B1 (en) * 2017-07-14 2019-06-05 新電元工業株式会社 Electronic module

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