JPS61163393A - Miscomputation preventing circuit for electronic cirucuit for electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to digital bit number limitation of musical tone data subjected to digital signal processing, and aims to prevent overflow of musical tone data subjected to digital calculations. There is.

[Summary of the invention]

The present invention relates to a digital bit limit for musical tone data subjected to digital signal processing, and an object of the present invention is to prevent overflow of musical tone data subjected to digital calculations.

For this purpose, a clip circuit is provided at the output of the digital filter 21 to relieve data overflow occurring within the digital filter. More specifically, a clip circuit is provided at the output of the adder circuit 21d.

[Conventional technology]

Conventionally, a musical tone signal generating device as shown in FIG. 2 has been devised. The operating principle of this musical tone signal generator is that RAM2
1 and a digital filter 21 (herein referred to as a low-pass filter), these two are connected in series to circulate musical tone signals and obtain a predetermined waveform. This idea is to first store musical sound data containing many harmonics in the RAM 20, and then gradually reduce the harmonic components using the digital filter 21, which is suitable for generating musical sounds from stringed instruments, etc. It is said that.

[Problem that the invention seeks to solve]

Here, the digital signal handled by the digital filter 21 is 1
If it does not have an accuracy of about 6 bits, the musical tone will be noisy, and the quality of the musical tone will depend largely on the number of bits of the digital data. If this is 16 bits, this 16 bit data needs to be multiplied and added within the digital filter. The multiplier circuits 21eL and 21h are 1
A 6-bit x 16-bit multiplication is performed and the result is extracted as 16-bit data. This is because the multipliers of the multiplier circuits 21α and 21b are treated as numbers below the decimal point,
Of the 32 bits of the result of 16 bits x 16 bits, the upper 16 bits are extracted. In other words, 32 bits are obtained as a result of a 16-bit x 16-bit operation, but treating only the upper 16 bits of these 32 bits as valid bits is inconsistent if we consider the multiplier of the multiplication circuit as a number below the decimal point. do not have.

Next, the outputs (16 bits) of each of the multiplier circuits 21α and 21h are added by the adder circuit 21Li, but 16 bits + 1
The addition of 6 pits results in 17 bits of digital data. This 17-bit digital data is stored in RAM2.
However, since the RAM 20 has only 16 bits in parallel, a contradiction in bit weighting occurs. In other words, the 16-bit digital data read from the RAM 20 becomes a 17-bit configuration by being operated on by the digital filter 21, and when it is written to the RAM 20 again, the least significant bit of the 17-bit data is cut off by 1 bit and discarded. must be written. This becomes a value obtained by dividing the data by 2, and the operation of the digital filter is no longer guaranteed.

[Means for solving problems]

In order to solve the above problems, the present invention provides a clip circuit at the output of the digital filter 21 as shown in FIG. 1, and attempts to relieve data overflow occurring within the digital filter. More specifically, a clip circuit is provided at the output of the adder circuit 21d.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. FIG. 1 shows a block diagram of the present invention, in which a digital filter 21
A clip circuit 22 is connected to the output side of the circuit.

Next, a detailed diagram of the vicinity of the clip circuit is shown in FIG.

Reference numeral 21d denotes an adder circuit, which is composed of a full adder, and 22 is a detailed diagram of a clip circuit. 22α and 22d are NOR circuits, 22b is a NAND circuit, and 22C is an AND circuit. 22e' to 422j are OR circuits, and 22k to 22p are exclusive OR circuits. xO to Xi5 are one input system of the adder circuit 21d, and YO
to Y15 - is the other input system.

The xO to X15 and YO to Y15 signals are digital data expressed as a catch of 2, and both x15 and Y15 are sign bits. In other words, there are two types of overflow in the adder circuit 21d: a negative value if level 1, and a positive value if level 0. In other words, this is the case of addition between negatives and addition between positives. The overflow occurs when both the Xδ value and the Y value are close to their maximum positive or negative values.

Table 1 shows the state of each bit when a positive overflow occurs.

When inputting large positive values for the values of X and Y in Table 1, SO~3
The sign bit of the addition result of 15 is negative (S15 = level 1)
Therefore, accurate calculation results cannot be obtained. At this time, the Noah circuit 22
Both the output of α and the 315 output of the adder circuit 21d are level 1.
Therefore, positive overflow detection appears in the output of the AND circuit 22C, and each gate of the OR circuits 22g to 22j and exclusive OR 22 to 22p is controlled, resulting in zO to shown in Table 1. It becomes the value of Z15. In other words, it is the maximum positive value.

Next, Table 2 shows an example of negative overflow.

When adding negative values, the result has a positive sign (S15=0)
Since this is inconvenient, it is forcibly set to the maximum negative value. Since this is an operation between negatives, the NAND circuit 22b and the NOR circuit 22d operate, and similarly to the positive over 70 time, the OR circuits 22g to 22j and the exclusive OR 22 to 22p are controlled. In the case of negative values, the exclusive OR 22 ~22p operates as an inverting element.

FIG. 4 illustrates the above operation as a musical sound waveform.

In Figure 4, X is a sine wave with a peak of 1.0, and Y
is a sine wave with a peak of 0.75.

The waveform 2 is the one obtained by adding the X waveform and Y waveform,
The shaded area is the overflowed area. In this overflow region, the sign and absolute value of the calculation result are not guaranteed at all, and digital signal processing cannot be performed.

The waveform No. 2 is the one provided with the clip circuit of the present invention.

〔Effect of the invention〕

As described above, the present invention can guarantee the operation of a system that obtains musical tones using digital signal processing technology or the like. In other words, in a system that circulates musical tone data, if an overflow occurs in the transmission path, not only will the calculated value itself not be guaranteed, but in the worst case scenario, the digital filter itself may oscillate. In particular, in systems such as all-pass filters, data is often circulated twice within the filter, making it very easy to oscillate. By using the present invention, it is possible to at least prevent filter oscillation, and in the event of an overflow, the musical sound data is clipped, so it can be handled equivalently to clipping of an analog waveform even though it is digitally processed, making subsequent countermeasures easier. Cheap.

[Brief explanation of drawings]

FIG. 1 is a block diagram according to the present invention, FIG. 2 is a conventional block diagram, FIG. 6 is a clip circuit according to the present invention, and FIG. 4 is a diagram showing the operation of the clip circuit according to the present invention. 20 ・・・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
...RAM21...Digital filter 22...Clip circuit 21α, 21h...Multiplication circuit 21C...Delay circuit 21d... ... Adder circuit or more

Claims (2)

[Claims] (1) Consisting of a memory that stores at least musical tone data and a digital filter that performs digital signal processing of musical sound waveforms, the output of the memory is connected to the input terminal of the digital filter, and the output of the digital filter is connected to the input of the memory. In the electronic circuit for an electronic musical instrument, the digital filter is composed of a digital multiplier circuit and a digital adder circuit, and the digital filter is configured to have a circular connection such that it is connected to the end of the circuit, and to obtain a musical tone signal from a predetermined position of the circular connection. The number of bits of the digital signal applied to the digital filter is the same before and after the calculation, and when the output value of the digital filter exceeds the value that can be expressed by the number of input bits of the digital filter, A miscalculation prevention circuit for an electronic circuit for an electronic musical instrument, characterized in that it operates a data clip circuit installed on the output side of a digital filter to prevent miscalculations (overflow) of musical tone data. (2) the musical tone data is a digital signal expressed in two's complement representation, and the output bits of the data clipping circuit are configured so as not to exceed the maximum value expressed within the number of input bits of the digital filter; The miscalculation prevention circuit for an electronic circuit for an electronic musical instrument according to claim 1, wherein the circuit is configured to output a maximum positive value when there is a positive overflow, and to output a maximum negative value when there is a negative overflow. .