JPS61160965A - Semiconductor ic device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a semiconductor integrated circuit device that integrates a high-performance MOS transistor and a high-speed bubble polar transistor.

2. Description of the Related Art A conventional semiconductor integrated circuit device in which a bipolar transistor and a MOS transistor are integrated is shown in FIG.

In the figure, 1 is the P-type substrate, 2 is the n-buried part of the bipolar transistor, 3 is the j1+ buried part of the MOS transistor, 4 is the n-well and the collector of the bipolar transistor, 5 is the n-well, and 6 is the isolated oxide. 7 is the p-type base of the bipolar transistor, 8 is the p-type base contact layer of the bipolar transistor, 9 is the p-region and the source of the MOS transistor, 10 is the p-region and M
The drain of the OS transistor, 11 is an n-region and a spaceconducting layer, 12 is an emitter in an n-region, 13 is a collector, 14 is an emitter, 16 is a base, 16 is a source electrode, 17 is a drain electrode, 18 is a gate oxide film, 19 is a gate electrode. In such a structure, since the gate electrode 18 and the source electrode 16 (or drain electrode 17) have a two-layer structure in the MOS transistor, the distance between the electrodes can be reduced. This reduces the size of the transistor and reduces parasitic capacitance. This will improve the performance of the transistor. On the other hand, since the base electrode 8 and emitter electrode 12 of the bibolar transistor have a single layer structure, it is necessary to provide a wide distance between the electrodes. This increases the base area and increases parasitic capacitance. This will significantly reduce the speed of the transistor.

Therefore, with such a conventional structure, it is difficult to integrate a high-performance MOS transistor and a high-speed bipolar transistor without mutually damaging the characteristics of both.

Problems to be Solved by the Invention Although the characteristics of the IMOS transistor in such a conventional semiconductor integrated circuit device are good, the speed of the bipolar transistor formed on the same substrate is not sufficiently high. In particular, it is necessary to increase the distance between the base electrode and emitter electrode of a bipolar transistor, which increases the base region, which impairs high speed performance due to an increase in base capacitance. The present invention has been made in view of the above, and provides a semiconductor integrated circuit device that can satisfactorily integrate a high-performance MOS transistor and a high-speed bipolar transistor with a simple configuration without impairing each other's performance. It is intended to.

Means for Solving the Problems In order to solve the above problems, the present invention has a gate electrode of a MOS transistor and an emitter electrode of a bipolar transistor formed in the same process.

and a source formed by providing an opening in an insulating film covering the gate electrode and the emitter electrode.

It is equipped with a drain electrode and a base electrode.

The emitter electrode and base electrode have a two-layer structure, and the gate electrode and source electrode (drain electrode) have a two-layer structure.

Effect of the present invention In accordance with the above structure, the distance between the emitter electrode and the base electrode of a bipolar transistor is shortened, and the distance between the base and base electrodes is reduced.
Reduce the capacitance between collectors.

Achieving high speed bipolar transistors while maintaining the high performance of MOS transistors.

Embodiment FIG. 1 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, 20 is a p-type substrate, and 21 is a calculation section of a MOS transistor.

22 is the n-buried portion of the bipolar transistor, and 23 is the n-buried portion of the bipolar transistor.
- well, 24 is an n-well and is the collector of a bipolar transistor, 25 is an isolation oxide film, and 26 is a hap region for MO
The source of the S transistor, 27 is the p region and the drain of the MOS transistor.

28 is the p-type base contact of the bipolar transistor, 29 is the p region and the source of the MOS transistor, 30
is the drain of the MOS transistor in the p region, 31 is the external base of the bipolar transistor in the p region, 32 is the internal base of the bipolar transistor in the p region, 33 is the emitter of the bipolar transistor in the n0 region, and 34 is the bipolar transistor in the n0 region. collector contact,
35 is a gate oxide film, 36 is a gate electrode, 3 is an emitter electrode, 38 is a glabella insulating film for multilayer, 39 is a source electrode, 40 is a fin 1-in electrode, 41 is a base electrode, 42 is a collector electrode, 43 is a It's a side wall.

In the structure shown in FIG. 1, the MOS transistor has a gate electrode 36 and a source electrode 39 (or drain electrode 4).
0) has a two-layer wt structure with an interlayer insulating film 38 in between, so the distance between the electrodes can be reduced. This reduces the size of the transistor, reduces parasitic capacitance, and improves transistor performance. In the bipolar transistor as well, since the emitter electrode 37 and the base electrode 41 have a two-layer structure with the interlayer insulating film 38 in between, the distance between the electrodes can be reduced. This reduces the base area of the transistor, reduces parasitic capacitance, and increases the speed of the transistor. The base electrode 41 and the source electrode 39 (or the drain electrode 40) are formed in the same process, and the gate electrode 36 and the emitter electrode 37 are formed in the same process.

As the material for the gate electrode 36 and the emitter electrode 37, polycrystalline Si, silicide, high melting point metal, etc. are used.

Next, a manufacturing process for realizing the structure of the semiconductor integrated circuit device will be explained based on FIGS. 2 to 9.

In FIG. 2, an oxide layer 25 is formed which separates the n-well regions 23,24. A gate oxide film 35 is formed in the n-well region 23. p-type impurity region a2. An n% impurity region 33 is formed.

Next, as shown in FIG. 3, after polycrystalline Si, silicide, or high melting point metal is deposited on the entire surface, the gate electrode 36. An emitter electrode 37 is formed.

Next, in FIG. 4, using the emitter electrode 37 as a mask, p-type impurity regions 32. By etching the n+ type impurity region 33, a p type active base region 32. n
Forming a ten-shaped emitter region 33 Next, as shown in FIG. 6, p-type impurities are implanted over the entire surface to form a low concentration source region 29. Drain region 30. A low concentration external base 31 is formed at the same time. At this time, directly under the gate electrode 36 and the emitter electrode 3
Implanting energy is set so that impurities do not enter directly under 7.

Next, in FIG. 6, a CvD SiO□ layer is formed on the entire surface.

Next, in FIG. 7, the gate electrode 3 is etched using anisotropic dry etching.
6. A side wall 43 is formed leaving only the side surface of the emitter electrode 37. The CVD5iO□ layer 43 over the source and drain regions 29, 30 and extrinsic base 31 is etched.

Next, in FIG. 8, p-type impurity ions are implanted into the entire surface of the p+ source 26. The external base 28 of the drain 27°p+ is formed at the same time.

Gate electrode 36. Side wall 43. Emitter electrode 3
The energy is set so that impurities from im-blanting do not enter directly under 7. The drain region 30 is a low concentration drain region and has a so-called L D D (light, t
This structure is effective in reducing hot electrons. Furthermore, the low concentration external base 28 is effective in improving the breakdown voltage between the emitter and the base.

Next, in FIG. 9, OV D Si0□ 38 is deposited on the entire surface. Next, source contact 44. Drain contact 45. Base contacts 46, 47 are drilled.

Finally, as shown in FIG. 1, the source electrode 39, the drain electrode 40. Base electrode 41. A collector electrode 42 is formed at the same time. In the steps shown in FIGS. 2 to 9, the n buried portion 22 of the bipolar transistor and the n ten buried portion 21 of the MOS transistor. Although the steps for forming the collector contact 34 of the bipolar transistor in the p-type substrate 20 and the n+ region are not shown.

It can be easily formed using conventional methods. The gate electrode 36 and the source and drain electrodes 39 and 40 have a two-layer structure,
The emitter electrode 3T and the base electrode 41 have a two-layer structure.

Effects of the Invention As described above, according to the present invention, it is possible to integrate a high-performance MOS transistor and a high-speed bipolar transistor with a simple structure without degrading each other's performance, which is extremely useful in practice. be.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIGS. 2 to 9 are cross-sectional views for explaining the manufacturing process of the semiconductor integrated circuit device, and FIG. 10 is a conventional semiconductor integrated circuit device. FIG. 1 is a cross-sectional view showing an integrated circuit device. 36...Gate electrode, 37...Emitter electrode. 38...Multilayer glabella insulating film, 39...
・Source electrode, 40...Drain electrode, 41・
...Base electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3t---p Hide ■ sail, ttri A7-ra 211p
Person 4j-74 Dorashia-IL Figure 2 Factor 10

Claims (1)

[Claims] A gate electrode of a MOS transistor, an emitter electrode of a bipolar transistor formed in the same process, an insulating film covering the gate electrode and the emitter electrode, and a source and drain electrode formed by opening the insulating film, respectively. A semiconductor integrated circuit device comprising a base electrode.