JPS61160168A - Priority discriminating device - Google Patents

Abstract

PURPOSE:To omit the replacement of a circuit element such as an IC at the change of priority, to simplify the circuit constitution of a device and to reduce current consumption by forming a priority changing means constituted of a read-only-memory (ROM) having a changing table. CONSTITUTION:The priority changing means for changing the priority of signals inputted to plural input terminals is constituted of the ROM having the changing table. Namely, the priority changing means is constituted of a ROM26, a priority output code is latched by an output from a shift register 21 which is a latch timing determining part, the output of a bus driver 32 is enabled and the priority output code is outputted to the outside. Then the output of the bus driver 23 is disabled by the differential input of a BUS BUSY signal and the succeeding latch is executed. Thus, said sequence is repeated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a priority determination device that selects and outputs signals input to a plurality of input terminals based on the priority order, and particularly relates to a priority determination device that selects and outputs signals input to a plurality of input terminals based on the priority order. The present invention relates to a circuit configuration of a priority order changing means for changing the priority order.

[Conventional technology]

2. Description of the Related Art Conventionally, a priority order determination device is known that selects and outputs signals input to a plurality of input terminals based on priority order.

FIG. 6 shows a CPU bus arbitration circuit in a conventional multi-CPU configuration. In the figure, 1 is a priority encoder having a plurality of input terminals (8 input terminals in the drawing), 2 is a decoder as a discriminating means for decoding the output of the priority encoder 1, and 3 is an input signal from an OR gate 4. A flip-flop latches the signal, and 5 is a shift register, which outputs H or L level signals to QO to Q3 based on the inverted output of σ1 of the priority encoder 1 inverted by the inverter 6 and the clock CL input from the AND gate 7. . 8 is an AND gate, and the 8g AND gate 8 ANDs the GS output of the priority encoder 1 and the clock CL and inputs the result to the OR gate 4. The other input of the OR gate 4 is the output of the Q2 terminal of the shift register 5. 9 is a three-man NAND gate that outputs the QO terminal output of the shift register 5, the inverted output of the Ql terminal inverted by the inverter IO, and NAND.
The output from gate 11 is input, and the output is input to AND gate 7. The other input of the AND gate 7 is the clock CL inverted by the inverter 12. On the other hand, the input of the NAND gate 13 is connected to the inverter 14
The inverted output of the Q2 terminal of the shift register 5 and the output of the QO terminal are connected to the GS input terminal of the decoder 2.

Further, the inverted output of the 03 terminal of the shift register 5, which has been inverted by the inverter 15, is input to the AND gate 16,
A RESET signal is input to the other input of the AND gate 16. The output of the AND gate 16 is input to the reset terminal of the shift register 5.

In addition, the flip-flop 17 has a data input terminal connected to the BUS
Input the BUSY signal, input the non-inverted output of the flip-flop 17 to the data input terminal of the flip-flop 18, and input the inverted output of the flip-flop 18 and the non-inverted output of the flip-flop 17 to the NAND gate 11. The output is input to the three-man powered NAND gate 9.

Next, the effect will be explained. First, as shown in the figure, a request signal S for each CPU to acquire bus control right is input. Then, the flip-flop 3 latches the request signal S at the rising edge of the clock CL. However, in this case, if there is no input (hereinafter this state will be considered as meaningless)
The output of priority encoder 1 becomes H (high level). On the other hand, the clock CL and the above GS output are A
Both are input to the ND gate 8, and the AND gate 8
Since the above σ3 output is H, the output of the clock CL
It is connected to the clock input terminal of the flip-flop 3 through the OR gate 4, and latches the human input signal at the rising edge of the clock CL. The input signal is 1 during this cycle.
This process is repeated until at least one exists (hereinafter, this state is considered to be input significant).

When the input becomes significant, the output becomes L (low level) and the output of the AND gate 8 becomes L. On the other hand, the OR gate 4 receives the output of the AND gate 8 and the shift register 5.
The Q2 terminal output of is input.

Since the shift register 5 has been reset in advance, the Q2 terminal output is L, and when the small output of the AND gate 8 becomes L, the output of the OR gate 4 becomes L, and the clock input terminal of the flip-flop 3 becomes L. L is input to , no launch is performed, and the previously latched value is held.

On the other hand, if the input is valid, the GS output is L, so it becomes H after passing through the inverter 6, and the DSI of the shift register 5
, DS2 terminals are both input with H level.

By the way, BUSBtJSY (No. 8) is set to L (active) when each processor connected to the system bus is given bus control authority, and set to H (inactive) when a command (memory read, write, etc.) is completed. This BUSBUSY signal is connected to the data input terminal of the flip-flop 17, but the flip-flops 17 and 18 and the NAND gate 11 constitute a differentiating circuit 19, and normally the output of the differentiating circuit (specifically Generally NA
ND gate 11 output) is H, and BLJSBUSY
The time when the signal changes from L (active) to H (inactive) is used as a trigger to output L level for one clock CL.

By the way, the human power input to the three-manpower NAND gate 9 is three: the output of the above-mentioned differentiating circuit 19, the QO output of the shift register 5, and the Q1 output through the inverter 10.

Output of the above differentiation circuit 19 (output of NAND gate 11)
is normally H, and since the shift register 5 has been reset, the QO terminal is output.On the other hand, the Q1 terminal output is inverted by the inverter 10 and becomes H, and the three-man power NAND gate 9 becomes H, and the input to AND gate 7 becomes H. The other input to the AND gate 7 is the clock CL, and the output of the AND gate 7 is the clock CL itself.

Therefore, the shift register 5 is input to the shift register CL, but if the input is significant as described above, DSL, DS2
Since H is input to both terminals, the QO terminal becomes H in synchronization with the rise of the clock CL. As a result, 3 manpower N
All the inputs of the AND gate 9 become H, the input to the AND gate 7 becomes L, and the shift register 5^ and clock CL are no longer input. At the same time, NAND gate 1
3, H is input from the QO terminal, and on the other hand, the Q2 terminal output remains in the reset state, so it is output and inverted by the inverter 14, and H is input, so NAND The output of the gate 13 becomes L, the mouth of the decoder 2 becomes L, the decoder 2 becomes output enabled, and the determination result P is output.

Note that at the time when the shift register 5 is being reset, the output of the NAND gate 13 becomes H, and the output of the decoder 2 is disabled.

CPU given pass priority based on judgment result
sets the BUSBUSY signal to L (active), and after the command (memory read, write) is completed, sets it to H (inactive).

Using the timing when the BUSBUSY signal rises from L to H as a trigger, flip-flop 17.18° and NAND
The output from the differentiating circuit 19 composed of the gate 11 is set to L for one clock CL, and the output of the three-man power NAND gate 9, that is, the input to the AND gate 7 is set to H.

Therefore, the clock CL can be input to the shift register 5, and the Q1 terminal output becomes H at the rising edge of the clock CL.
The input to the three-man power NAND gate 9 through the inverter 10 becomes L, and thereafter the output of the NAND gate 9, that is, the input of the AND gate 7 becomes H. Therefore, the clock CL can be input to the shift register 5, and the next clock C
At L, the Q2 terminal output changes from L to H, the output of the OR gate 4 changes from L to H, and the flip-flop 3 latches the next input signal at the rising edge from L to H.

At the same time, the Q2 terminal output is inverted by the inverter 14, so it is input to the NAND gate 13. On the other hand, since the input from the QO terminal is H, the output of the NAND gate 13, that is, the 61 terminal of the decoder 2 is The signal becomes H, and the decoder 2 becomes output disabled. Furthermore, the Q3 terminal becomes H at the next clock CL, is inverted by the inverter 15, becomes L, and is input to the AND gate 16, and the other input R
Since the ESET signal is normally H, the output of the AND gate 16 becomes L and is input to the reset terminal, and the shift register 5 is reset.

Note that the RESET signal lasts for a certain period only when the power is turned on, but is normally H, and while the Q3 terminal output is L, the AN
The output of the D game) 16 becomes H, and the shift register 5 is not reset.

The next input signal is latched, and if the input is significant, the above sequence is performed; if the input is insignificant, the σ] output of the priority encoder 1 becomes H, so the clock CL is output from the AND gate 8, and the flip-flop 3 repeats the latch until the input becomes significant. The reason why the clock CL to the shift register 5 is inverted by the inverter 12 will be explained below.

The differentiating circuit 19 and the shift register 5 are both connected to the clock CL.
It latches at the rising edge of . Therefore, since the clock CL to the shift register 5 is inverted by the inverter 12, the clock CL to the differentiation circuit 19 is shifted by half a clock CL.

On the other hand, the differentiating circuit 1 that detected the rising edge of the BUSBUSY signal
9 outputs L of 1 clock CL width, resulting in NAND
The clock CL can be input to the shift register 5 only for the time when the input to the gate 7 is one clock CLO width H, but since it is shifted by half a clock CL, latching is performed reliably.

[Problem that the invention seeks to solve]

By the way, the conventional CP configured as described above
In the circuit that implements the bus arbitration method between U, there is only one priority encoder 1, so the priority of the CPU is determined by the way the signal line is connected to the connection terminal of the priority encoder 1. It is determined. Therefore, for example, when adopting a rotation priority control method that converts the priority order based on the previous judgment result, multiple priority encoders L that convert the priority order of the CPU are required, and other ICs are also required, making the circuit complicated. There was a problem with this.

Accordingly, an object of the present invention is to provide a priority order determination device that allows changes in priority order without replacing circuit components.

[Means for solving problems]

The present invention is equipped with a priority order changing means constituted by a read-only memory having a change table.

[Effect]

The read-only memory of the priority order changing means changes the priority order of the signal input to the input terminal based on the change table.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 5. Note that the same components as those in the prior art are given the same reference numerals, and the description thereof will be omitted.

However, 21 is a shift register according to the present invention, in which the conventional QO-Q3 terminal is shifted to Q1 to Q4 terminals in the present invention, and the QO terminal output is input to the clock input terminal of the flip-flop 22. are doing.

Further, the output of the NAND gate 13 is input to the terminal of the bus driver 23 at σ. A bus receiver 24 receives input signals from the outside and outputs signals to the internal circuit. The outputs of the flip-flops 3 and 25 determine the address of a read-only memory (hereinafter referred to as ROM) 26. The output 0ONO2 of the ROM 26 is latched by the flip-flop 22, and the output is input to the decoder 2. The output of is input to the bus driver 23. 27 is a timer, the output of the OR gate 4 is input to the B terminal, the output Q is input to the data input terminal of the flip-flop 28, and the non-inverted output of the flip-flop 28 and the clock CL are input to the AND gate 29. , the output is A
It is input to the ND gate 8 and the inverter 12. Above R
The OM 26 constitutes a priority order changing means.

FIG. 1 shows a circuit diagram of an embodiment of the present invention, and FIG. 2 shows a block diagram of FIG. 1. The details will be described later, but only an outline will be given here. The request signal S is latched by the flip-flop 3 serving as an input signal launch section, and simultaneously by the flip-flop 25 serving as the next segment latch section. Flip-flop 3 as these latch parts
．． The timer 27 stops the input of the clock CL to the shift register 2/ as a latch timing determining section for a certain period of time for the delay time from when the output of the ROM 25 is input to the address input terminal of the ROM 26 until it is output.
Wait for output from 6. The timer 27 is stopped at the timing when the content from the ROM 26 is thought to have been output, and the shift register 21 as the latch timing determining section
It is possible to input clock CL to Thereafter, the priority output code is latched by the output from the shift register 1 serving as the latch timing determination section, and the bus driver 23 is enabled for output, and the priority output code is output to the outside. Then, the bus driver 23 is output disabled by differential input of the BUSBUSY signal, and the next latching is performed, and the sequence is repeated.

Next, the circuit diagram shown in FIG. 1 will be explained in detail. R
An example of the contents of the table of OM26 is shown in FIG. R.O.
The table M26 is divided into 8 segments (one segment has 256 addresses) according to the 3-bit address input from A8 to AIO. The address input of A O-A 7 is the input of the request signal S, and depending on that input and the segment selected in advance, the current judgment result is set to 00.
Output to ~02, and select next segment to 03~
At 05, a bit indicating whether there is even one input signal (hereinafter, this state will be regarded as input significant) is output at 06.

In each segment, the function is the same as that of the prior art priority encoder, and the judgment results are outputted in 3-bit codes from 00 to 02 for AO to A7 manually. Then, an operation is performed to virtually change the connection method of the AO to A7 manual signal lines to the priority encoder using the segments, and the determination results are output to 00 to 02. The priority order for each segment is shown in a table 30 shown in FIG. In this embodiment, the value obtained by adding 1 to the current determination result is set as the segment to be selected next time. Note that the request signal line 5o-37 is the same as that shown in FIG. Further, the actual table 31 is created using the example shown in FIG. In addition, in FIG. 3, 5O-37 indicates a request signal.

Further, in the figure, PO-P7 indicates a segment.

Now, referring to FIG. 1, the operation will be explained. R when power is turned on
The ESET signal causes flip-flop 3, 17.
18. 25. 28. Timer 27. Shift register 5 is reset. As a result, the flip-flop 17
．． The output of the differentiating circuit 19 (output of the NAND gate 11) consisting of 18 and the NAND gate 11 is at H level, the Q terminal output of the timer 27 is high, the non-inverting output of the flip-flop 28 is low, and each terminal of the shift register 4 is at high level. The signal becomes L, and the input from the Q3 terminal to the OR gate 4 becomes L. Further, the output of the NAND gate 13 becomes H, and the bus driver 23 becomes output disabled.

Now, after reset, the outputs of flip-flops 3 and 25 become L, the address inputs of AO to AIO become L, and the fourth
From the figure, the 03 to 05 terminal outputs are O (3-bit code), 0
H is output from the 6th terminal. Therefore, the clock CL can be input to the clock input terminals of the flip-flops 3 and 25, and the flip-flop 3 can input the request signal S and
The flip-flop 25 latches the outputs of terminals 03 to 05 of the ROM 26, respectively. The timer 27 has a clock C
The rising edge of L is used as a trigger to set the Q terminal to H.

Then, the inverted output of the flip-flop 28 becomes L, and A
The output of the ND gate 29 becomes L, and the clock CL is no longer output. On the other hand, the duration of the high level of the Q terminal output of the timer 27 is determined by the external resistor and capacitor of the timer 27, but it is determined that the high level is maintained for a slightly longer time than the output delay time after address input. put.

Also, when the Q terminal output of the timer 27 becomes L, the inverted output of the flip-flop 28 becomes H, and the AND gate 29
Clock CL can be output from 0 of ROM26.
If the output from terminal 6 is H, the table 31 in FIG. 4 indicates that there is no input (a state in which there is no input signal), the clock CL is output from the AND gate 8, and the flip-flop 3°25 is activated as described above. Repeat the latch until the input becomes significant.

Furthermore, when the output from the 06 terminal of the ROM 26 becomes L, the input is significant as shown in FIG. 2, and the clock CL is not output from the AND gate 8, but the latched value is held. At the same time, both the DS1 and DS2 terminals of the shift register 2t become H, and the rising edge of the clock CL is used as a trigger to drive the QO terminal to L.
to H, and the flip-flop 22 latches the current determination result output from the ROM 26 and outputs it to the decoder 2.

Further, with the next clock CL, the Q1 terminal is set to H, the output of the NAND gate 13 is set to L, the bus driver 23 is enabled for output, and the output of the decoder 2, which is the current determination result, is output to the external signal line. The subsequent operations are exactly the same as those of the prior art. With the rise of the BUSBUSY signal, the clock CL can be input to the shift register 1, the output of the NAND gate 13 becomes H, the bus driver 23 becomes output disabled, and at the same time, the flip-flops 3 and 25 perform latching. If the input is invalid, latching is performed until the input becomes significant, and if the input is significant manually, the above sequence is repeated.

Note that FIG. 5 shows a timing chart based on the outputs of the main terminals. Note that (a) is the output of the clock CL, (b) is the output of the OR gate 4, (c) is the request input signal S latched by the flip-flop 3, (d) is the segment selection signal launched by the flip-flop 23, (
E) is the impedance of the 06 terminal of ROM26, (E)
is the inverted output of the flip-flop 28, (G) is the output of the QO terminal of the shift register 5, (J) is the output code latched by the flip-flop 22, (W) is the output of the NAND gate 13, (NU) is the shift register (R) is the output of the Q4 terminal of shift register 5, (W) is the BUSBUSY signal, (W) is the NAND gate 11.
The output of each is shown.

In the above embodiment, there are eight request input signals S,
A ROM with a memory space of 2nd word x 7 bits was sufficient as a priority conversion table, but in general, when there are 2n requested input signals, a memory space of 2 (in + nl words x (2n + 1) bits) is required. If a ROM with
If there are six, a ROM having a virtual memory space of 220 words x 9 bits may be used.

〔effect〕

As explained above, according to the present invention, the priority order changing means for changing the priority order of signals input to a plurality of input terminals is constituted by a read-only memory equipped with a change table. There is no need to replace circuit elements such as , IC, etc., so the circuit becomes simple and consumes less current.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram according to an embodiment of the present invention, and FIG. 2 is a circuit diagram according to an embodiment of the present invention.
FIG. 3, which is a block diagram of FIG. 1, is a diagram showing the priorities of the first to eighth signal lines in each of the eight segments of the ROM shown in FIG. FIG. 4 is a diagram showing a table of one segment out of which the ROM table of FIG. 1 is divided into eight segments. FIG. 5 is a timing chart showing the output timing of the main terminals of the circuit shown in FIG. 1, and FIG. 6 is a circuit diagram showing the prior art. 2... Discrimination means (decoder), 21... Shift register, 26... Priority change means (ROM). Agent Masuo Oiwa (2 idiots) Figure 5

Claims (1)

[Claims] Determines the priority of signals input to multiple input terminals,
A priority order determining device comprising a determining means for selecting and outputting the signal based on the priority order, wherein the priority order changing means changes the priority order based on the previous determination result of the determining means. A priority determination device characterized in that it is constructed of a read-only memory having a table.