JPS61156987A - digital disc playback device - Google Patents

Abstract

PURPOSE:To lower a processing operation and heighten a processing speed by providing a simple hardware of an arithmetic circuit and a temporarily storing latch circuit between a central processing unit and a video memory. CONSTITUTION:In case of scrolling a data of (i, j) address on a screen shown in the figure (A), the address (i, j) of a video RAM209 is addressed from a CPU205, a data of the address (i, j) is read and temporarily stored in a latch circuit 221. A data given to an exclusive OR circuit 208 from the CPU205 is made '0'. When a switch 220 is turned from off to on, the exclusive OR circuit 208 operates as a buffer circuit. At this time, by the CPU205 a writing address of the video RAM209 is designated as (i, j+1). Thereby, a content of a latch circuit 221 is written in the address (i, j+1), and a display device is also moved to the address of (i, j+1) as shown in the figure (B). Accordingly, in this case, a right scrolling is done.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital disc playback device that plays back subcodes of, for example, an optical compact disc, and particularly aims to improve the screen clearing function.

[Technical background of the invention]

In the field of audio equipment, a digital recording and reproducing system using PCM technology has been adopted in order to achieve high fidelity reproduction and excellent operability.

This food playback device is required to have a variety of advanced control functions and performance that are not found in conventional analog recording and playback systems. This is an optical compact disc system.To explain it to you, the disc contains the reproduced music signal for stereo playback, as well as sub-codes to improve operability and realize all advanced functions. .

The subcode data is subcode P, subcode Q, and subcode R for each frame.

... Consists of 8-bit data called subcode W. Among these, subcode R-W (consisting of 6 bits per frame) is different from subcodes P and Q, and is synchronized with the reproduced music signal, for example, on a television 17.
It is used as data to display the entire image on the screen.

The data of this subcode (R-W) is roughly divided into 1 unit of display image data or image operation commands such as scrolling the screen, which will be described later, and each data is 24X6=14
Consists of 4 bits.

The unit of this data is called a block, and its structure is set as shown in FIG.

The second figure shows subcodes (R-W) t' in the horizontal direction, and 24 lines of this data in the vertical direction. Shinbiru 0
is mode/item data and specifies a display screen mode, which will be described later.

Simple 1 is instruction data indicating the type of image display data and image manipulation command.

Symbols 4 to 19 are data for each instruction. Note that symbols 2 to 3. 20 to 23 are 'fi:, /4' lity data generated by Reed-Solomon code,
The playback device uses this to perform data error determination, error correction, and the like.

The surface modes specified by Symbill O include Television Graphics Mode (TV Mode), Line Gela Fix Mode (LINE Sodo), and Zero Mode (
ZERO mode) and user mode.

The TV mode is a mode assumed for a display device such as an all-cathode ray tube display in which one screen is composed of 288 x 192 pixels. LINE mode is 288
This mode is intended for all simple display devices, such as liquid crystal displays, in which one screen is composed of 24 x 24 dots of pixels.

Figure 1 and Figure 1D are LINE mode)', TV-T-
-) shows an assumed memory configuration diagram. One screen is 6
A fine molecule is hit in an area of ×12 dots t-1,
This unit area is called a font.

Therefore, TV mode is 48x16 font, LINE
The mode is set as 48x2 font as one screen, but since hidden memory for scrolling is added, 50x1 font is set as one screen.
8 fonts, 49 x 4 fonts, are secured. The above-mentioned display pixel data in units of 1 pack is data in units of 1 font, and data areas of simple 8 to 19 (6X
Each pixel data in the font is stored in 12 bits).

TV Momo allows you to select 16 colors out of 4,096 colors to display on the screen using a pre-specified color palette, making it possible to display a vivid screen with subtle expressions such as intermediate colors and complex color changes. (8 colors in LINE mode). Among display screen modes, ZERO mode is a NOP (No
This ZERO mode data is recorded in all the subcode R-W data of the disc which is in the (non-operation) mode and does not record an image.

Pack data in TV mode and IJNE mode includes:
In addition to the image display data described above, there are image manipulation commands. The type of command is represented by the instruction data of Symbill 1, and commands include scroll commands for the entire screen (commands that move the entire screen left and right or up and down), scroll commands for only a specific row or column, and commands that move the entire screen in one color. In addition to the preset memory command, which fills in the area with a color, there is an exclusive or command, which overpaints the displayed color and creates a multicolored screen.By combining these commands, various effective effects can be created. You can configure the screen. Is the user mode Con A for business use? This mode allows the user of the disc player to freely determine the instructions and data.

[Problems with background technology]

In the conventional audio digital disc playback device described above, the image storage circuit 102 is electrically connected to a central processing circuit (hereinafter referred to as CPU) 100, as shown in FIG. 11, and stores various data. can be processed. In this case, the mutual signals are given directionality in the data transfer direction by the direction switch 101. In this case, the input and output terminals of the memory circuit 1020 are the same, but if the input and output terminals are separate as shown in FIG. 12, the directionality of the signal is switched by switching the switch 103. The above data processing requires a CPU of 100 t.
- performed by operating software;

By the way, when scrolling is performed on the display screen of a display device, the data in the memory circuit 102 is once read out, and then written at a different address. Tsut
, b. The CPU 100 specifies an arbitrary address in the memory circuit 102, reads the data therein, and then changes the address and writes the data there again in sequence. Such processing requires switching the data signal transfer direction and bidirectional data transfer, which takes a lot of time for software processing and makes it difficult to increase the scrolling speed. Also, the storage circuit 102 Exclusive OR processing may be applied to the data in the file and then written again. In such a case, the software performs arithmetic processing on the data transferred to the CPU 100 and then returns the data to the same location, but the arithmetic processing time is added.

This process is called an exclusive-or operation that is performed when one screen is displayed with overlapping colors.
Since this is performed by software on the CPU J00 side as described above, this is an obstacle to increasing the overall speed of image processing.

[Purpose of the invention]

The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide a digital disc playback device that can speed up address changes and arithmetic changes of data contents for image data in a video memory.

[Summary of the invention]

This invention, for example, as shown in FIGS. 1 and 2,
An arithmetic circuit 20B, for example, an exclusive OR circuit 201111C between the U 205 and the video RAM 209.
By providing simple hardware such as the latch circuit 221 and the latch circuit 221, the above object can be achieved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment in which the present invention is fully applied to an optical compact disc player. The subcodes (R to W) reproduced from the compact disc are input to the deinterleave circuit 202 via the input interface 201f, and the data arrangement thereof is rearranged into the correct order.

The output with the data array returned to normal is sent to the error correction circuit 2.
Error determination and error correction processing are performed using the parity data input to 03 and generated by the Reed-Don-Romon code. The error-corrected subcode R-W is
It is input to a central processing unit (hereinafter referred to as CPU) 205 via an input/output interface 204 and is decoded. The CPU 205 reads the subcodes R to Wi, decodes the mode/item data, and displays the display screen mode P (TV
mode, LINE mode 1', ZER mode, user mode).

CPU j 0 g has mode/item data of TV
mode or LINE mode, the instruction data is checked and the type of image display data and image manipulation command is determined. The program read only memory (hereinafter referred to as P-ROM) 207 includes CPo
A fixed program for controlling the 205 is stored in random access memory (RAM).
Data necessary for the program is stored in 206.

Next, the 7-o/to data consisting of numbers 8 to 19 is converted to a single number (0 to 15) and then sent to the video RAM 209 via the exclusive OR circuit 208 and the switch 220t. written. Video RAM 30
The 9K written data of the first color number is read out in synchronization with the television signal and input to a color lookup table memory (hereinafter referred to as CLUT RAM) 210. Color lookup table (CLUT)
has a rich color palette, 16 out of 4096 colors
The selected color is registered in the form of a number (0 to 15). Therefore, the data of the first color read from the video RAM 209 is stored in the CLUT RAM 2101/
C is compared with the stored R, G, and B color data, and this color data is input to a digital-to-analog conversion circuit 211 and converted into R, G, and B color signals including a luminance signal. The color signal is input to the television monitor device 212 and displayed. In the CLUT RAM 2JO, color lookup table data is stored in advance at a predetermined address from the CPU 205 side via the interface 204.

The video mausoleum control circuit 213 is a video RAM
209 address control, write or read selection, etc. When the control circuit 213 performs write control, the video RAM 20g is
205 side and perform read control, the video RAM 209 is synchronized with the television monitor device 21.
The two sides can be synchronized. Therefore, the control circuit 21
3, from CPU 205 to interface 2
Control notes are inputted through the readout controller 214, which generates synchronization signals (horizontal and vertical synchronization signals) for the monitor device 212, as well as a timing signal.

By the way, in this invention, in order to perform high-speed scrolling, a means for changing the address position of data in the video RAM 209, and a means for changing the address position of data in the video RAM 209, and a means for changing the address position of data in the video RAM 209, and a means for changing the address position of data in the video RAM 209, and a means for changing the address position of data in the video RAM 209, and
The feature lies in the means for performing calculations on the AM 209 data.

These functions can be achieved by using the exclusive OR circuit 208 and the latch circuit 221.

Now, CPU 205, exclusive circuit 22)
, switch 220, and video RAM 209 will be extracted and explained with reference to FIG. FIG. 2B shows another embodiment in which the input and output terminals of the sb and the video RAM 209/ are independent; in this case, the switch 220 is not necessary.

To explain the configuration of the prisoner in Figure 2 as a representative example, the video RAM
When data is written to 209, switch 220
is turned on, and the output of exclusive OR circuit 20g is input to video RAM 209. Video RA
For normal data writing to M209K,
Data O is input from the CPU 205, and the exclusive/OR circuit 208 is operated as a mere buffer 7 circuit.

[When scrolling]

Now, a case will be described in which the data at address (1, j) on the screen 300 shown in FIGS. 3(A)K is scrolled. First, the address (i, j) of the video RAM 209 is C
Addressed by PU 205, its address (1
, j) is read out and temporarily stored in the latch circuit 221. Next, when the data given from the CPU 205 to the exclusive OR circuit 20g is set to 0 and the switch 220t is turned on from off, the exclusive OR circuit 208 functions as a buffer circuit.

Also, at this time, the CPU 205 controls the video RAM.
The write address of 209 is specified as (1,j+1). As a result, the contents of the latch circuit 221 are written to the address (t, j+1), and the display position is also changed to ω) in FIG.
The IC is moved to the address (t, j+1) as shown. Therefore, in this case, scrolling is performed to the right. In the case of left scrolling, data can be written by changing the address to (1, j-1) in the same way. In the case of upward scrolling, there is data at address (x, j) on the screen 300 in FIG. 4 (4), and the data is 7'2. #i), read this data and temporarily store it in the latch circuit 22, and then write the latch contents to the video RAM j 09 by specifying the write address 't-(1-1, J)VC. 4. As shown in FIG. 4 (B), the display data moves to the address of the button (1-x, j). In the case of downward scrolling, you can change the address to (1+1.1) and write in the same way.

The timing chart for the scrolling operation described above is as follows.
The result will be as shown in the figure. That is, the address (i, j
)', the contents of that address are latched in the latch circuit 221 at timing ■, and the contents of the address are latched in the latch circuit 221 at timing ■.
Change all lines to the next address ■, and write the latch contents at timing ■. Time point ■ is the end of scrolling.

[Exclusive OR operation]

“According to the standards for optical connoisseur disc players, the exclusive or command is used to specify the color (C0L
OR) r OJ and color (C0LOR) r I
J performs an exclusive OR operation. C0LORr OJ in Figure 6 is the font data (symbil 8~
19) C0LORr I J
is the color number that is exclusively ORed with the color number of the pixel having the value "1" in the 7-ont data.

ROW, COLUMN given in Simple 6.7
is the 7-ont address to which this instruction is executed.

Furthermore, CHrOJ and CHrlJ are channel numbers and have values from 0 to 15.

'77Nk6.7 given 7'j ROW, CO
An address in the video RAM 209 is specified using the data in LUMN, and the data at this address is read out, latched in the latch circuit 221, and temporarily stored. Next, a color number from the new font data to be subjected to the exclusive OR operation is outputted through the entire CPU 205 and inputted to the exclusive OR circuit 208. As a result, the empty number from the latch circuit 221 and the new friend's empty number are exclusive ORed and inputted to the video RAM 209K via the switch 220t. Therefore, the data at the above address is replaced by an exclusive OR operation K
Complete the exclusive or operation.

The timing chart of the above operation is as shown in FIG. 7. When address (2) is specified, font data (2) at that address is read out and latched at timing (2). Upon latching, an exclusive logic operation is obtained at time point (2), and then the video RAM 209 is written at time point (2). Therefore, the font data (2) subjected to the exclusive OR operation is written to the video RAM 209.

In the above description, the arithmetic processing circuit is an exclusive OR circuit, but depending on the purpose, it may be replaced with an AND circuit or an OR circuit to obtain desired data (color change data).

As described above, this device can temporarily read data at an arbitrary address in the video RAM 209 to the latch circuit, and write it into the video RAM j 09 again. In this case, scrolling can be achieved by changing the write address, and if the arithmetic circuit is provided with an arithmetic function, exclusive OR processing can be performed, for example.

In the case of an exclusive OR circuit, for example, if the output of the latch circuit 221 is forcibly set to "0" from the outside, it operates as a mere buffer circuit and can be used as a normal write data transmission path for the video RAM 209.

〔Effect of the invention〕

As explained above, according to the present invention, a latch circuit for temporary storage is provided between the central processing unit and the video memory.
By providing a simple hardware arithmetic circuit, processing operations by software can be significantly reduced and processing speed can be improved. Furthermore, completely different processes such as screen scrolling and exclusive-or operations can be selectively executed.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, and FIG. 2G(A) is a configuration explanatory diagram showing a part of FIG. 1. FIG. 2 CB) is a configuration explanatory diagram showing another embodiment of the same FIG. 5 is a timing explanatory diagram for explaining the scrolling operation of the device of FIG. 1, FIG. 6 is an explanatory diagram showing an example of the structure of data used in the device of this invention, and FIG. 7 is an explanatory diagram of the scrolling operation of the device of FIG. FIG. 9 is a timing explanatory diagram for explaining the exclusive OR operation of the device. Figures 8, 9, and 10 are explanatory diagrams showing examples of data configurations used in optical compact disc players, respectively, and Figures 11 and 12 are diagrams showing central processing units in conventional digital disc playback systems, respectively. FIG. 3 is a diagram showing a connection configuration tube of a memory circuit. 204... Interface, 205... Central processing unit (CPU), 2 ([... Exclusive OR circuit, 209... Video memory, 220... Switch, 221... Latch circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 2 (A) (B) Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 6 dots 10 Figure 12

Claims (1)

[Scope of Claims] A disc in which image data and data to be reproduced including image manipulation instructions are digitized is played back, the image manipulation instructions are decoded by a central processing unit, and the image data is once converted into video data. A digital disc playback device that inputs and stores image data in a memory and displays an image of the image data on a display by reading the data, comprising: a multi-input logic circuit to which the output of the central processing unit is input; a latch circuit for latching read data of and inputting the latched data to the logic circuit; and means for inputting an output of the logic circuit to a write input terminal of the video memory; A digital disc playback device, characterized in that it is configured to perform scrolling or data arithmetic processing in response to switching of the arithmetic mode of the logic circuit and address control of the video memory.