JPS61156865A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61156865A JPS61156865A JP59277448A JP27744884A JPS61156865A JP S61156865 A JPS61156865 A JP S61156865A JP 59277448 A JP59277448 A JP 59277448A JP 27744884 A JP27744884 A JP 27744884A JP S61156865 A JPS61156865 A JP S61156865A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- tantalum
- compound
- capacitor
- oxygen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 21
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 20
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000001301 oxygen Substances 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 7
- 150000001875 compounds Chemical class 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 10
- 150000003482 tantalum compounds Chemical class 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- -1 tantalum- aluminum-oxygen Chemical compound 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 5
- 229910001936 tantalum oxide Inorganic materials 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 241001648319 Toronia toru Species 0.000 description 1
- BROYGXJPKIABKM-UHFFFAOYSA-N [Ta].[Au] Chemical compound [Ta].[Au] BROYGXJPKIABKM-UHFFFAOYSA-N 0.000 description 1
- 229910052789 astatine Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
- Physical Vapour Deposition (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体装置を構成する
容量の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to the structure of a capacitor that constitutes a semiconductor device.
ダイナミックＲＡ Ｍ （Ｒａｎｄｏｍ Ａｃｃｅｓｓ
Ｍｅｍｏｒｙ）等の構成要素として容量全具備した半
導体装置においては、チップ中に占める容量の面積が大
きく、そのため上記半導体装置の小屋化の妨げとなって
いる。従って容量の面積ｔ″）極力小さくすることが上
記半導体装置の高密度化を計る上で重要である。Dynamic RAM (Random Access
In a semiconductor device that has a full capacity as a component such as a memory, the area occupied by the capacity in the chip is large, which is an obstacle to making the semiconductor device small. Therefore, it is important to minimize the area t'' of the capacitor in order to increase the density of the semiconductor device.
容量の占める面積を小さく、かつ大きな容量値を得るた
めに、従来、誘電材料としての誘電率の大きなタンタル
の酸化物を用いた構造が試みらｎている。第６図はタン
タル酸化物を誘電体として形成した容量の一例の断面図
であり、単結晶シリコン又は多結晶シリコン層１の上に
タンタル酸化物の誘電体層２ｔ−介して多結晶シリコン
層３ｔ−形、成し容量を構成していた。In order to reduce the area occupied by the capacitor and obtain a large capacitance value, attempts have been made to construct a structure using tantalum oxide, which has a high dielectric constant, as a dielectric material. FIG. 6 is a cross-sectional view of an example of a capacitor formed using tantalum oxide as a dielectric material. - form, formation, and capacity.
また誘電体層としてタンタルとシリコンと酸素の化合物
及びタンタルとシリコンと酸素と窒素の化合物を使った
容量が特開昭５８−１０８５５ 号に発表されている。Further, capacitors using a compound of tantalum, silicon, and oxygen and a compound of tantalum, silicon, oxygen, and nitrogen as a dielectric layer have been published in JP-A-58-10855.
上記した第６図に示すタレタル酸化物を誘電体とする容
量は、タンタル酸化物の誘電率が大きいので、たしかに
大きな容量が得らｎるが、−万洩れ電流が極めて大きく
、装置の高密度化を計る目的からに大きな問題となって
いる。The capacitor using tantalum oxide as a dielectric shown in Fig. 6 above certainly has a large capacitance because the dielectric constant of tantalum oxide is large, but the leakage current is extremely large and the density of the device is high. This has become a major problem for the purpose of measuring economic growth.
従って、本発明の第１の目的に洩れ電流のすくないタン
タルの化合物を使った容量を具備する半導体装（ｔを提
供することにある。Accordingly, a first object of the present invention is to provide a semiconductor device (t) having a capacitance using a tantalum compound with low leakage current.
−万、誘電体としてタンタルとシリコンと酸素の化合物
もしくはタンタルとシリコンと酸素と窒素の化合物を使
用すれば洩れ電流は大幅に小さくすることができるが、
それにともない誘電率は小さくなってしまう。従って装
置の小型化、高密度化を達成するためには誘電ｙ＄金あ
まりさげることなく、かつ洩ｎ電流のすくないタンタル
金含む誘電体層並びにその構造が望まれていた。- If a compound of tantalum, silicon, and oxygen or a compound of tantalum, silicon, oxygen, and nitrogen is used as the dielectric, the leakage current can be significantly reduced.
As a result, the dielectric constant becomes smaller. Therefore, in order to achieve miniaturization and high density of devices, a dielectric layer containing tantalum gold and its structure that does not require much sacrifice of dielectric gold and has low leakage current has been desired.
本発明者は’Ｉ’ａｚｏｓ膜中に混入する８ｉ０２の量
と電気特性の関係について第３図の関係があることを知
った。第２図は誘電率および耐圧（定量のリーク電流が
流れるときの電圧）が８１０２の混入量に対し変化する
様子を示したものであり、 ８ｉ０ｚ混入量が多くなる
と耐圧は改善さするが、誘電率が著しく低下することを
示している。そこで本発明者は一つの誘電体に２つの層
を形成することを考えた。The inventor of the present invention has found that the relationship between the amount of 8i02 mixed in the 'I'azos film and the electrical characteristics is as shown in FIG. 3. Figure 2 shows how the dielectric constant and withstand voltage (voltage when a certain amount of leakage current flows) change with the amount of 8102 mixed in. As the amount of 8i0z added increases, the withstand voltage improves, but the dielectric constant This shows that the rate decreases significantly. Therefore, the inventor considered forming two layers in one dielectric.
従りて、本発明の第２の目的は、誘電率を大きくさげる
ことなく、かつ洩れ電流の小さいタンタル化合物を誘電
体とする容量を具備する半導体装置を提供することにあ
る。Therefore, a second object of the present invention is to provide a semiconductor device having a capacitance using a tantalum compound as a dielectric material, which does not significantly reduce the dielectric constant and has a small leakage current.
本発明の＠１の発明の半導体装置は、半導体基板又は電
極の表面にタンタルを含む化合物よりなる誘電体層、電
極を積層して形成された容量を具備する半導体装置にお
いて、前記誘電体層がタンタルとアルミニウムと酸素と
の化合物より構成される。The semiconductor device of the invention @1 of the present invention is a semiconductor device including a capacitor formed by laminating a dielectric layer made of a compound containing tantalum and an electrode on the surface of a semiconductor substrate or an electrode, wherein the dielectric layer is Composed of a compound of tantalum, aluminum, and oxygen.
また、本発明の第２の発明の半導体装置は、半導淳基板
又に電極の表面にタンタルを含む化合物よりなる誘電体
層、電極を積層して形成さｎた容量を具備する半導体装
置において、前記誘電体層にタンタルに対し化合物を形
成する物質の混入量が膜内部では少く、膜の表裏並びに
端部では多く含んで構成さｎる。Further, a semiconductor device according to a second aspect of the present invention is a semiconductor device having a capacitance formed by laminating a dielectric layer made of a compound containing tantalum and an electrode on the surface of a semiconductor substrate or an electrode. The amount of the substance that forms a compound with respect to tantalum in the dielectric layer is small in the interior of the film, and large in the front and back surfaces and edges of the film.
なお、第２の発明の誘電体層としてにタンタルとシリコ
ンと酸素の化合物、又はタンタルとアルミニウムと酸素
とからなる化合物、又はタンタルとシリコンと酸素と窒
素とからなる化合物を適用することに工す効果を発揮す
ることができる。Note that it is possible to apply a compound of tantalum, silicon, and oxygen, a compound of tantalum, aluminum, and oxygen, or a compound of tantalum, silicon, oxygen, and nitrogen as the dielectric layer of the second invention. It can be effective.
以下、本発明の実施例について５図面を参照して説明す
る。第１図は本発明の第１の実施例の断面図であり、ｎ
チャ／ネルＭＯｆ９構造のダイナミックＲＡＭＣ）メモ
リセルの断ｒＭｔ−示す。第１図において、１）はＰ型
のシリコン基板、１２１）！素子領域を分離するフィー
ルド酸化膜、１３および１４はｎ型の高濃度不純物領域
、１５はゲート酸化膜。Embodiments of the present invention will be described below with reference to five drawings. FIG. 1 is a cross-sectional view of a first embodiment of the present invention, with n
A diagram of a dynamic RAMC memory cell with a channel/channel MOf9 structure is shown. In FIG. 1, 1) is a P-type silicon substrate, 121)! A field oxide film isolating the element regions, 13 and 14 are n-type high concentration impurity regions, and 15 is a gate oxide film.
１６［多結晶シリコン等よりなるゲート電極、１７は誘
電体層％ １８は電極、１９は絶縁層をそれぞれ示す。16 is a gate electrode made of polycrystalline silicon or the like, 17 is a dielectric layer, 18 is an electrode, and 19 is an insulating layer.
上記第１図において、誘電体層１７とその上下に配設さ
れた不純物領域１４および電極１８とに工９％容量が構
成されることは周知である。この容量の誘電体層１７は
、従来Ｓム０冨が多く使われていたが、本賽施例ではこ
れをタンタル（Ｔａ）、アルミニウム（九〇、酸素（０
２）の化合物Ｔａ ｘＡｊｙＯｚを用いて形成した。In FIG. 1, it is well known that the dielectric layer 17, the impurity regions 14 and the electrodes 18 disposed above and below the dielectric layer 17 have a 9% capacitance. For the dielectric layer 17 of this capacitance, S0000 was often used in the past, but in this example it is made of tantalum (Ta), aluminum (0000), oxygen (0000), etc.
It was formed using the compound TaxAjyOz of 2).
上記ＴａｘＡｌｙＯｚ 工９なる誘電体層１７を形成
する方法に、特に限定する必！！にないが、その一方法
としてはコ愉スパッタ（Ｃｏ−＠ｐｕｔ ｔｌｒ） 法
ｒ用いることでア今。即ち通常のコ・スパッタ法におい
て、それぞれ酸化タンタル（Ｔ３ｘＯｓ）および酸化ア
ルミニウム（ＡｔｚＯａ）よりなる２個のターゲットを
用いｎばよい。There is no particular limitation on the method of forming the dielectric layer 17 using the above-mentioned TaxAlyOz process. ! However, one method is to use the Co-@put tlr method. That is, in the usual co-sputtering method, two targets each made of tantalum oxide (T3xOs) and aluminum oxide (AtzOa) may be used.
またＴａｙＡｔｙＣ）ｚエフなる誘電体層を形成する他
の方法は気相成長法を用いることである。例えばＴａＣ
ｌ３およびＡｔ（ＣＨｘ ） ａ ｔ−反応炉に導き酸
素と反応させｎば工い。Another method for forming the dielectric layer is to use a vapor phase growth method. For example, TaC
l3 and At(CHx)at- are introduced into a reactor and reacted with oxygen.
このように、 ＴａｘＡｊｙＯｚ よりなる誘電体層
管用いて形成した容量は比誘電率が通常用いられるＳｉ
ｎｇのそれの数倍大きいため、同一容量値を得る面積を
極めて小さくすることができる。さらに本発明によるＴ
ａｘＡｌｙＯｚｌｌｌＪｄ洩れ電流が１０−’Ａ以下と
極めで小さい九め半導体装置の高密度化用の容量の誘電
体膜として十分効果を発揮できる。In this way, the capacitance formed using the dielectric layer tube made of TaxAjyOz has a relative dielectric constant of Si, which is normally used.
Since it is several times larger than that of ng, the area for obtaining the same capacitance value can be made extremely small. Furthermore, T according to the present invention
It has an extremely small leakage current of 10-'A or less, and can be sufficiently effective as a capacitor dielectric film for increasing the density of semiconductor devices.
第２図は本発明の第２賽施例の容量の誘電体層の組成構
造全説明するための図であり、膜内部の８ｉ、０又はＳ
ｉ、ｑＮ又に人１．０の混入量を示している。図から明
らかなように、Ｓｉ、Ｏ又はＳｊ、Ｏ。FIG. 2 is a diagram for explaining the entire compositional structure of the dielectric layer of the capacitor in the second embodiment of the present invention.
i, qN also shows the amount of contamination of 1.0 people. As is clear from the figure, Si, O or Sj, O.
Ｎ又にＡ４０の混入量は膜内部では少く、膜の表裏で多
い。即ち膜内部では８ｉ、０もしくは８ｉ、０゜Ｎもし
くはＡｔ、 Ｏの混入量を少く、比誘電率を高め、膜の
表裏では反応による洩れ電流の増加を防止するために前
記物質の混入量を多くしである。The amount of N or A40 mixed inside the membrane is small, but is large on the front and back sides of the membrane. In other words, the amount of 8i, 0, 8i, 0°N or At, O mixed inside the film is reduced to increase the dielectric constant, and the amount of the above substances mixed on the front and back surfaces of the film is reduced in order to prevent an increase in leakage current due to reaction. There are many.
上記膜構造の誘電体層を形成する方法は特に限定する必
要框ないが、その一方法としては前記したようにコ・ス
パッタ法金用いることである。即ち通常のスパッタ法に
おいてＴａ２０ｇと８ｉ０２もしくにＴ幻ＯＢとん１０
３工９なる２個のターゲットを用いればよく、混入量を
変えるｖｃは２個の゛ターゲットに加わるパワーを変え
るとか、半導体装置のそれぞれのターゲットに対する露
出時間金変えること等にエリ容易Ｖｃ賽施できる。Although there is no need to limit the method of forming the dielectric layer having the above-mentioned film structure, one method is to use the co-sputtering method as described above. That is, in the normal sputtering method, Ta20g and 8i02 or T phantom OBton 10
It is sufficient to use two targets of 3 and 9, and Vc can be easily used to change the amount of mixture, such as changing the power applied to the two targets or changing the amount of exposure time for each target of the semiconductor device. can.
まｔ、他の方法としては、気相成長法を用い。Another method is vapor phase growth.
膜形底時間に対し、Ｓｉ、０もしくに８ｉ、ｑＮもしく
はＡ４０ｔ−含むガスの反応炉への導入量全変化させる
ことｉｃより容易に本発明に用いる誘電体層を形成する
ことができる。The dielectric layer used in the present invention can be more easily formed by changing the total amount of Si, 0, 8i, qN, or A40t-containing gas introduced into the reactor with respect to the film bottom time.
なお、以上説明した誘電体層を適用したダイナオ、りＲ
ＡＭのメモリセルに第１図と全く同一構造でよく、その
容量に、誘電体層のみを層の表裏には８４．０又はＳｔ
、０．Ｎ又はＡｊ、 ０の混入量を多く、膜内部では少
くなった構造のタンタル化合物としており、高濃度不純
物１４と電極１８とから構成されている。In addition, Dynao and RiR to which the dielectric layer described above is applied
The AM memory cell may have exactly the same structure as shown in Fig. 1, and its capacitance requires only a dielectric layer and 84.0 or St.
,0. A tantalum compound having a structure in which a large amount of N or Aj, 0 is mixed and a small amount inside the film is used, and is composed of a high concentration impurity 14 and an electrode 18.
第４図は本発明の第３の実施例の断面図である。FIG. 4 is a sectional view of a third embodiment of the invention.
本実施例は本発明に係る容量を用いて作成した他のダイ
ナミックＲＡＭのメモリセルである。本実施例において
は誘電体層１７と共にその誘電体層１７と高濃度不純物
領域１４の間にシリサイド層２０が挿入されており容量
の信頼性をより向上させることができる。図においては
第１図と同一部分は同一符号で示しである。This example is another dynamic RAM memory cell fabricated using the capacitor according to the present invention. In this embodiment, a silicide layer 20 is inserted together with the dielectric layer 17 between the dielectric layer 17 and the high concentration impurity region 14, so that the reliability of the capacitance can be further improved. In the figure, the same parts as in FIG. 1 are indicated by the same reference numerals.
第５図は本発明の第４の実施例のｇＩ部部面面図あり、
本発明に係る容量金量いて作成した他のダイナミックＲ
ＡＭのメモリセルを示す。なお、図において、第１図〜
第４図と同一部分は同一符号で示しである。本実施例で
は、容量部が半導体基板１）０表面に設けられた凹部に
形成されており。FIG. 5 is a partial sectional view of the gI section of the fourth embodiment of the present invention,
Other dynamic R created using capacitive metal according to the present invention
An AM memory cell is shown. In addition, in the figure, Figure 1~
The same parts as in FIG. 4 are indicated by the same reference numerals. In this embodiment, the capacitor portion is formed in a recess provided on the surface of the semiconductor substrate 1)0.
容量部の面積ｔ−冥効的に広くすることに工り大きな容
量値金得ることができる。A large capacitance value can be obtained by effectively increasing the area t of the capacitor section.
このように形成した上記実施例のダイナミックＲＡＭは
前記した組成、Ｗ造の誘電体層を用いているため、誘電
率の低下が少なく、従りそ容量を小屋にすることができ
る之め、当該容量を用いた装置を高密度化することがで
きる。Since the dynamic RAM of the above embodiment formed in this manner uses a dielectric layer having the composition described above and made of W, the decrease in dielectric constant is small and the capacitance can be reduced. Devices using capacitance can be densified.
以上説明したように、本発明によれば、誘電体層みして
りｌタルとアルオニウムと酸素からなるりｌタルの化合
物ＴａｘＡｔｙｏｚ を用いることによりこれを用いた
容量に比誘電率が通常用いられる８ｉｏｎの数倍大きい
ため同一容量値を得るＣＩ積を極めて小さくすることが
できると共に、洩れ電流も極めて小さくすることができ
る。As explained above, according to the present invention, by using the dielectric layer TaxAtyoz, which is a compound of tal, tal, alonium, and oxygen, the relative dielectric constant is normally used for the capacitance using this. Since it is several times larger than 8 ions, the CI product for obtaining the same capacitance value can be made extremely small, and the leakage current can also be made extremely small.
また、誘電体層として夕／タルとシリコント酸素からな
る化合物、もしくは夕／タルとシリコンと酸素と窒素か
らなる化合物、もしくに夕／タルとアルミニウムと酸素
とからなる化合物のいず几かを誘電体として用いながら
も比誘電率の低下がすくなく、かつ洩れ電流の極めて少
い容量が実現できるため本発明の主ｇｋｓの容量ｔ−構
成要素として具備する半導体装置を高密度化することが
できる。In addition, as a dielectric layer, a compound consisting of tal, silicon, oxygen, or tal, a compound consisting of tal, silicon, oxygen, and nitrogen, or a compound consisting of tal, aluminum, and oxygen may be used. Although it is used as a dielectric, it is possible to realize a capacitance with a small decrease in dielectric constant and an extremely small leakage current, so that the semiconductor device provided as the capacitance t-component of the main gks of the present invention can be highly densified. .
第１図に本発明の一実施例の断面図、ＩＮ２図は本発明
の主要部である誘電体膜の組成構造を説明するための図
、第３図に本発明の原理説明用ＯＴ ａ ２０ｓとＳ
ｉ０２ の比率とコ／デ／ザ特性との関係を示す図、第
４図、′ｌＸ５図にそれぞれ本発明の他の実施例の断面
図、第６図は従来例の断面図である。
ｌ・・・・・・Ｐ型シリコン基板、２・・・・・・誘電
体層、３・・・・・・多結晶シリコン層、１）・・・・
・・Ｐ型シリコン基板、１２−−−−＝７４−にド酸化
膜、１３，１４，１４ａ・・・・・・高濃度不純物領域
、１５・・・・・・ゲート酸化膜、１６・・・・・・多
結晶シリコン％ １７，１７８・・・・・・誘電体層、
１８，１８１・・・・・・電極、１９・・・・・・絶縁
層、２０．２０ａ・・・・・・シリサ・イド層。
亨１頂
Ｎｆ表位ドブづの（Ｅ麹
矛２８２Ｉ
牛３＠
′￥−４回
￥２回Fig. 1 is a sectional view of an embodiment of the present invention, Fig. IN2 is a diagram for explaining the composition structure of a dielectric film which is the main part of the present invention, and Fig. 3 is an OT a 20s for explaining the principle of the present invention. and S
FIGS. 4 and 1X5 are cross-sectional views of other embodiments of the present invention, and FIG. 6 is a cross-sectional view of a conventional example. l...P-type silicon substrate, 2...dielectric layer, 3...polycrystalline silicon layer, 1)...
...P-type silicon substrate, 12----=74- doped oxide film, 13, 14, 14a...high concentration impurity region, 15...gate oxide film, 16... ...Polycrystalline silicon% 17,178...Dielectric layer,
18,181...electrode, 19...insulating layer, 20.20a...silicide layer. Toru 1 top Nf surface Dobuzuno (E Kojiko 282I Ushi 3 @ ′ ¥ - 4 times ¥ 2 times
Claims (1)
物よりなる誘電体層、電極を積層して形成された容量を
具備する半導体装置において、前記誘電体層がタンタル
とアルミニウムと酸素との化合物よりなることを特徴と
する半導体装置。（２）半導体基賠又は電極の表面にタ
ンタルを含む化合物よりなる誘電体層、電極を積層して
形成された容量を具備する半導体装置において、前記誘
電体層はタンタルに対し化合物を形成する物質の混入量
が膜内部では、少く、膜の表裏並びに端部では多く含ま
れることを特徴とする半導体装置。 （３）誘電体層がタンタルとシリコンと酸素からなる化
合物、又はタンタルとアルミニウムと酸素からなる化合
物、又はタンタルとシリコンと酸素と窒素からなる化合
物である特許請求の範囲第（２）項記載の半導体装置。[Scope of Claims] (1) A semiconductor device having a capacitor formed by stacking a dielectric layer made of a compound containing tantalum and an electrode on the surface of a semiconductor substrate or an electrode, wherein the dielectric layer is made of tantalum and aluminum. A semiconductor device comprising a compound of and oxygen. (2) In a semiconductor device including a dielectric layer made of a compound containing tantalum on the surface of a semiconductor substrate or an electrode, and a capacitor formed by laminating electrodes, the dielectric layer is a substance that forms a compound with tantalum. 1. A semiconductor device characterized in that a small amount of . (3) Claim (2), wherein the dielectric layer is a compound consisting of tantalum, silicon, and oxygen, or a compound consisting of tantalum, aluminum, and oxygen, or a compound consisting of tantalum, silicon, oxygen, and nitrogen. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59277448A JPS61156865A (en) | 1984-12-28 | 1984-12-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59277448A JPS61156865A (en) | 1984-12-28 | 1984-12-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61156865A true JPS61156865A (en) | 1986-07-16 |
Family
ID=17583714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59277448A Pending JPS61156865A (en) | 1984-12-28 | 1984-12-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61156865A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6281752A (en) * | 1985-10-07 | 1987-04-15 | Oki Electric Ind Co Ltd | Semiconductor memory device |
| JPS632363A (en) * | 1986-06-20 | 1988-01-07 | Nec Corp | Capacity film |
| US5541454A (en) * | 1990-05-31 | 1996-07-30 | Canon Kabushiki Kaisha | Semiconductor device containing electrostatic capacitive element and method for manufacturing same |
| EP0880167A3 (en) * | 1997-05-23 | 1998-12-02 | Lucent Technologies Inc. | Capacitor comprising improved ta0x-based dielectric |
| JP2001230386A (en) * | 1999-12-22 | 2001-08-24 | Hynix Semiconductor Inc | Semiconductor device including high dielectric capacitor dielectric and method of manufacturing the same |
| JP2008252118A (en) * | 1998-03-12 | 2008-10-16 | Lucent Technol Inc | Electronic component with doped metal oxide dielectric material and process for making electronic component with doped metal oxide dielectric material |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54133089A (en) * | 1978-04-06 | 1979-10-16 | Nec Corp | Thin film capacitor and its manufacture |
| JPS5519855A (en) * | 1978-07-28 | 1980-02-12 | Nec Corp | Thin film condenser and manufacture thereof |
| JPS5810855A (en) * | 1981-07-14 | 1983-01-21 | Fujitsu Ltd | semiconductor equipment |
| JPS59114863A (en) * | 1982-12-22 | 1984-07-03 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1984
- 1984-12-28 JP JP59277448A patent/JPS61156865A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54133089A (en) * | 1978-04-06 | 1979-10-16 | Nec Corp | Thin film capacitor and its manufacture |
| JPS5519855A (en) * | 1978-07-28 | 1980-02-12 | Nec Corp | Thin film condenser and manufacture thereof |
| JPS5810855A (en) * | 1981-07-14 | 1983-01-21 | Fujitsu Ltd | semiconductor equipment |
| JPS59114863A (en) * | 1982-12-22 | 1984-07-03 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6281752A (en) * | 1985-10-07 | 1987-04-15 | Oki Electric Ind Co Ltd | Semiconductor memory device |
| JPS632363A (en) * | 1986-06-20 | 1988-01-07 | Nec Corp | Capacity film |
| US5541454A (en) * | 1990-05-31 | 1996-07-30 | Canon Kabushiki Kaisha | Semiconductor device containing electrostatic capacitive element and method for manufacturing same |
| EP0880167A3 (en) * | 1997-05-23 | 1998-12-02 | Lucent Technologies Inc. | Capacitor comprising improved ta0x-based dielectric |
| JP2008252118A (en) * | 1998-03-12 | 2008-10-16 | Lucent Technol Inc | Electronic component with doped metal oxide dielectric material and process for making electronic component with doped metal oxide dielectric material |
| JP2001230386A (en) * | 1999-12-22 | 2001-08-24 | Hynix Semiconductor Inc | Semiconductor device including high dielectric capacitor dielectric and method of manufacturing the same |
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