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JPS6115217A - Cut-off controller for application of power supply - Google Patents

Cut-off controller for application of power supply

Info

Publication number
JPS6115217A
JPS6115217A JP59134605A JP13460584A JPS6115217A JP S6115217 A JPS6115217 A JP S6115217A JP 59134605 A JP59134605 A JP 59134605A JP 13460584 A JP13460584 A JP 13460584A JP S6115217 A JPS6115217 A JP S6115217A
Authority
JP
Japan
Prior art keywords
signal
cut
time
power supply
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59134605A
Other languages
Japanese (ja)
Inventor
Yoshiki Shimoma
下間 芳樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59134605A priority Critical patent/JPS6115217A/en
Publication of JPS6115217A publication Critical patent/JPS6115217A/en
Pending legal-status Critical Current

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  • Direct Current Feeding And Distribution (AREA)
  • Power Sources (AREA)

Abstract

PURPOSE:To control the cut-off time point for application of a power supply according to the state of a load by supplying the output signal of a comparator to a computer to decide the propriety of the cut-off operation by an operating system of the computer and delivering a command signal based on the result of said decision. CONSTITUTION:A comparator 4b transmits the time coincidence signal to an external unit via a signal line 7 when the coincidence is obtained between the output of a timepiece 3 and the contents of a register 2. The external unit knows a scheduled cut-off time point of the power supply from the signal on the line 7 and then decides the propriety of the cut-off of the power supply. If the cut- off is possible, the external unit delivers a power supply cut-off command signal via a signal line 8 to control a control circuit 5. In the case of a computer, the interruption is applied to the computer by the signal on the line 7. Thus a deciding program is started to decide whether or not an operating system processed all jobs. Then the signal on the line 8 is outputted to the circuit 5.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は電子計算機などの電源を自動的に投入、切断
する電源投入切断制御装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a power on/off control device that automatically turns on and off the power of a computer or the like.

〔従来技術〕[Prior art]

第1図は従来の電源投入切断制御装置の一例を示すブロ
ック図である。図においてfil 、 +2)aそれぞ
れレジスタ、(3)は時刻を表すディジタル符号を出力
する時計であって、たとえば、カウンタと、このカウン
タに1秒ごとに1本のパルスを入力するパルス発生器か
ら構成される。(4a) 、 (4b)はそれぞれ比較
器、(5)は制御回路、(6)は外部に対して出力され
る接点信号であり、この接点信号によって外部の所定の
装置に対する電源の投入、切断を制御する。
FIG. 1 is a block diagram showing an example of a conventional power on/off control device. In the figure, fil, +2)a are registers, and (3) is a clock that outputs a digital code representing the time, for example, from a counter and a pulse generator that inputs one pulse every second to this counter. configured. (4a) and (4b) are comparators, (5) is a control circuit, and (6) is a contact signal output to the outside, and this contact signal turns on and off power to a predetermined external device. control.

レジスタ(1)(この明細書では第1のレジスタという
)には第1の時刻を表すディジタル符号を設定し、レジ
スタ(2)(この明細書では第2のレジスタという)に
は第2の時刻を表すディジタル符号を設定し、時計(3
)の出力がレジスタ(1)の内容と合致したとき、比較
器(4&)  ti信信号出出力て制御回路(5)を制
御し接点信号(6)を閉接して、外部の所定の装置に電
源が投入される。同様に1時計(3)の出力がレジスタ
(2)の内容と合致したとき、比較器(4b)は信号を
出力して制御回路(5)を制御し接点信号(6)を開放
して、上記外部の所定の装置の電源が切断される。
A digital code representing the first time is set in register (1) (referred to as the first register in this specification), and a second time is set in register (2) (referred to as the second register in this specification). Set the digital code representing the clock (3
) matches the contents of the register (1), the comparator (4&) outputs a signal to control the control circuit (5), closes the contact signal (6), and connects it to a predetermined external device. Power is turned on. Similarly, when the output of the 1 clock (3) matches the contents of the register (2), the comparator (4b) outputs a signal to control the control circuit (5) and open the contact signal (6). The power of the predetermined external device is cut off.

第1図に示すよう々従来の装置は、たとえば、照明の点
灯、消灯の制御には便利であるが、上記外部の所定の装
置が電子計算機であるような場合には適していない。電
子計算機を無人運転して所定の作業を実施するよう々場
合には、電源の投入は、あらかじめ設定された時刻通り
に行うことができても、電源切断の時刻は、すべての必
要な処理が完了するまで延期しなければならない。すな
わち、その計算機に投入されたジョブの量によって電源
を切断できる時刻が変化し、電源を切断するための最終
的な判断は、電源投入切断制御装置−&けでは行うこと
ができず、従って第1図に示す装置は、電子計算機のよ
うにその装置自体の中に判断機構を備えていて動作する
、いわゆるインテリジェンシ(intelligene
y )  の高い装置に対しては使用できないという欠
点があった。
Although the conventional device shown in FIG. 1 is convenient for controlling lighting on and off, for example, it is not suitable for cases where the predetermined external device is a computer. When a computer is operated unattended to perform a specified task, even if the power can be turned on at a preset time, the power may be turned off at the time when all necessary processing has been completed. It must be postponed until completed. In other words, the time at which the power can be turned off changes depending on the amount of jobs input to the computer, and the final decision to turn off the power cannot be made by the power on/off control device. The device shown in Figure 1 is a so-called intelligent device that operates by being equipped with a judgment mechanism within itself, like an electronic computer.
It has the disadvantage that it cannot be used for devices with high y).

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除去するた
めになされたもので、この発明では第1図の比較器(4
b)の出力によって直ちに電源を切断するという制御は
行わず、比較器(4b)の出力信号を計算機に入力しそ
のO8(オペレーティングシステム)によって電源切断
のり否を判断させ、その判断結果による指令信号により
制御回路(5)を制御することにした。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above.
The output signal of the comparator (4b) is not controlled to immediately turn off the power by the output of b), but the output signal of the comparator (4b) is input to the computer, and the O8 (operating system) judges whether or not to turn off the power, and the command signal is generated based on the judgment result. It was decided to control the control circuit (5) by the following.

〔発明の実施例〕[Embodiments of the invention]

以下この発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第2図はこの発明の一実施例を示すブロック図であって
、第1図と同一符号は同−又は相当する部分を示し、(
7) 、 (81はそれぞれ信号線である。
FIG. 2 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and (
7) and (81 are signal lines, respectively.

第2図において第1図と同一符号の部分は第1図の場合
と同様に動作するので重複した説明は省略する。時計(
3)の出力がレジスタ(2)の内容と一致したとき比較
器(4b)は時刻一致信号を信号線(7)を介して外部
装置に伝える。外部装置は信号線(7)上の信号により
ミ源切断予定時刻となったことを知り、電源切断の可否
を判断した後、切断可能であれば信号線(8)を介して
電源切断指令信号を出力し制御回路(5)を制御する。
In FIG. 2, parts having the same reference numerals as those in FIG. 1 operate in the same manner as in FIG. 1, so a redundant explanation will be omitted. clock(
When the output of 3) matches the contents of the register (2), the comparator (4b) transmits a time match signal to the external device via the signal line (7). The external device learns from the signal on the signal line (7) that the scheduled time to disconnect the power source has arrived, determines whether it is possible to disconnect the power, and then sends a power disconnect command signal via the signal line (8) if it is possible to disconnect the power. is output to control the control circuit (5).

計算機の例で言えば、信号線(7)上の信号によって計
算機に割込みがかけられ、判断プログラムが起動され、
O8がすべてのジープを処理し終えたか否かを判定して
信号線(8)上の信号を出力する。
In the example of a computer, the signal on the signal line (7) interrupts the computer and starts the judgment program.
The O8 determines whether all the jeeps have been processed and outputs a signal on the signal line (8).

第2図に示すレジスタfil 、 f2)は、外部から
任意の時刻を設定することができるメモリとしての一般
的な形のものを示したが、ROM(読出し専用メモリ、
機械的スイッチを使用するROMを含む)のような半固
定的なメモリを使ってもよいので、この明細書において
レジスタという範囲には上記圏も含むものとする。
The registers fil, f2) shown in FIG. 2 are of a general form as a memory that can set any time from the outside, but they can also be used as ROM (read-only memory,
A semi-permanent memory such as a ROM (including a ROM using a mechanical switch) may also be used, so in this specification, the term "register" includes the above-mentioned category.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、あらかじめ設定された
時刻に外部装置の電源を投入、切断し装置の自動運転を
行うことができるだけでなく、その時の当該外部装置の
負荷の状況に合せて電源切断時刻を制御することができ
る。たとえば電子計算機において、電源切断予定時刻を
示す信号が入力された時点でジョブの残りがなければそ
の時点で電源を切断し、ジョブの残りがあれば、その残
り全部を完了した後電源切断指令信号を出力することが
できる。
As described above, according to the present invention, it is possible not only to automatically operate the device by turning on and off the power to the external device at preset times, but also to automatically operate the device according to the load status of the external device at that time. Cutting time can be controlled. For example, in a computer, if there are no remaining jobs when a signal indicating the scheduled power-off time is input, the power is turned off at that point, and if there are remaining jobs, the power is turned off after completing all remaining jobs. can be output.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の装置を示すブロック図、第2図はこの発
明の一実施例を示すブロック図である。 (1)・・・第1のレジスタ、(2)・・・第2のレジ
スタ、(3)・・・時計、(4a)・・・第1の比較器
、(4b)・・・第2の比較器、(5)・・・制御回路
、(6)・・・接点信号、(7) 、 (8)・・・そ
れぞれ信号線。 尚、各図中同一符号は同−又は相当部分を示す。
FIG. 1 is a block diagram showing a conventional device, and FIG. 2 is a block diagram showing an embodiment of the present invention. (1)...first register, (2)...second register, (3)...clock, (4a)...first comparator, (4b)...second comparator, (5)...control circuit, (6)...contact signal, (7), (8)...respectively signal line. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 時刻を表すディジタル符号を発生する時計、第1の時刻
を表すディジタル符号が設定される第1のレジスタ、第
2の時刻を表すディジタル符号が設定される第2のレジ
スタ、上記第1のレジスタの内容と上記時計の出力とを
比較し両者が一致したとき時刻一致信号を出力する第1
の比較器、上記第2のレジスタの内容と上記時計の出力
とを比較し両者が一致したとき時刻一致信号を出力する
第2の比較器、上記第1の比較器の出力する時刻一致信
号により所定の電源を投入し、上記第2の比較器の出力
する時刻一致信号を上記所定の電源により動作する所定
の装置に送出し、この送出した信号に対する上記所定の
装置からの応答信号により上記所定の電源を切断するよ
う制御する手段を備えた電源投入切断制御装置。
a clock that generates a digital code representing time; a first register in which a digital code representing a first time is set; a second register in which a digital code representing a second time is set; A first unit that compares the content with the output of the clock and outputs a time matching signal when the two match.
A second comparator that compares the contents of the second register with the output of the clock and outputs a time coincidence signal when the two match, and a time coincidence signal output from the first comparator. A predetermined power source is turned on, a time coincidence signal outputted from the second comparator is sent to a predetermined device operated by the predetermined power source, and a response signal from the predetermined device to the sent signal causes the time matching signal to be outputted from the second comparator. A power on/off control device comprising means for controlling the power off of the device.
JP59134605A 1984-06-29 1984-06-29 Cut-off controller for application of power supply Pending JPS6115217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59134605A JPS6115217A (en) 1984-06-29 1984-06-29 Cut-off controller for application of power supply

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59134605A JPS6115217A (en) 1984-06-29 1984-06-29 Cut-off controller for application of power supply

Publications (1)

Publication Number Publication Date
JPS6115217A true JPS6115217A (en) 1986-01-23

Family

ID=15132305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59134605A Pending JPS6115217A (en) 1984-06-29 1984-06-29 Cut-off controller for application of power supply

Country Status (1)

Country Link
JP (1) JPS6115217A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642907U (en) * 1987-06-25 1989-01-10

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642907U (en) * 1987-06-25 1989-01-10

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