JPS61150415A - Push-pull output integrated circuit - Google Patents

Abstract

PURPOSE:To avoid consumption of useless electric power by setting a flowing current at a level equal to the charging/discharging current obtained when the voltage of a capacitor is changed by a level between logical valves '1' and '0'. CONSTITUTION:When a rectangular signal supplied to an input terminal 1 changes to '0' from '1', a signal Vc differentiated by a capacitor C is obtained and impressed to the base of a pnp transistor TRT4. As the coincidence is obtained between Vdd and GND for the voltage direction of the signal Vc, the voltage is impressed to the base of the TRT4 so that a deep vias is applied to said base from an OFF state. Thus the TRT4 is turned on to charge the gate capacity of a TRT3. When the input signal is changed to '1' from '0', a TRT2 is turned on and the gate capacity of the TRT3 is drawn out in the form oaf a drain current. Then the TRT3 is turned off. In other words, both TRT3 and T2 are turned on and off according to the change of the input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pushable output integrated circuit, and more particularly to a pushable output integrated circuit connected to a low voltage logic section.

(Prior Art) Conventionally, many high-voltage push-pull output circuits have been used in which two N-channel MOS transistors are used in the output section. This is because the N-channel MOS)9 transistor has advantages over the P-channel MO8 transistor in terms of operating speed and current capacity, and the high-voltage P,N
This is because it is difficult to integrate both channel MOS transistors on the same semiconductor substrate.

FIG. 2 is a circuit diagram of an example of a conventional push-nable output circuit.

A signal is input from signal input terminal 1 and the high voltage N-channel MOS transistor T! When turned on, N channel M
OS) Register T2 is turned off by inverter INV. By turning on the MOS transistor Tt, the high voltage side power supply V
Current flows from DD through resistor R and R2, and resistor R1
Due to the voltage drop, the base and emitter of the 6pNP transistor T4 are biased, the transistor T4 is turned on, and the collector voltage of the transistor T4, that is, the N-channel MO8) and the gate potential of the yin resistor T3 become almost the same as the power supply voltage VDD. At this time, the gate voltage up to the Zener voltage of the Zener diode D between the gate and source of the transistor T3 is applied between the gate and source of the transistor T3, acts as a gate voltage, turns on the transistor T3, and supplies current to the load. do.

When the polarity of the input signal is reversed, transistor T1 is turned off and transistor T is turned on, drawing current from the load via a path from Zener diode D through transistor T2.

(Problems to be Solved by the Invention) In such a circuit, if the resistors R1, R2, etc. are formed using an integrated circuit, they can only have a resistance of about 10Ω due to area constraints. Since power consumption increases as the square of the voltage being handled, when the voltage becomes high, the problem arises that the circuit of FIG. 2 consumes too much power and cannot be used.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a low power consumption push-pull output integrated circuit that eliminates unnecessary power consumption.

(Means for Solving the Problems) The pushinable output integrated circuit of the present invention includes a capacitor whose one end is connected to a signal input terminal, and a PNP whose base is connected to the other end of the capacitor and whose emitter is connected to a high-voltage power supply.
a transistor, and an N-channel first M0 whose gate is connected to the signal input terminal, whose source is connected to the low-voltage power supply, and whose drain is connected to the collector of the PNP transistor.
8); a second N-channel MOS transistor whose gate is connected to the collector of the PNP transistor, whose source is connected to the output terminal, and whose drain is connected to the high-voltage power supply; and whose cathode is connected to the collector of the PNP transistor. The anode is connected to the output terminal and the second MOS
The transistor includes a Zener diode connected to the source of the transistor.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This embodiment includes a capacitor C whose one end is connected to the signal input terminal 1, a PNP transistor T4 whose base is connected to the other end of the capacitor C and whose emitter is connected to the high voltage side power supply VDD K, and whose gate is connected to the signal input terminal 1. A first N-channel MOS transistor T2 has a source connected to the low voltage side power supply GND and a drain connected to the collector of the PNP transistor T4, and a gate connected to the collector of the P]'IP transistor T4 and a source connected to the output terminal 2. The second N-channel whose drain is connected to the high voltage side power supply VDD
It is configured to include an MOS transistor T3 and a Zener diode D whose cathode is connected to the collector of the PNP transistor T4 and whose anode is connected to the output terminal 2 and the source of the second MOS transistor T3.

Next, the operation of this embodiment will be explained. It is assumed that a rectangular wave signal as shown in the figure is input to the signal input terminal 1. When this signal changes from '1' to '0', this change is differentiated by capacitor C, resulting in a signal V as shown in the figure.
This signal Vc (PNP) is applied to the base of the transistor T4. In FIG. 1, since the direction of the voltage of the signal Vc is made to match the direction of VDD and GND, a voltage is applied so that the base of transistor 4 is deeply biased from the off state. This turns on PNP transistor T4, and transistor T3
The transistor T3 is turned on.

Even if this differential waveform disappears and the PNP transistor T4 is turned off, the gate capacitance of the transistor T3 remains charged, so it continues to be on.

The next input voltage change, that is, the input signal changes from '0' to 1
”, the transistor T2 turns on, the gate capacitance of the transistor T3 is drawn out as the drain current of T2, and the transistor T3 turns off. That is, depending on the change in the input signal, the transistor T3.Tz
will turn on and off.

The current flowing at this time is such that the voltage of capacitor C is logic "1"
The charging/discharging current when the level changes between "0" and "0" is extremely small, and #1 almost no power consumption is involved. It has been found through experiments that the capacitance of such a capacitor C may be 0.1 to IPF, which is a value that can be incorporated into an integrated circuit.

(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a push-pull output integrated circuit that eliminates wasteful power consumption, reduces power consumption, and can be incorporated into an integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional push-pull output circuit. 1...Signal input terminal, 2...Output terminal,
C... Capacitor, D... Zener diode, GND... ...Low voltage side power supply, Rt, Rz...Resistance, T1
~T3...N-channel MO8 transistor,
T4...PNP transistor, ■DD...
...High voltage side power supply.

Claims (1)

[Claims] A capacitor whose one end is connected to the signal input terminal, a PNP transistor whose base is connected to the other end of the capacitor and whose emitter is connected to the high-voltage power supply, and a PNP transistor whose gate is connected to the signal input terminal, whose source is connected to the low-voltage power supply, and whose drain is connected to the low-voltage power supply. a first N-channel MOS transistor whose gate is connected to the collector of the PNP transistor, a second N-channel MOS transistor whose gate is connected to the collector of the PNP transistor, whose source is connected to the output terminal, and whose drain is connected to the high-voltage power supply.
a MOS transistor, a cathode connected to the collector of the PNP transistor and an anode connected to the output terminal and the second
A push-pull output integrated circuit comprising: a Zener diode connected to a source of a MOS transistor.