JPS61150246A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61150246A JPS61150246A JP59271013A JP27101384A JPS61150246A JP S61150246 A JPS61150246 A JP S61150246A JP 59271013 A JP59271013 A JP 59271013A JP 27101384 A JP27101384 A JP 27101384A JP S61150246 A JPS61150246 A JP S61150246A
- Authority
- JP
- Japan
- Prior art keywords
- plastic
- semiconductor device
- chip
- stage
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は通信装置、電子計算装置などの電子回路に用い
られる半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device used in electronic circuits such as communication devices and electronic computing devices.
従来より通信装置、電子計算装置等の電子回路には半導
体集積回路をプラスチックでパッケージングした半導体
装置が用いられている。この半導体装置のパッケージン
グ工程は、予め半導体集積回路チップを搭載するステー
ジおよび多数の端子用リードをタイバーで連結したリー
ドフレームを金属板より打抜き形成しておき、このリー
ドフレームのステージにチップをグイボンディングし、
次いでチップの電極とリード間を細線にてワイヤボンデ
ィングし、次いでリードの一部およびチップをプラスチ
ックでモールドしたのち、タイバーを切断し、リードを
折曲する諸工程より成っている。従ってパッケージ後の
半導体装置は第３図の断面図に示すように上からプラス
チック１、チップ２、ステージ３、プラスチック１の４
層構造となる。なお４はリード、５は細線である。2. Description of the Related Art Semiconductor devices in which semiconductor integrated circuits are packaged in plastic have conventionally been used in electronic circuits such as communication devices and electronic computing devices. In the packaging process of this semiconductor device, a stage on which a semiconductor integrated circuit chip is mounted and a lead frame, in which a number of terminal leads are connected with tie bars, are punched out of a metal plate in advance, and the chip is guided onto the stage of this lead frame. bonding,
Next, the electrodes of the chip and the leads are wire-bonded using thin wires, then part of the leads and the chip are molded with plastic, and then the tie bars are cut and the leads are bent. Therefore, as shown in the cross-sectional view of FIG.
It has a layered structure. Note that 4 is a lead and 5 is a thin wire.
上記の構成のものにあっては、チップを搭載したステー
ジ３が金属であるためモールドした樹脂１と熱膨張係数
が大きく違い、そのため温度の変化により熱応力が発生
し、搭載したチップ２にクラックを発生させるという問
題があった。In the structure described above, since the stage 3 on which the chip is mounted is made of metal, its coefficient of thermal expansion is significantly different from that of the molded resin 1, and as a result, thermal stress is generated due to temperature changes, causing cracks in the mounted chip 2. There was a problem in that it caused
本発明は、上記問題点を解消した半導体装置を提供する
もので、その手段は、半導体集積回路が形成されたチッ
プをステージの上に搭載し、プラスチソクでモールドし
た半導体装置において、前記ステージはプラスチックで
形成されたものであることを特徴とする半導体装置によ
ってなされる。The present invention provides a semiconductor device that solves the above-mentioned problems.The present invention provides a semiconductor device in which a chip on which a semiconductor integrated circuit is formed is mounted on a stage, and the stage is molded with plastic. The present invention is made by a semiconductor device characterized in that it is formed of.
上記半導体装置は、ステージがプラスチックで形成され
たものであるため、外周にモールドしたプラスチックと
熱膨張率の差は無いか又は僅少となる。従って温度の変
化により発生する熱応力は小さくなり、チップのクラッ
ク発生は防止される。In the above semiconductor device, since the stage is made of plastic, there is no or only a slight difference in coefficient of thermal expansion from the plastic molded on the outer periphery. Therefore, thermal stress caused by temperature changes is reduced, and cracks in the chip are prevented.
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図に本発明の半導体装置を断面図として示す。FIG. 1 shows a cross-sectional view of a semiconductor device of the present invention.
本実施例は、第１図の如くチップ１０がプラスチック製
のステージ１１の上に搭載され、リード１２との間にワ
イヤ１３によりワイヤボンディングされた後、全体がプ
ラスチック１４によりモールドされたも、のである。In this embodiment, a chip 10 is mounted on a plastic stage 11 as shown in FIG. be.
以上のような半導体装置は例えば次のようにしく３）
て作成される。すなわち、まず第２図ａの如くリード２
０をタイバー２１で連結して形成したリードフレーム２
２と、第２図すの如くリード２０が嵌合される四部２３
を有するプラスチック製のステージ２４を用意する。次
に第２図Ｃの如（リードフレーム２２とステージ２４を
はめ込み又は接着剤により接合し、さらにステージ２４
上にＡｇペーストによりデツプ２５を接着する。その後
の工程は従来と同様にしてワイヤボンディング、プラス
チックモールド後、リードフレーム２２のタイバーを切
断し、リード２０を規定の寸法に折曲して完成する。The semiconductor device as described above is manufactured, for example, in the following manner 3). That is, first, as shown in Fig. 2a, lead 2 is
Lead frame 2 formed by connecting 0 with tie bars 21
2, and a fourth part 23 into which the lead 20 is fitted as shown in Figure 2.
A plastic stage 24 is prepared. Next, as shown in FIG.
A depth 25 is bonded on top with Ag paste. The subsequent steps are the same as in the past, after wire bonding and plastic molding, the tie bars of the lead frame 22 are cut, and the leads 20 are bent to a specified size to complete the process.
このように形成された本実施例は第１図の断面図に示す
ように上からプラスチック１４、チップ１０、プラスチ
ック製ステージ１１、プラスチック１４があり、材料的
にはプラスチック、シリコン、プラスチックの三層構造
となる。従って熱応力が減小しチップのクラックは防止
される。As shown in the cross-sectional view of FIG. 1, this embodiment formed in this way includes, from the top, a plastic 14, a chip 10, a plastic stage 11, and a plastic 14. In terms of materials, there are three layers of plastic, silicon, and plastic. It becomes a structure. Therefore, thermal stress is reduced and chip cracking is prevented.
以上説明したように本発明によれば、ステージがプラス
チックであるため、外周にモールドしたプラスチックと
熱膨張の差が無くなるか又は僅小となるため、温度変化
により発生する熱応力は少なくなり、チップのクランク
発生を防止することができる。As explained above, according to the present invention, since the stage is made of plastic, the difference in thermal expansion from the plastic molded on the outer periphery is eliminated or minimized, so thermal stress generated due to temperature changes is reduced, and the chip It is possible to prevent the occurrence of cranking.
第１図は本発明の半導体装置の一実施例を示す断面図、
第２図は本発明の実施例の半導体装置の作成法を説明す
るための図、第３図は従来の半導体装置を示す断面図で
ある。
図中、１０はチップ、１１はステージ、１２はリード、
１３はワイヤ、】４はプラスチックモールドをそれぞれ
示す。FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention;
FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a sectional view showing a conventional semiconductor device. In the figure, 10 is a chip, 11 is a stage, 12 is a lead,
13 indicates a wire, and ]4 indicates a plastic mold, respectively.
Claims (1)
に搭載し、プラスチックでモールドした半導体装置にお
いて、前記ステージはプラスチックで形成されたもので
あることを特徴とする半導体装置。1. A semiconductor device in which a chip on which a semiconductor integrated circuit is formed is mounted on a stage and molded with plastic, characterized in that the stage is made of plastic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59271013A JPS61150246A (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59271013A JPS61150246A (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61150246A true JPS61150246A (en) | 1986-07-08 |
Family
ID=17494190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59271013A Pending JPS61150246A (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61150246A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6412560A (en) * | 1987-07-07 | 1989-01-17 | Nec Corp | Semiconductor device |
| US5840599A (en) * | 1989-06-30 | 1998-11-24 | Texas Instruments Incorporated | Process of packaging an integrated circuit with a conductive material between a lead frame and the face of the circuit |
-
1984
- 1984-12-24 JP JP59271013A patent/JPS61150246A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6412560A (en) * | 1987-07-07 | 1989-01-17 | Nec Corp | Semiconductor device |
| US5840599A (en) * | 1989-06-30 | 1998-11-24 | Texas Instruments Incorporated | Process of packaging an integrated circuit with a conductive material between a lead frame and the face of the circuit |
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