JPS61148670A - Brake release signal generating device - Google Patents

Abstract

PURPOSE:To remove necessity for the frequency generator and to use the most part of a circuitry in common for the revolutionary speed controlling system of a motor by so forming the system that a brake release signal is obtained when the period of the digital signal reed out from a disc continues to be of a value larger than a prescribed value for a specified period. CONSTITUTION:An RS flip flop circuit 27 is made in set state by a pulse LP1. If the output of a period detecting circuit 25 is in low level during one period TA of the pulse LP1, the RS flip flop circuit 27 is maintained in the set state. And, an AND circuit 29 closes its gate, thereby preventing the pulse LP2 from passing through it. Therefore, the circuit 30 is never reset. If this state is continued for a time N2-fold of the period TA i.e. for the period TB, the Q-output of an RS flip flop circuit 30 is kept at the high level for the said period of time. In result, the Q-output of a D flip flop circuit 31 becomes high level by the timing of a pulse LP4.

Description

Detailed Description of the Invention [Technical Field of the Invention] This invention relates to brake release signal generation and control in a digital disc player. [Technical Background of the Invention] This invention converts an audio signal into digital PCM as a digital data signal, Digital audio discs (DAD) are recorded on discs using unevenness caused by pit rows, and digital disc players that detect the pit rows of this disc and reproduce the original audio signals have been developed.

With ζ and ζ rotors, such disk strips and rows are recorded using a constant linear velocity method (CLV). For this reason, for example, when tracking a row of pins with an optical pickup element, the disk is driven such that its rotational speed decreases as the optical pickup element moves from the inner circumference to the outer circumference of the disk. . This rotational speed control is performed by extracting a synchronization signal synchronized with each frame of the digital data signal from the frequency component of the digital data signal read from the disc, and adjusting the frequency of the synchronization signal to a predetermined frequency so that the frequency of each disc is adjusted to a predetermined frequency. This is done by controlling the rotation speed.

Here, if the above synchronization signal cannot be obtained, such as when the motor starts rotating or when the pickup element is moved at high speed, the period (one period or half period) of the digital data signal read from the disk is ) is detected and the rotation of the disk motor is controlled so that this value becomes a predetermined value, thereby making the linear velocity of the pit row constant.

In such a digital disc player, the rotating disc motor is stopped by driving the disc motor with a brake/4' pulse having the opposite polarity to the drive pulse of the disc motor. In such a configuration, if the brake torque is not released at a predetermined timing after applying brake torque to the disc motor, the disc motor will rotate in reverse.

Conventionally, a circuit as shown in FIG. 6 has been used as a circuit for generating a brake release signal for releasing the brake torque. In the figure, each time the motor 12 that rotationally drives the disk 11 rotates once, the frequency generator (FG)
) 23 outputs N arm pulses Pl (N is a positive integer).

This output/mother pulse Ps (see FIG. 7(a)) is frequency-divided by two in the frequency dividing circuit 14, and the pulse Ps shown in FIG. 7(b) is
! It is said that The timing generation circuit 15 uses this /4 pulse P.
Clear counter 16 in synchronization with - / Shinrusu CL (7th
(see figure (e)), latch circuit 17, chi/hiresu LP
(see FIG. 7(d)).

When the counter I6 is cleared by the clear pulse CL, the reference clock CK from the reference clock generation circuit 18 is
count. This count value is latched into the child circuit 17 according to the latch pulse LP. As a result, the latch circuit 17 has a count value of about one cycle of the clear pulse CL, in other words, a count value of about two cycles of the output/arm pulse P1 of the frequency generator 13. be touched. ff! latched by latch circuit 17) [N
(see Fig. 7 (@)) becomes larger than a predetermined value, that is, when the rotational speed of the motor 12 becomes low, the decoder 19 outputs a brake release signal Sm (see Fig. 7 (f)).
)) is output.

[Problems with background technology]

However, the above configuration requires a frequency generator 13 and a circuit dedicated to generating a brake release signal, resulting in an increase in the number of components of the player.

[Purpose of the invention]

The present invention was made in order to cope with the above-mentioned situation, and an object of the present invention is to provide a frequency generator without requiring a frequency generator.

[Summary of the invention]

The present invention is configured to obtain a brake release signal when the period of the digital data signal read from the disk continues to be greater than a predetermined period for a predetermined period.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. The output of an optical pickup element 23 that reads digital data signals from a disk 21 that is rotationally driven by a motor 22 is given to a recording signal processing circuit 24 . The recording signal processing circuit 24 extracts a digital data signal (EFM signal) So from the output of the pickup element 23. This digital data signal SD is input to the period detection circuit 25, and the time length of each one cycle is measured using the reference clock signal and the reference clock signal CK with the period T from the reference clock signal generator circuit 26. Then, the period detection circuit 25 outputs a low level pulse P1 when the time length of each period is less than a predetermined value MT (where M is a positive integer) and is equal to or more than (M+1)T. . The details of the operation of the period detection circuit 25 will be described later.

The output/4 pulse Pa of the period detection circuit 25 is given as a reset input R to the RS flip, pflo, de circuit 27. The set input S of this RS flip-flop circuit 27 is the pulse LP output from the timing generation circuit 28.
, is given.

The timing generation circuit 28 converts the digital data signal S, outputted from the recording signal processing circuit 24 into Nl (for example, N,
= 128), and ΔRus L P 1 * LPI (second
Figure (a) (see bl) is obtained. Furthermore, the timing generation circuit 28 generates these i4 pulses L P 1 +LP,
Divide the frequency by Nz (for example, N value = 16) and calculate the value L
P s * L Pa (Figure 2 (c), (d)
).

Here, the phase of /Yars L P HIL P a is delayed by about one period with respect to the pulse L P @ r L P s K, respectively.

RS free, the output of the deflop circuit 27 and the pulse LP,
is input to the AND circuit 29, and the output of this AND circuit 29 becomes the reset input R of the RS free f floor 1 circuit 30. R87.

The Q output of the Gufrodde circuit 30 becomes the D input of the D input, differential opening, and f circuit 31. The set input S of the RS flip-flop circuit 30 is a pulse LP.

, D flip-flop, clock manual C of circuit 31
K is / 臂Rus LP4. Then, the Q output of the D flip-flop circuit 31 becomes the brake release signal S.

The operation in the above configuration will be explained. RS free, deflo,
The f circuit 27 is set in the /4 pulse LP, and the RS
Free, def 0. The f circuit 30 is brought into a set state by pulses L and P output at the same timing as the pulse LPl.

Here, the RS fly, pflo, g circuit 30 is /9rus LP
, the phase of the pulse LP is delayed by about one period f t
D free, defro, decircuit 3 at the timing of 4rus LP4
The Q output of 1 becomes high and low. The Q output of the D-flip flow lag circuit 31 is used as a brake release signal as described above, but the brake torque is released using the Q output.
It is done at the timing when the output becomes high level.

RS fly, f floor lag circuit 30 is Norusu LP.

The set state is maintained over one period TI of when the output pulse P1 of the period detection circuit 25 is always at a low level between and. That is, RS free, defro,
The 'f circuit 27 is put into a set state by the /4' pulse LPH, but if the output of the period detection circuit 25 is low during one cycle Tm of this pulse LP1, the RS-flip and Pflode circuits 27 are set. The set state is maintained.As a result, the AND circuit 29 closes P-T and the pulse LP2 cannot pass through this AND circuit 29, so the RS flip-defrozzo circuit 30 is not reset.This state is the N of the period TA. : If it continues for the period TB, the Q output of the RS free, defro, de circuit 30 will be kept at high level during this period, so the D free, pfrog circuit 31
The Q output becomes high level at the timing of pulse LP4.

On the other hand, if the output/4' pulse P1 of the period detection circuit 25 becomes irregular even once during the period Tm of the period Tm, the digital data signal will not be detected during the period Tm. If a state in which one period is less than or equal to MT occurs even once, the RS Furi, Pflo, and De circuit 27 then/or the RUS LP.
It remains in the reset state until , is output. As a result, /Yars LP.

The RS flip-flop circuit 27
The Q output of becomes high level and the AND circuit 29 becomes f-)
Since the circuit 30 is opened, the RS free, defro, defro circuit 30 is reset by the pulse LP. R87 Ritsu defro,
Once the output circuit 30 is set, the /4 pulse LP
Since the set state is not set until 3 is output, the D flip flow,
The Q output of the f circuit 31 never becomes high level.

In this way, in the circuit of FIG. 1, the digital data signal s
N of D, a state in which one period of the digital data signal is less than or equal to MT does not occur even once in the period Tm, and this is N.
When this happens twice, a brake release signal Sm is output. Digital data signal s, +7)
When the time length of each cycle is equal to or greater than (M+1)T over NI XN2 cycles, the brake release signal SA is output.

Now, if the minimum period of the digital data signal when the disk 21 rotates normally is 6T and M is 22, then 6T is 23T.
When the rotation period of the disc 21 becomes 3.8 times the normal rate, the brake release signal S is output. Explain using.

In the tiIJa diagram, the pulses CLA and SPA input to terminals 1m and 2* are shown in Figure 4 (a), (b), (c
), this signal is synchronized with the rising edge of the digital data signal sD. /4 input to terminals 3a and 4a
'Rus CLB, SPB are shown in Figure 4 (a), (d), (
As shown in el, the falling edge of the digital data signal SO is synchronized with the falling edge of the digital data signal SO.

The counter 5a is cleared by the clock CLA and the reference clock given from the terminal 6a (FIG. 4(f)) CK
count. Similarly, 1 force counter 7m is pulse CLB
The clock is cleared and the reference clock CK is counted. The counter 5a measures one cycle from the rising edge of the digital data signal So to the next rising edge, and the counter 7a measures one cycle from one falling edge to the next falling edge. Judgment circuits 8* and 9* are each counter 5*
If the time-converted output of the count value of , 7m is less than MT, a high level signal is output.

By the way, in the mode of measuring one cycle of the digital data signal SD, the /4 pulse CNT applied to the terminal 10alC is at a high level. As a result, /4 Lus SP
A and SPB are respectively e-) circuit 11 a 11
2 a through the AND circuit 13&.

Given to 14&. In this case, the digital data signal s
If the time length of one cycle of D is less than or equal to MT, /Yars8PA
, judgment circuit 8m at the timing of 8PB.

Since the output of 9a is at high level, X z4 Luz SPA
, SPB pass through A7p circuits 13* and 14h, respectively. The outputs of these AND circuits JJm and J4m are passed through the OR circuit 15a and given to the RSS free delay circuit 27 as the output signal P1 of the period detection circuit 25.
Reset this.

Although the case where the time length of a cycle is measured in units of one cycle has been described above, it may be measured in units of half a cycle. In this case, the pulse CNT applied to the terminal 10aK is set to low level.

As a result, /4rus SPA and SPB are each r
- AND circuit 14 through the AND circuit 12m + 11m
a.

13a. Then, if the half cycle from the rising edge to the falling edge of the digital data signal 81) is less than or equal to MT, the output of the determination circuit 8a becomes high level, so that the pulse SPB passes through the AND circuit 13a. On the other hand, if the half cycle at i of digital data signal SD is less than or equal to MT, the output of discrimination circuit 9a becomes incorrect, so it passes through AND circuit 14a. .

In this manner, even when measuring a half period of the digital data signal SD, the period detection circuit 25 shown in FIG. 1 measures two types of half periods, just as when measuring one period. Tebru.

Now, the digital data signal s when the disk 21 rotates normally
When the minimum period of D is 3TS M = 22, when 3T expands to 23T or more, that is, when the rotation period of the disk 21 becomes -T- = 7.7 times the normal time,
This means that the brake release signal S is output.

By the way, in a digital disc player, when the motor 22 starts rotating or when the backup element 23 moves at high speed, the period of the reproduced digital data signal (1
motor 2 so that the period or half period) becomes a predetermined value.
As described above, the linear velocity of the pit row is kept constant by controlling the rotational speed of the pit row.

The brake release signal generating device of the present invention can be constructed very simply by using the rotational speed control device for keeping the linear velocity of the pit row constant.

This will be explained below. Figure IE5 is a circuit diagram showing the configuration of the rotational speed control device. The period detection circuit 31 has KT (T
When a maximum period greater than or equal to one period of the reference black, the output black of the signal generation circuit 32, and the signal CK is detected, the output pulse Pb becomes high level. /? output from the timing generation circuit 33? Luz LP1 * LPs * LP3 *
LP4 is the same as that output from the timing generation circuit 28 described above.

The R8 flip-flop circuit 34 is reset by the mother pulse LPI, and the maximum period is K (T
), the set state is reached.

The RS flip-flo, de circuit 36 is set at /Yars LPs, and even once during the period TI, the RS flip-flo,! If the output of the flop circuit 3401 is incorrect, the /4 pulse LP passes through the AND circuit 35, so it is reset.

RS Furi, Pflo.

D7 the Q output of the decircuit 36, deflo, f circuit 37VC
Give as D input. This D free, differential 0dd circuit 37
The fact that the Q output is at a high level means that the maximum period of the digital data signal SD is greater than or equal to KT.

When the period of the digital data signal becomes extremely long due to noise, etc., the RS flip-flop circuit 34 is mistakenly set to the set state, but when it returns to normal, the i output of the RE flip-flop circuit 34 becomes low level. becomes. Unless the noise etc. continues during the period TI? )、Raysu、
The f-flow and decircuits 36 are not set, reducing the influence of noise.

Note that the rotational speed of the motor 22 is controlled by the Q output of the D-free and defrode circuit 31.

Here, if the output pulse of the period detection circuit Pb is inverted by half,
Since this inverted output becomes -irrepel below (K-1)T, this half-inverted output can be used in place of the output pulse P of the period detection circuit 25 in FIG.

Therefore, the period detection circuit 25 and timing generation circuit 28 in FIG. 1 can be used in combination with the period detection circuit 31 and timing generation circuit 33 in FIG. The only circuits required are three free and defrode circuits and one AND circuit.

〔Effect of the invention〕

As described above, according to the present invention, a frequency generator is not required and most of the circuit is omitted.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a timing chart for explaining the operation in Figure 1, Figure 3 is a circuit diagram showing an example of a specific configuration of the period detection circuit in Figure 2, and Figure 4 is for explaining the operation in Figure 3. Fig. 5 is a circuit diagram for explaining the effect of Fig. 1, Fig. 6 is a circuit diagram showing a conventional brake release signal generator, and Fig. 7 explains the operation of Fig. 6. This is a timing chart for 21... Disc, 22... Motor, 23... Bic A, de-element, 24... Recording signal processing circuit, 25...
...Period detection circuit, 26...Reference clock generation circuit,
27.30...R8 free, defrodder circuit, 29...
・AND circuit, 28...timing generation circuit, 31・
...D flip-flop circuit.

Claims (1)

[Claims] In a digital disc player that reads the digital data signal from a disc on which the digital data signal is recorded, a cycle for detecting whether the cycle of the digital data signal read from the disc is larger than a predetermined value. a detection means; a second detection means for detecting whether or not a detection output indicating that the period is greater than the predetermined value is continuously obtained from the period detection means over a predetermined period; When a detection result indicating that the cycle is greater than the predetermined value is obtained continuously over the predetermined period, a brake release signal is generated to release the brake torque of the motor that rotationally drives the disk. A brake release signal generation device comprising brake release signal generation means.