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JPS6114739A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6114739A
JPS6114739A JP59135485A JP13548584A JPS6114739A JP S6114739 A JPS6114739 A JP S6114739A JP 59135485 A JP59135485 A JP 59135485A JP 13548584 A JP13548584 A JP 13548584A JP S6114739 A JPS6114739 A JP S6114739A
Authority
JP
Japan
Prior art keywords
package
semiconductor device
lead
lead terminals
transparent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59135485A
Other languages
Japanese (ja)
Inventor
Toshihiko Minami
南 俊彦
Yuji Kajiyama
梶山 雄次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59135485A priority Critical patent/JPS6114739A/en
Publication of JPS6114739A publication Critical patent/JPS6114739A/en
Pending legal-status Critical Current

Links

Classifications

    • H10W46/00
    • H10W46/601
    • H10W46/607
    • H10W72/07551
    • H10W72/50
    • H10W72/5449
    • H10W74/00
    • H10W90/756

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素子チップがパッケージ内に収納され
て成る半導体装置に関し、特に、透明材料により形成さ
れたパッケージ音用いて成る半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a semiconductor element chip is housed in a package, and more particularly to a semiconductor device in which a package is formed of a transparent material.

〔従来の技術〕[Conventional technology]

電子部品としての半導体装置は、取扱い性、チップの保
護、配線基板への装着等の観点より、一般にパッケージ
に収納された形態で供給されている。このパッケージと
しては、金属パッケージ、セラミック・パッケージ、樹
脂封止パッケージ等の種々のものが知られている。
2. Description of the Related Art Semiconductor devices as electronic components are generally supplied in a packaged form from the viewpoint of ease of handling, chip protection, mounting on a wiring board, and the like. Various types of packages are known, such as metal packages, ceramic packages, and resin-sealed packages.

ここで、第4図および第5図は、上述のような半導体装
置のそれぞn互いに異なる従来例を示す斜視図である。
Here, FIGS. 4 and 5 are perspective views showing different conventional examples of the semiconductor device as described above.

これらの第4図、第5図において、リード端子(いわゆ
るピン)M、52が突出しており、これらのリード端子
あるいはピンのうちの基準となる端子、例えばいわゆる
第1ピン等全表示するためのマークとして、谷パッケー
ジ41.51にはそ九ぞれ例えば凹部43.53が形成
されている。
In these figures 4 and 5, lead terminals (so-called pins) M, 52 are protruding, and among these lead terminals or pins, reference terminals, such as the so-called first pin, etc., are used to display all of them. As a mark, each valley package 41.51 is formed with, for example, a recess 43.53.

すなわち、第4図の例では、1ビン表示マークとなる凹
部43に最も近いピン42Aが第1ピンであり、また第
5図の例では、切欠凹部53を上方に配置したときのト
ング・ビューにおける左上端のピン52Aが第1ビンと
なる。
That is, in the example of FIG. 4, the pin 42A closest to the recess 43 serving as the 1-bin display mark is the first pin, and in the example of FIG. The pin 52A at the upper left end becomes the first bin.

ところで、例えば受光素子や発光素子等のように、半導
体素子チップに対して外部光を照射したリ、あるいは半
導体素子チップからの光音外部に導出する必要がある場
合には、上記パッケージの少くとも半導体素子チップと
対応する部分を透明とした構造が用いられるが、パッケ
ージの一部に透明材料會用いることによる構造の複雑化
ケ避けたい場合や、部品全体ケ小型化したい場合等にお
いては、パノクージ全体ka明材料で形成することも行
わバでいる。
By the way, when external light is irradiated onto a semiconductor element chip, such as a light receiving element or a light emitting element, or when it is necessary to lead light sound from the semiconductor element chip to the outside, at least one of the above packages is used. A structure in which the part corresponding to the semiconductor element chip is transparent is used, but if you want to avoid complicating the structure by using transparent material for part of the package, or if you want to miniaturize the entire component, panocouples are used. It is also possible to form the entire structure from a transparent material.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このような全体が透明なパッケージ音用いた半導体装置
において、上述した第1ビン等の基準となるリード端子
全表示するために、例えばパッケージ表面に四部や凸部
等を形成しても、パッケージが透明であるため表面の凹
凸が判読し難いという欠点がある。これは、半導体装置
の取扱い時のみならず、配線基板に装着した後でも、パ
ッケージ下部の配線パターンが透けて見えるため、パッ
ケージ表面の凹凸と配線パターンとが視覚的に判別し難
い。そこで、透明パッケージ表面に基準ビン表示用のイ
ンク・マーク會記載することも考えられるが、運搬、取
扱い時等に上記インク・マークのインクによりパッケー
ジ表面が汚れ、受光効率や発光効率等が低下したり、場
合によっては誤動作の原因ともなる虞扛がある。
In a semiconductor device using such a completely transparent package sound, even if four parts or convex parts are formed on the package surface in order to display all the lead terminals that serve as the reference for the first bin, etc., the package will not be visible. Since it is transparent, it has the disadvantage that it is difficult to read the irregularities on the surface. This is because the wiring pattern at the bottom of the package is visible not only when handling the semiconductor device but also after it is mounted on a wiring board, making it difficult to visually distinguish between the unevenness on the package surface and the wiring pattern. Therefore, it may be possible to write an ink mark on the surface of the transparent package to indicate the reference bottle, but the ink of the above ink mark may stain the package surface during transportation and handling, reducing light receiving efficiency and light emitting efficiency. In some cases, there is a risk that this may cause malfunction.

本発明は、このような実情に鑑み、簡単な構成で透明パ
ッケージ下部いた半導体装置の第1ビン等の基準リード
端子の表示が行え、表面が汚nる虞れがなく、明瞭に基
準ビンの判別が行えるとともに、パッケージの表からの
みならず裏からも基準ビンの判別が行えるような半導体
装置の提供を目的とする。
In view of these circumstances, the present invention has a simple configuration that allows the reference lead terminals of the first bin, etc. of a semiconductor device located at the bottom of a transparent package to be displayed, and the reference lead terminals of the reference bin can be clearly displayed without the risk of contaminating the surface. It is an object of the present invention to provide a semiconductor device that can perform identification and also allows identification of a reference bottle not only from the front side of a package but also from the back side.

〔問題点全解決するための手段〕[Means to solve all problems]

すなわち、本発明に係る半導体装置の特徴は、複数本の
リード端子(いわゆるビン)に接続された半導体素子チ
ップが透明パッケージ内に収納されて成る半導体装置に
おいて、複数本のリード端子のうちの基準となるリード
端子、例えば第1ピンの透明パッケージ内部の形状會、
他のリード端子とは異なった視覚的に容易に区別し得る
形状とし、すなわち例えば第1ピンの内部リード部にの
み円形孔を穿設して、基準リード端子表示(例えば1ビ
ン表示)全行うことである。
That is, the feature of the semiconductor device according to the present invention is that in a semiconductor device in which a semiconductor element chip connected to a plurality of lead terminals (so-called bins) is housed in a transparent package, a standard among the plurality of lead terminals is The shape of the lead terminal, for example, the inside of the transparent package of the first pin,
The shape is different from other lead terminals and can be easily distinguished visually, for example, a circular hole is drilled only in the internal lead part of the first pin, and all reference lead terminals are displayed (for example, 1-bin display). That's true.

〔作用〕[Effect]

したがって、透明パッケージ内部の各リード端子の形伏
塗透かして見たときに、第1ピン等の基準リード端子の
形状が他の端子の形状と異なっており、視覚的に容易に
区別できるため、基準リード端子の判別がパッケージ表
面からも裏面からも確実に行える。また、パッケージ表
面にインク・マーク等を印刷する必要がなく、表面がイ
ンクにより汚れる虞れがない。
Therefore, when viewed through the shape coating of each lead terminal inside the transparent package, the shape of the reference lead terminal such as the first pin is different from the shape of other terminals and can be easily distinguished visually. The reference lead terminal can be reliably identified from both the front and back sides of the package. Furthermore, there is no need to print ink marks or the like on the surface of the package, and there is no risk that the surface will be stained with ink.

〔実施例〕〔Example〕

第1図は本発明の第1の実施例となる半導体装置會示す
平面図である。この第1図において、例えば透明樹脂よ
り成る透明パッケージ1内に封止された半導体素子チッ
プ2には、複数個のワイヤ・ボンディング用電極バンド
3が形成されており、これらのボンディング・バンド3
とリード端子4の端部とは、ボンディング・ワイヤ5全
介して電気的に接続されている。リード端子4は複数本
、例えば8本設けられており、これらのリード端子4の
うち基準となる端子、例えば第1ビン4Aの透明パッケ
ージ1内部には、他のリード端子と異なった区別し得る
形状として、円形孔6が穿設されている。すなわち、透
明パッケージ1内のり−ド0パターンとして、基準リー
ド端子である第1ビン4A以外のリード端子4には、例
えば四角形状の孔7が穿設されていたり、孔無しの形状
となっているのに対し、第1ビン4Aのみに円形孔6が
形成されている。これらのパッケージ内リード・パター
ンは、透明パッケージ1を透かして外部より明瞭に見る
ことができ、第1ビン4Aの円形孔6會他のリード端子
の形状から明確に区別して判読できる。
FIG. 1 is a plan view showing a semiconductor device assembly according to a first embodiment of the present invention. In FIG. 1, a plurality of wire bonding electrode bands 3 are formed on a semiconductor element chip 2 sealed in a transparent package 1 made of, for example, transparent resin.
and the end of the lead terminal 4 are electrically connected through the entire bonding wire 5. A plurality of lead terminals 4, for example eight, are provided, and among these lead terminals 4, a reference terminal, for example, inside the transparent package 1 of the first bottle 4A, has a terminal that can be distinguished from other lead terminals. As for the shape, a circular hole 6 is bored. That is, as the lead 0 pattern in the transparent package 1, the lead terminals 4 other than the first bin 4A, which is the reference lead terminal, have, for example, a rectangular hole 7 or no hole. On the other hand, the circular hole 6 is formed only in the first bottle 4A. These in-package lead patterns can be clearly seen from the outside through the transparent package 1, and can be clearly distinguished and read from the shapes of the circular holes 6 and other lead terminals of the first bottle 4A.

ここで、上記第1ビン4A’に指示するためのパッケー
ジ内リード形状は、上記円形孔6に限定されず、例えば
第2図に示す本発明の第2の実施例のように、略U字状
の切り欠きllk第1ビン4Aに形成してもよい。この
U字状の切り欠き11も、他のリード端子4のパッケー
ジ内形状に対比して明瞭に区別できることは勿論である
Here, the shape of the lead in the package for directing the first bottle 4A' is not limited to the circular hole 6, but is, for example, approximately U-shaped as in the second embodiment of the present invention shown in FIG. A notch may be formed in the first bottle 4A. Of course, this U-shaped notch 11 can also be clearly distinguished from the shape of the other lead terminals 4 in the package.

次に、第3図は本発明の第3の実施例を示し、半導体素
子チップ2を透明パッケージ1に対して斜めに傾けた例
を示している。この第3の実施例の半導体装置において
も、透明パッケージ1内のリード・パターンとして、基
準リード端子となる例えば第1ピン4Aのみに例えば円
形孔6ケ穿設し、他のリード端子4と視覚的に容易に識
別可能としている。
Next, FIG. 3 shows a third embodiment of the present invention, in which the semiconductor element chip 2 is tilted obliquely with respect to the transparent package 1. Also in the semiconductor device of the third embodiment, as a lead pattern in the transparent package 1, for example, six circular holes are formed only in the first pin 4A, which serves as the reference lead terminal, and the other lead terminals 4 are visually connected to each other. easily identifiable.

なお、本発明は上記実施例のみに限定されるものではな
く、例えば基準となるリード端子は第1ピンに限定され
ず、基準リード端子全表示するための形状も円形孔やU
字状の切り欠きの他に、他のリード端子と視覚的に明瞭
に区別できる形状であれば何でもよい。これは、基準リ
ード端子以外のリード端子金てに円形孔あるいは四角形
孔を穿設し、基準リード端子のみを孔無しとすることも
含むものである。
Note that the present invention is not limited to the above-mentioned embodiments. For example, the reference lead terminal is not limited to the first pin, and the shape for displaying all the reference lead terminals may also be a circular hole or a U.
In addition to the letter-shaped notch, any shape may be used as long as it can be visually distinguished from other lead terminals. This also includes drilling circular or square holes in the lead terminals other than the reference lead terminals, leaving only the reference lead terminals without holes.

〔発明の効果〕〔Effect of the invention〕

本発明に係る半導体装置によnば、透明パッケージ表面
かして見たときに、他の形状と異なる形状のリード端子
、例えば円形孔6の穿設さ扛たものやU字状の切り欠き
11が形成されたもの等全判別することにより、基準と
なるリード端子、例えば第1ピン4A’に明確に認識で
きる。こハは、パッケージが透明であることから、パッ
ケージ表面からのみならず裏面からも同様に第1ピン等
の基準リード端子會明瞭に見分けることができ、ユーザ
がパッケージ會裏面から見ながら使用する場合等でも基
準リード端子の判読が容易に行える。
According to the semiconductor device according to the present invention, a lead terminal having a shape different from other shapes when viewed through the surface of the transparent package, such as a lead terminal with a circular hole 6 cut out or a U-shaped notch, can be seen through the surface of the transparent package. 11, etc., it is possible to clearly recognize the reference lead terminal, for example, the first pin 4A'. Since the package is transparent, the reference lead terminals such as the 1st pin can be clearly distinguished not only from the front side of the package but also from the back side, and when the user uses the package while viewing from the back side. etc., the reference lead terminal can be easily read.

また、透明パッケージ表面に凹凸等を形成する場合に比
べて、視覚的に判別し易く、誤認等が生ずる虞れが無く
、確実な基準リード端子の判読が行える。さらに、透明
パッケージ表面にインク・マーク等を付す場合に比べて
、インクによる汚れ等が生じて感度低下2来すような欠
点も回避できる。
Furthermore, compared to the case where irregularities are formed on the surface of the transparent package, it is easier to visually distinguish the reference lead terminal, there is no possibility of misidentification, and the reference lead terminal can be reliably read. Furthermore, compared to the case where ink marks or the like are attached to the surface of a transparent package, it is possible to avoid drawbacks such as a decrease in sensitivity due to stains caused by ink, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例金示す平面図、第2図は
本発明の第2の実施例會示す平面図、第3図は本発明の
第3の実施例會示す平面図であり、第4図および第5図
はそ扛ぞれ互いに異なる従来例を示す斜視図である。 100.透明パッケージ 2・・・半導体素子テップ 4・・・ リード端子 4A・・・基準リード端子(第1ピン)6・・・円形孔 11・・・ U字状の切り欠き
FIG. 1 is a plan view showing a first embodiment of the invention, FIG. 2 is a plan view showing a second embodiment of the invention, and FIG. 3 is a plan view showing a third embodiment of the invention. , FIG. 4, and FIG. 5 are perspective views showing different conventional examples. 100. Transparent package 2...Semiconductor element tip 4...Lead terminal 4A...Reference lead terminal (first pin) 6...Circular hole 11...U-shaped notch

Claims (1)

【特許請求の範囲】[Claims] 複数本のリード端子に接続された半導体素子が透明パッ
ケージ内に収納されて成る半導体装置において、上記複
数本のリード端子のうちの基準となるリード端子の上記
透明パッケージ内部の形状を他のリード端子とは異なつ
た形状として基準リード端子表示を行うことを特徴とす
る半導体装置。
In a semiconductor device in which a semiconductor element connected to a plurality of lead terminals is housed in a transparent package, the shape inside the transparent package of the reference lead terminal among the plurality of lead terminals is compared to that of the other lead terminals. A semiconductor device characterized in that a reference lead terminal is displayed as a shape different from that of the semiconductor device.
JP59135485A 1984-06-30 1984-06-30 Semiconductor device Pending JPS6114739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59135485A JPS6114739A (en) 1984-06-30 1984-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59135485A JPS6114739A (en) 1984-06-30 1984-06-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6114739A true JPS6114739A (en) 1986-01-22

Family

ID=15152821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59135485A Pending JPS6114739A (en) 1984-06-30 1984-06-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6114739A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246247A (en) * 1989-03-20 1990-10-02 Mitsubishi Electric Corp Semiconductor device
JPH0661410A (en) * 1993-01-25 1994-03-04 Mitsubishi Electric Corp Semiconductor device
US6692404B2 (en) 2001-08-29 2004-02-17 Honda Giken Kogyo Kabushiki Kaisha Engine control system and method for hybrid vehicle
US10351745B2 (en) 2014-12-23 2019-07-16 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particles and method of forming same
US10358589B2 (en) 2015-03-31 2019-07-23 Saint-Gobain Abrasives, Inc. Fixed abrasive articles and methods of forming same
US10364383B2 (en) 2012-01-10 2019-07-30 Saint-Gobain Ceramics & Plastics, Inc. Abrasive particles having complex shapes and methods of forming same
US10428255B2 (en) 2011-12-30 2019-10-01 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particle and method of forming same
US10557067B2 (en) 2014-04-14 2020-02-11 Saint-Gobain Ceramics & Plastics, Inc. Abrasive article including shaped abrasive particles
US10563106B2 (en) 2013-09-30 2020-02-18 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particles and methods of forming same
US10563105B2 (en) 2017-01-31 2020-02-18 Saint-Gobain Ceramics & Plastics, Inc. Abrasive article including shaped abrasive particles
US11718774B2 (en) 2016-05-10 2023-08-08 Saint-Gobain Ceramics & Plastics, Inc. Abrasive particles and methods of forming same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57194559A (en) * 1981-05-27 1982-11-30 Hitachi Ltd Semicondcutor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57194559A (en) * 1981-05-27 1982-11-30 Hitachi Ltd Semicondcutor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246247A (en) * 1989-03-20 1990-10-02 Mitsubishi Electric Corp Semiconductor device
JPH0661410A (en) * 1993-01-25 1994-03-04 Mitsubishi Electric Corp Semiconductor device
US6692404B2 (en) 2001-08-29 2004-02-17 Honda Giken Kogyo Kabushiki Kaisha Engine control system and method for hybrid vehicle
US10428255B2 (en) 2011-12-30 2019-10-01 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particle and method of forming same
US10364383B2 (en) 2012-01-10 2019-07-30 Saint-Gobain Ceramics & Plastics, Inc. Abrasive particles having complex shapes and methods of forming same
US10563106B2 (en) 2013-09-30 2020-02-18 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particles and methods of forming same
US12305108B2 (en) 2013-09-30 2025-05-20 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particles and methods of forming same
US10557067B2 (en) 2014-04-14 2020-02-11 Saint-Gobain Ceramics & Plastics, Inc. Abrasive article including shaped abrasive particles
US10351745B2 (en) 2014-12-23 2019-07-16 Saint-Gobain Ceramics & Plastics, Inc. Shaped abrasive particles and method of forming same
US10358589B2 (en) 2015-03-31 2019-07-23 Saint-Gobain Abrasives, Inc. Fixed abrasive articles and methods of forming same
US11718774B2 (en) 2016-05-10 2023-08-08 Saint-Gobain Ceramics & Plastics, Inc. Abrasive particles and methods of forming same
US10563105B2 (en) 2017-01-31 2020-02-18 Saint-Gobain Ceramics & Plastics, Inc. Abrasive article including shaped abrasive particles

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